git.rot13.org Git - linux/blob - drivers/gpu/drm/tegra/dc.c

   1 /*
   2  * Copyright (C) 2012 Avionic Design GmbH
   3  * Copyright (C) 2012 NVIDIA CORPORATION.  All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/debugfs.h>
  12 #include <linux/iommu.h>
  13 #include <linux/of_device.h>
  14 #include <linux/pm_runtime.h>
  15 #include <linux/reset.h>
  16
  17 #include <soc/tegra/pmc.h>
  18
  19 #include "dc.h"
  20 #include "drm.h"
  21 #include "gem.h"
  22 #include "hub.h"
  23 #include "plane.h"
  24
  25 #include <drm/drm_atomic.h>
  26 #include <drm/drm_atomic_helper.h>
  27 #include <drm/drm_plane_helper.h>
  28
  29 static void tegra_dc_stats_reset(struct tegra_dc_stats *stats)
  30 {
  31         stats->frames = 0;
  32         stats->vblank = 0;
  33         stats->underflow = 0;
  34         stats->overflow = 0;
  35 }
  36
  37 /* Reads the active copy of a register. */
  38 static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset)
  39 {
  40         u32 value;
  41
  42         tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
  43         value = tegra_dc_readl(dc, offset);
  44         tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
  45
  46         return value;
  47 }
  48
  49 static inline unsigned int tegra_plane_offset(struct tegra_plane *plane,
  50                                               unsigned int offset)
  51 {
  52         if (offset >= 0x500 && offset <= 0x638) {
  53                 offset = 0x000 + (offset - 0x500);
  54                 return plane->offset + offset;
  55         }
  56
  57         if (offset >= 0x700 && offset <= 0x719) {
  58                 offset = 0x180 + (offset - 0x700);
  59                 return plane->offset + offset;
  60         }
  61
  62         if (offset >= 0x800 && offset <= 0x839) {
  63                 offset = 0x1c0 + (offset - 0x800);
  64                 return plane->offset + offset;
  65         }
  66
  67         dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset);
  68
  69         return plane->offset + offset;
  70 }
  71
  72 static inline u32 tegra_plane_readl(struct tegra_plane *plane,
  73                                     unsigned int offset)
  74 {
  75         return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset));
  76 }
  77
  78 static inline void tegra_plane_writel(struct tegra_plane *plane, u32 value,
  79                                       unsigned int offset)
  80 {
  81         tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset));
  82 }
  83
  84 bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev)
  85 {
  86         struct device_node *np = dc->dev->of_node;
  87         struct of_phandle_iterator it;
  88         int err;
  89
  90         of_for_each_phandle(&it, err, np, "nvidia,outputs", NULL, 0)
  91                 if (it.node == dev->of_node)
  92                         return true;
  93
  94         return false;
  95 }
  96
  97 /*
  98  * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the
  99  * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy.
 100  * Latching happens mmediately if the display controller is in STOP mode or
 101  * on the next frame boundary otherwise.
 102  *
 103  * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The
 104  * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits
 105  * are written. When the *_ACT_REQ bits are written, the ARM copy is latched
 106  * into the ACTIVE copy, either immediately if the display controller is in
 107  * STOP mode, or at the next frame boundary otherwise.
 108  */
 109 void tegra_dc_commit(struct tegra_dc *dc)
 110 {
 111         tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
 112         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
 113 }
 114
 115 static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
 116                                   unsigned int bpp)
 117 {
 118         fixed20_12 outf = dfixed_init(out);
 119         fixed20_12 inf = dfixed_init(in);
 120         u32 dda_inc;
 121         int max;
 122
 123         if (v)
 124                 max = 15;
 125         else {
 126                 switch (bpp) {
 127                 case 2:
 128                         max = 8;
 129                         break;
 130
 131                 default:
 132                         WARN_ON_ONCE(1);
 133                         /* fallthrough */
 134                 case 4:
 135                         max = 4;
 136                         break;
 137                 }
 138         }
 139
 140         outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
 141         inf.full -= dfixed_const(1);
 142
 143         dda_inc = dfixed_div(inf, outf);
 144         dda_inc = min_t(u32, dda_inc, dfixed_const(max));
 145
 146         return dda_inc;
 147 }
 148
 149 static inline u32 compute_initial_dda(unsigned int in)
 150 {
 151         fixed20_12 inf = dfixed_init(in);
 152         return dfixed_frac(inf);
 153 }
 154
 155 static void tegra_plane_setup_blending_legacy(struct tegra_plane *plane)
 156 {
 157         u32 background[3] = {
 158                 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
 159                 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
 160                 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
 161         };
 162         u32 foreground = BLEND_WEIGHT1(255) | BLEND_WEIGHT0(255) |
 163                          BLEND_COLOR_KEY_NONE;
 164         u32 blendnokey = BLEND_WEIGHT1(255) | BLEND_WEIGHT0(255);
 165         struct tegra_plane_state *state;
 166         u32 blending[2];
 167         unsigned int i;
 168
 169         /* disable blending for non-overlapping case */
 170         tegra_plane_writel(plane, blendnokey, DC_WIN_BLEND_NOKEY);
 171         tegra_plane_writel(plane, foreground, DC_WIN_BLEND_1WIN);
 172
 173         state = to_tegra_plane_state(plane->base.state);
 174
 175         if (state->opaque) {
 176                 /*
 177                  * Since custom fix-weight blending isn't utilized and weight
 178                  * of top window is set to max, we can enforce dependent
 179                  * blending which in this case results in transparent bottom
 180                  * window if top window is opaque and if top window enables
 181                  * alpha blending, then bottom window is getting alpha value
 182                  * of 1 minus the sum of alpha components of the overlapping
 183                  * plane.
 184                  */
 185                 background[0] |= BLEND_CONTROL_DEPENDENT;
 186                 background[1] |= BLEND_CONTROL_DEPENDENT;
 187
 188                 /*
 189                  * The region where three windows overlap is the intersection
 190                  * of the two regions where two windows overlap. It contributes
 191                  * to the area if all of the windows on top of it have an alpha
 192                  * component.
 193                  */
 194                 switch (state->base.normalized_zpos) {
 195                 case 0:
 196                         if (state->blending[0].alpha &&
 197                             state->blending[1].alpha)
 198                                 background[2] |= BLEND_CONTROL_DEPENDENT;
 199                         break;
 200
 201                 case 1:
 202                         background[2] |= BLEND_CONTROL_DEPENDENT;
 203                         break;
 204                 }
 205         } else {
 206                 /*
 207                  * Enable alpha blending if pixel format has an alpha
 208                  * component.
 209                  */
 210                 foreground |= BLEND_CONTROL_ALPHA;
 211
 212                 /*
 213                  * If any of the windows on top of this window is opaque, it
 214                  * will completely conceal this window within that area. If
 215                  * top window has an alpha component, it is blended over the
 216                  * bottom window.
 217                  */
 218                 for (i = 0; i < 2; i++) {
 219                         if (state->blending[i].alpha &&
 220                             state->blending[i].top)
 221                                 background[i] |= BLEND_CONTROL_DEPENDENT;
 222                 }
 223
 224                 switch (state->base.normalized_zpos) {
 225                 case 0:
 226                         if (state->blending[0].alpha &&
 227                             state->blending[1].alpha)
 228                                 background[2] |= BLEND_CONTROL_DEPENDENT;
 229                         break;
 230
 231                 case 1:
 232                         /*
 233                          * When both middle and topmost windows have an alpha,
 234                          * these windows a mixed together and then the result
 235                          * is blended over the bottom window.
 236                          */
 237                         if (state->blending[0].alpha &&
 238                             state->blending[0].top)
 239                                 background[2] |= BLEND_CONTROL_ALPHA;
 240
 241                         if (state->blending[1].alpha &&
 242                             state->blending[1].top)
 243                                 background[2] |= BLEND_CONTROL_ALPHA;
 244                         break;
 245                 }
 246         }
 247
 248         switch (state->base.normalized_zpos) {
 249         case 0:
 250                 tegra_plane_writel(plane, background[0], DC_WIN_BLEND_2WIN_X);
 251                 tegra_plane_writel(plane, background[1], DC_WIN_BLEND_2WIN_Y);
 252                 tegra_plane_writel(plane, background[2], DC_WIN_BLEND_3WIN_XY);
 253                 break;
 254
 255         case 1:
 256                 /*
 257                  * If window B / C is topmost, then X / Y registers are
 258                  * matching the order of blending[...] state indices,
 259                  * otherwise a swap is required.
 260                  */
 261                 if (!state->blending[0].top && state->blending[1].top) {
 262                         blending[0] = foreground;
 263                         blending[1] = background[1];
 264                 } else {
 265                         blending[0] = background[0];
 266                         blending[1] = foreground;
 267                 }
 268
 269                 tegra_plane_writel(plane, blending[0], DC_WIN_BLEND_2WIN_X);
 270                 tegra_plane_writel(plane, blending[1], DC_WIN_BLEND_2WIN_Y);
 271                 tegra_plane_writel(plane, background[2], DC_WIN_BLEND_3WIN_XY);
 272                 break;
 273
 274         case 2:
 275                 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_X);
 276                 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_Y);
 277                 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_3WIN_XY);
 278                 break;
 279         }
 280 }
 281
 282 static void tegra_plane_setup_blending(struct tegra_plane *plane,
 283                                        const struct tegra_dc_window *window)
 284 {
 285         u32 value;
 286
 287         value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 |
 288                 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC |
 289                 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC;
 290         tegra_plane_writel(plane, value, DC_WIN_BLEND_MATCH_SELECT);
 291
 292         value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 |
 293                 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC |
 294                 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC;
 295         tegra_plane_writel(plane, value, DC_WIN_BLEND_NOMATCH_SELECT);
 296
 297         value = K2(255) | K1(255) | WINDOW_LAYER_DEPTH(255 - window->zpos);
 298         tegra_plane_writel(plane, value, DC_WIN_BLEND_LAYER_CONTROL);
 299 }
 300
 301 static bool
 302 tegra_plane_use_horizontal_filtering(struct tegra_plane *plane,
 303                                      const struct tegra_dc_window *window)
 304 {
 305         struct tegra_dc *dc = plane->dc;
 306
 307         if (window->src.w == window->dst.w)
 308                 return false;
 309
 310         if (plane->index == 0 && dc->soc->has_win_a_without_filters)
 311                 return false;
 312
 313         return true;
 314 }
 315
 316 static bool
 317 tegra_plane_use_vertical_filtering(struct tegra_plane *plane,
 318                                    const struct tegra_dc_window *window)
 319 {
 320         struct tegra_dc *dc = plane->dc;
 321
 322         if (window->src.h == window->dst.h)
 323                 return false;
 324
 325         if (plane->index == 0 && dc->soc->has_win_a_without_filters)
 326                 return false;
 327
 328         if (plane->index == 2 && dc->soc->has_win_c_without_vert_filter)
 329                 return false;
 330
 331         return true;
 332 }
 333
 334 static void tegra_dc_setup_window(struct tegra_plane *plane,
 335                                   const struct tegra_dc_window *window)
 336 {
 337         unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
 338         struct tegra_dc *dc = plane->dc;
 339         bool yuv, planar;
 340         u32 value;
 341
 342         /*
 343          * For YUV planar modes, the number of bytes per pixel takes into
 344          * account only the luma component and therefore is 1.
 345          */
 346         yuv = tegra_plane_format_is_yuv(window->format, &planar);
 347         if (!yuv)
 348                 bpp = window->bits_per_pixel / 8;
 349         else
 350                 bpp = planar ? 1 : 2;
 351
 352         tegra_plane_writel(plane, window->format, DC_WIN_COLOR_DEPTH);
 353         tegra_plane_writel(plane, window->swap, DC_WIN_BYTE_SWAP);
 354
 355         value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
 356         tegra_plane_writel(plane, value, DC_WIN_POSITION);
 357
 358         value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
 359         tegra_plane_writel(plane, value, DC_WIN_SIZE);
 360
 361         h_offset = window->src.x * bpp;
 362         v_offset = window->src.y;
 363         h_size = window->src.w * bpp;
 364         v_size = window->src.h;
 365
 366         value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
 367         tegra_plane_writel(plane, value, DC_WIN_PRESCALED_SIZE);
 368
 369         /*
 370          * For DDA computations the number of bytes per pixel for YUV planar
 371          * modes needs to take into account all Y, U and V components.
 372          */
 373         if (yuv && planar)
 374                 bpp = 2;
 375
 376         h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
 377         v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
 378
 379         value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
 380         tegra_plane_writel(plane, value, DC_WIN_DDA_INC);
 381
 382         h_dda = compute_initial_dda(window->src.x);
 383         v_dda = compute_initial_dda(window->src.y);
 384
 385         tegra_plane_writel(plane, h_dda, DC_WIN_H_INITIAL_DDA);
 386         tegra_plane_writel(plane, v_dda, DC_WIN_V_INITIAL_DDA);
 387
 388         tegra_plane_writel(plane, 0, DC_WIN_UV_BUF_STRIDE);
 389         tegra_plane_writel(plane, 0, DC_WIN_BUF_STRIDE);
 390
 391         tegra_plane_writel(plane, window->base[0], DC_WINBUF_START_ADDR);
 392
 393         if (yuv && planar) {
 394                 tegra_plane_writel(plane, window->base[1], DC_WINBUF_START_ADDR_U);
 395                 tegra_plane_writel(plane, window->base[2], DC_WINBUF_START_ADDR_V);
 396                 value = window->stride[1] << 16 | window->stride[0];
 397                 tegra_plane_writel(plane, value, DC_WIN_LINE_STRIDE);
 398         } else {
 399                 tegra_plane_writel(plane, window->stride[0], DC_WIN_LINE_STRIDE);
 400         }
 401
 402         if (window->bottom_up)
 403                 v_offset += window->src.h - 1;
 404
 405         tegra_plane_writel(plane, h_offset, DC_WINBUF_ADDR_H_OFFSET);
 406         tegra_plane_writel(plane, v_offset, DC_WINBUF_ADDR_V_OFFSET);
 407
 408         if (dc->soc->supports_block_linear) {
 409                 unsigned long height = window->tiling.value;
 410
 411                 switch (window->tiling.mode) {
 412                 case TEGRA_BO_TILING_MODE_PITCH:
 413                         value = DC_WINBUF_SURFACE_KIND_PITCH;
 414                         break;
 415
 416                 case TEGRA_BO_TILING_MODE_TILED:
 417                         value = DC_WINBUF_SURFACE_KIND_TILED;
 418                         break;
 419
 420                 case TEGRA_BO_TILING_MODE_BLOCK:
 421                         value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
 422                                 DC_WINBUF_SURFACE_KIND_BLOCK;
 423                         break;
 424                 }
 425
 426                 tegra_plane_writel(plane, value, DC_WINBUF_SURFACE_KIND);
 427         } else {
 428                 switch (window->tiling.mode) {
 429                 case TEGRA_BO_TILING_MODE_PITCH:
 430                         value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
 431                                 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
 432                         break;
 433
 434                 case TEGRA_BO_TILING_MODE_TILED:
 435                         value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
 436                                 DC_WIN_BUFFER_ADDR_MODE_TILE;
 437                         break;
 438
 439                 case TEGRA_BO_TILING_MODE_BLOCK:
 440                         /*
 441                          * No need to handle this here because ->atomic_check
 442                          * will already have filtered it out.
 443                          */
 444                         break;
 445                 }
 446
 447                 tegra_plane_writel(plane, value, DC_WIN_BUFFER_ADDR_MODE);
 448         }
 449
 450         value = WIN_ENABLE;
 451
 452         if (yuv) {
 453                 /* setup default colorspace conversion coefficients */
 454                 tegra_plane_writel(plane, 0x00f0, DC_WIN_CSC_YOF);
 455                 tegra_plane_writel(plane, 0x012a, DC_WIN_CSC_KYRGB);
 456                 tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KUR);
 457                 tegra_plane_writel(plane, 0x0198, DC_WIN_CSC_KVR);
 458                 tegra_plane_writel(plane, 0x039b, DC_WIN_CSC_KUG);
 459                 tegra_plane_writel(plane, 0x032f, DC_WIN_CSC_KVG);
 460                 tegra_plane_writel(plane, 0x0204, DC_WIN_CSC_KUB);
 461                 tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KVB);
 462
 463                 value |= CSC_ENABLE;
 464         } else if (window->bits_per_pixel < 24) {
 465                 value |= COLOR_EXPAND;
 466         }
 467
 468         if (window->bottom_up)
 469                 value |= V_DIRECTION;
 470
 471         if (tegra_plane_use_horizontal_filtering(plane, window)) {
 472                 /*
 473                  * Enable horizontal 6-tap filter and set filtering
 474                  * coefficients to the default values defined in TRM.
 475                  */
 476                 tegra_plane_writel(plane, 0x00008000, DC_WIN_H_FILTER_P(0));
 477                 tegra_plane_writel(plane, 0x3e087ce1, DC_WIN_H_FILTER_P(1));
 478                 tegra_plane_writel(plane, 0x3b117ac1, DC_WIN_H_FILTER_P(2));
 479                 tegra_plane_writel(plane, 0x591b73aa, DC_WIN_H_FILTER_P(3));
 480                 tegra_plane_writel(plane, 0x57256d9a, DC_WIN_H_FILTER_P(4));
 481                 tegra_plane_writel(plane, 0x552f668b, DC_WIN_H_FILTER_P(5));
 482                 tegra_plane_writel(plane, 0x73385e8b, DC_WIN_H_FILTER_P(6));
 483                 tegra_plane_writel(plane, 0x72435583, DC_WIN_H_FILTER_P(7));
 484                 tegra_plane_writel(plane, 0x714c4c8b, DC_WIN_H_FILTER_P(8));
 485                 tegra_plane_writel(plane, 0x70554393, DC_WIN_H_FILTER_P(9));
 486                 tegra_plane_writel(plane, 0x715e389b, DC_WIN_H_FILTER_P(10));
 487                 tegra_plane_writel(plane, 0x71662faa, DC_WIN_H_FILTER_P(11));
 488                 tegra_plane_writel(plane, 0x536d25ba, DC_WIN_H_FILTER_P(12));
 489                 tegra_plane_writel(plane, 0x55731bca, DC_WIN_H_FILTER_P(13));
 490                 tegra_plane_writel(plane, 0x387a11d9, DC_WIN_H_FILTER_P(14));
 491                 tegra_plane_writel(plane, 0x3c7c08f1, DC_WIN_H_FILTER_P(15));
 492
 493                 value |= H_FILTER;
 494         }
 495
 496         if (tegra_plane_use_vertical_filtering(plane, window)) {
 497                 unsigned int i, k;
 498
 499                 /*
 500                  * Enable vertical 2-tap filter and set filtering
 501                  * coefficients to the default values defined in TRM.
 502                  */
 503                 for (i = 0, k = 128; i < 16; i++, k -= 8)
 504                         tegra_plane_writel(plane, k, DC_WIN_V_FILTER_P(i));
 505
 506                 value |= V_FILTER;
 507         }
 508
 509         tegra_plane_writel(plane, value, DC_WIN_WIN_OPTIONS);
 510
 511         if (dc->soc->has_legacy_blending)
 512                 tegra_plane_setup_blending_legacy(plane);
 513         else
 514                 tegra_plane_setup_blending(plane, window);
 515 }
 516
 517 static const u32 tegra20_primary_formats[] = {
 518         DRM_FORMAT_ARGB4444,
 519         DRM_FORMAT_ARGB1555,
 520         DRM_FORMAT_RGB565,
 521         DRM_FORMAT_RGBA5551,
 522         DRM_FORMAT_ABGR8888,
 523         DRM_FORMAT_ARGB8888,
 524         /* non-native formats */
 525         DRM_FORMAT_XRGB1555,
 526         DRM_FORMAT_RGBX5551,
 527         DRM_FORMAT_XBGR8888,
 528         DRM_FORMAT_XRGB8888,
 529 };
 530
 531 static const u64 tegra20_modifiers[] = {
 532         DRM_FORMAT_MOD_LINEAR,
 533         DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED,
 534         DRM_FORMAT_MOD_INVALID
 535 };
 536
 537 static const u32 tegra114_primary_formats[] = {
 538         DRM_FORMAT_ARGB4444,
 539         DRM_FORMAT_ARGB1555,
 540         DRM_FORMAT_RGB565,
 541         DRM_FORMAT_RGBA5551,
 542         DRM_FORMAT_ABGR8888,
 543         DRM_FORMAT_ARGB8888,
 544         /* new on Tegra114 */
 545         DRM_FORMAT_ABGR4444,
 546         DRM_FORMAT_ABGR1555,
 547         DRM_FORMAT_BGRA5551,
 548         DRM_FORMAT_XRGB1555,
 549         DRM_FORMAT_RGBX5551,
 550         DRM_FORMAT_XBGR1555,
 551         DRM_FORMAT_BGRX5551,
 552         DRM_FORMAT_BGR565,
 553         DRM_FORMAT_BGRA8888,
 554         DRM_FORMAT_RGBA8888,
 555         DRM_FORMAT_XRGB8888,
 556         DRM_FORMAT_XBGR8888,
 557 };
 558
 559 static const u32 tegra124_primary_formats[] = {
 560         DRM_FORMAT_ARGB4444,
 561         DRM_FORMAT_ARGB1555,
 562         DRM_FORMAT_RGB565,
 563         DRM_FORMAT_RGBA5551,
 564         DRM_FORMAT_ABGR8888,
 565         DRM_FORMAT_ARGB8888,
 566         /* new on Tegra114 */
 567         DRM_FORMAT_ABGR4444,
 568         DRM_FORMAT_ABGR1555,
 569         DRM_FORMAT_BGRA5551,
 570         DRM_FORMAT_XRGB1555,
 571         DRM_FORMAT_RGBX5551,
 572         DRM_FORMAT_XBGR1555,
 573         DRM_FORMAT_BGRX5551,
 574         DRM_FORMAT_BGR565,
 575         DRM_FORMAT_BGRA8888,
 576         DRM_FORMAT_RGBA8888,
 577         DRM_FORMAT_XRGB8888,
 578         DRM_FORMAT_XBGR8888,
 579         /* new on Tegra124 */
 580         DRM_FORMAT_RGBX8888,
 581         DRM_FORMAT_BGRX8888,
 582 };
 583
 584 static const u64 tegra124_modifiers[] = {
 585         DRM_FORMAT_MOD_LINEAR,
 586         DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0),
 587         DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1),
 588         DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2),
 589         DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3),
 590         DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4),
 591         DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5),
 592         DRM_FORMAT_MOD_INVALID
 593 };
 594
 595 static int tegra_plane_atomic_check(struct drm_plane *plane,
 596                                     struct drm_plane_state *state)
 597 {
 598         struct tegra_plane_state *plane_state = to_tegra_plane_state(state);
 599         unsigned int rotation = DRM_MODE_ROTATE_0 | DRM_MODE_REFLECT_Y;
 600         struct tegra_bo_tiling *tiling = &plane_state->tiling;
 601         struct tegra_plane *tegra = to_tegra_plane(plane);
 602         struct tegra_dc *dc = to_tegra_dc(state->crtc);
 603         int err;
 604
 605         /* no need for further checks if the plane is being disabled */
 606         if (!state->crtc)
 607                 return 0;
 608
 609         err = tegra_plane_format(state->fb->format->format,
 610                                  &plane_state->format,
 611                                  &plane_state->swap);
 612         if (err < 0)
 613                 return err;
 614
 615         /*
 616          * Tegra20 and Tegra30 are special cases here because they support
 617          * only variants of specific formats with an alpha component, but not
 618          * the corresponding opaque formats. However, the opaque formats can
 619          * be emulated by disabling alpha blending for the plane.
 620          */
 621         if (dc->soc->has_legacy_blending) {
 622                 err = tegra_plane_setup_legacy_state(tegra, plane_state);
 623                 if (err < 0)
 624                         return err;
 625         }
 626
 627         err = tegra_fb_get_tiling(state->fb, tiling);
 628         if (err < 0)
 629                 return err;
 630
 631         if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK &&
 632             !dc->soc->supports_block_linear) {
 633                 DRM_ERROR("hardware doesn't support block linear mode\n");
 634                 return -EINVAL;
 635         }
 636
 637         rotation = drm_rotation_simplify(state->rotation, rotation);
 638
 639         if (rotation & DRM_MODE_REFLECT_Y)
 640                 plane_state->bottom_up = true;
 641         else
 642                 plane_state->bottom_up = false;
 643
 644         /*
 645          * Tegra doesn't support different strides for U and V planes so we
 646          * error out if the user tries to display a framebuffer with such a
 647          * configuration.
 648          */
 649         if (state->fb->format->num_planes > 2) {
 650                 if (state->fb->pitches[2] != state->fb->pitches[1]) {
 651                         DRM_ERROR("unsupported UV-plane configuration\n");
 652                         return -EINVAL;
 653                 }
 654         }
 655
 656         err = tegra_plane_state_add(tegra, state);
 657         if (err < 0)
 658                 return err;
 659
 660         return 0;
 661 }
 662
 663 static void tegra_plane_atomic_disable(struct drm_plane *plane,
 664                                        struct drm_plane_state *old_state)
 665 {
 666         struct tegra_plane *p = to_tegra_plane(plane);
 667         u32 value;
 668
 669         /* rien ne va plus */
 670         if (!old_state || !old_state->crtc)
 671                 return;
 672
 673         value = tegra_plane_readl(p, DC_WIN_WIN_OPTIONS);
 674         value &= ~WIN_ENABLE;
 675         tegra_plane_writel(p, value, DC_WIN_WIN_OPTIONS);
 676 }
 677
 678 static void tegra_plane_atomic_update(struct drm_plane *plane,
 679                                       struct drm_plane_state *old_state)
 680 {
 681         struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
 682         struct drm_framebuffer *fb = plane->state->fb;
 683         struct tegra_plane *p = to_tegra_plane(plane);
 684         struct tegra_dc_window window;
 685         unsigned int i;
 686
 687         /* rien ne va plus */
 688         if (!plane->state->crtc || !plane->state->fb)
 689                 return;
 690
 691         if (!plane->state->visible)
 692                 return tegra_plane_atomic_disable(plane, old_state);
 693
 694         memset(&window, 0, sizeof(window));
 695         window.src.x = plane->state->src.x1 >> 16;
 696         window.src.y = plane->state->src.y1 >> 16;
 697         window.src.w = drm_rect_width(&plane->state->src) >> 16;
 698         window.src.h = drm_rect_height(&plane->state->src) >> 16;
 699         window.dst.x = plane->state->dst.x1;
 700         window.dst.y = plane->state->dst.y1;
 701         window.dst.w = drm_rect_width(&plane->state->dst);
 702         window.dst.h = drm_rect_height(&plane->state->dst);
 703         window.bits_per_pixel = fb->format->cpp[0] * 8;
 704         window.bottom_up = tegra_fb_is_bottom_up(fb) || state->bottom_up;
 705
 706         /* copy from state */
 707         window.zpos = plane->state->normalized_zpos;
 708         window.tiling = state->tiling;
 709         window.format = state->format;
 710         window.swap = state->swap;
 711
 712         for (i = 0; i < fb->format->num_planes; i++) {
 713                 struct tegra_bo *bo = tegra_fb_get_plane(fb, i);
 714
 715                 window.base[i] = bo->paddr + fb->offsets[i];
 716
 717                 /*
 718                  * Tegra uses a shared stride for UV planes. Framebuffers are
 719                  * already checked for this in the tegra_plane_atomic_check()
 720                  * function, so it's safe to ignore the V-plane pitch here.
 721                  */
 722                 if (i < 2)
 723                         window.stride[i] = fb->pitches[i];
 724         }
 725
 726         tegra_dc_setup_window(p, &window);
 727 }
 728
 729 static int tegra_plane_atomic_async_check(struct drm_plane *plane,
 730                                           struct drm_plane_state *state)
 731 {
 732         int err;
 733
 734         /*
 735          * It is not obvious whether it's fine for framebuffer to disappear
 736          * while display controller could be accessing it or hardware could
 737          * cope with that somehow. Let's just disallow that to happen.
 738          */
 739         if (!state->fb)
 740                 return -EINVAL;
 741
 742         /* the rest should be fine to change asynchronously */
 743         err = tegra_plane_atomic_check(plane, state);
 744         if (err)
 745                 return err;
 746
 747         return 0;
 748 }
 749
 750 static inline void tegra_plane_clear_latching(struct drm_plane *plane)
 751 {
 752         struct tegra_plane *p = to_tegra_plane(plane);
 753         struct tegra_dc *dc = p->dc;
 754
 755         /* clear pending latching request from the previous async update */
 756         tegra_dc_writel(dc, 0, DC_CMD_STATE_CONTROL);
 757 }
 758
 759 static inline void tegra_plane_atomic_flush(struct drm_plane *plane)
 760 {
 761         struct tegra_plane *p = to_tegra_plane(plane);
 762         struct tegra_dc *dc = p->dc;
 763
 764         /* latch updated registers and activate the new state */
 765         tegra_dc_writel(dc, 1 << (p->index + 9), DC_CMD_STATE_CONTROL);
 766         tegra_dc_writel(dc, 1 << (p->index + 1), DC_CMD_STATE_CONTROL);
 767 }
 768
 769 static void tegra_plane_atomic_async_update(struct drm_plane *plane,
 770                                             struct drm_plane_state *state)
 771 {
 772         tegra_plane_clear_latching(plane);
 773         tegra_plane_copy_state(plane, state);
 774         tegra_plane_atomic_update(plane, plane->state);
 775         tegra_plane_atomic_flush(plane);
 776 }
 777
 778 static const struct drm_plane_helper_funcs tegra_plane_helper_funcs = {
 779         .atomic_check = tegra_plane_atomic_check,
 780         .atomic_disable = tegra_plane_atomic_disable,
 781         .atomic_update = tegra_plane_atomic_update,
 782         .atomic_async_check = tegra_plane_atomic_async_check,
 783         .atomic_async_update = tegra_plane_atomic_async_update,
 784 };
 785
 786 static unsigned long tegra_plane_get_possible_crtcs(struct drm_device *drm)
 787 {
 788         /*
 789          * Ideally this would use drm_crtc_mask(), but that would require the
 790          * CRTC to already be in the mode_config's list of CRTCs. However, it
 791          * will only be added to that list in the drm_crtc_init_with_planes()
 792          * (in tegra_dc_init()), which in turn requires registration of these
 793          * planes. So we have ourselves a nice little chicken and egg problem
 794          * here.
 795          *
 796          * We work around this by manually creating the mask from the number
 797          * of CRTCs that have been registered, and should therefore always be
 798          * the same as drm_crtc_index() after registration.
 799          */
 800         return 1 << drm->mode_config.num_crtc;
 801 }
 802
 803 static struct drm_plane *tegra_primary_plane_create(struct drm_device *drm,
 804                                                     struct tegra_dc *dc)
 805 {
 806         unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
 807         enum drm_plane_type type = DRM_PLANE_TYPE_PRIMARY;
 808         struct tegra_plane *plane;
 809         unsigned int num_formats;
 810         const u64 *modifiers;
 811         const u32 *formats;
 812         int err;
 813
 814         plane = kzalloc(sizeof(*plane), GFP_KERNEL);
 815         if (!plane)
 816                 return ERR_PTR(-ENOMEM);
 817
 818         /* Always use window A as primary window */
 819         plane->offset = 0xa00;
 820         plane->index = 0;
 821         plane->dc = dc;
 822
 823         num_formats = dc->soc->num_primary_formats;
 824         formats = dc->soc->primary_formats;
 825         modifiers = dc->soc->modifiers;
 826
 827         err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
 828                                        &tegra_plane_funcs, formats,
 829                                        num_formats, modifiers, type, NULL);
 830         if (err < 0) {
 831                 kfree(plane);
 832                 return ERR_PTR(err);
 833         }
 834
 835         drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs);
 836         drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255);
 837
 838         err = drm_plane_create_rotation_property(&plane->base,
 839                                                  DRM_MODE_ROTATE_0,
 840                                                  DRM_MODE_ROTATE_0 |
 841                                                  DRM_MODE_REFLECT_Y);
 842         if (err < 0)
 843                 dev_err(dc->dev, "failed to create rotation property: %d\n",
 844                         err);
 845
 846         return &plane->base;
 847 }
 848
 849 static const u32 tegra_cursor_plane_formats[] = {
 850         DRM_FORMAT_RGBA8888,
 851 };
 852
 853 static int tegra_cursor_atomic_check(struct drm_plane *plane,
 854                                      struct drm_plane_state *state)
 855 {
 856         struct tegra_plane *tegra = to_tegra_plane(plane);
 857         int err;
 858
 859         /* no need for further checks if the plane is being disabled */
 860         if (!state->crtc)
 861                 return 0;
 862
 863         /* scaling not supported for cursor */
 864         if ((state->src_w >> 16 != state->crtc_w) ||
 865             (state->src_h >> 16 != state->crtc_h))
 866                 return -EINVAL;
 867
 868         /* only square cursors supported */
 869         if (state->src_w != state->src_h)
 870                 return -EINVAL;
 871
 872         if (state->crtc_w != 32 && state->crtc_w != 64 &&
 873             state->crtc_w != 128 && state->crtc_w != 256)
 874                 return -EINVAL;
 875
 876         err = tegra_plane_state_add(tegra, state);
 877         if (err < 0)
 878                 return err;
 879
 880         return 0;
 881 }
 882
 883 static void tegra_cursor_atomic_update(struct drm_plane *plane,
 884                                        struct drm_plane_state *old_state)
 885 {
 886         struct tegra_bo *bo = tegra_fb_get_plane(plane->state->fb, 0);
 887         struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
 888         struct drm_plane_state *state = plane->state;
 889         u32 value = CURSOR_CLIP_DISPLAY;
 890
 891         /* rien ne va plus */
 892         if (!plane->state->crtc || !plane->state->fb)
 893                 return;
 894
 895         switch (state->crtc_w) {
 896         case 32:
 897                 value |= CURSOR_SIZE_32x32;
 898                 break;
 899
 900         case 64:
 901                 value |= CURSOR_SIZE_64x64;
 902                 break;
 903
 904         case 128:
 905                 value |= CURSOR_SIZE_128x128;
 906                 break;
 907
 908         case 256:
 909                 value |= CURSOR_SIZE_256x256;
 910                 break;
 911
 912         default:
 913                 WARN(1, "cursor size %ux%u not supported\n", state->crtc_w,
 914                      state->crtc_h);
 915                 return;
 916         }
 917
 918         value |= (bo->paddr >> 10) & 0x3fffff;
 919         tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);
 920
 921 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
 922         value = (bo->paddr >> 32) & 0x3;
 923         tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);
 924 #endif
 925
 926         /* enable cursor and set blend mode */
 927         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
 928         value |= CURSOR_ENABLE;
 929         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
 930
 931         value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);
 932         value &= ~CURSOR_DST_BLEND_MASK;
 933         value &= ~CURSOR_SRC_BLEND_MASK;
 934         value |= CURSOR_MODE_NORMAL;
 935         value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC;
 936         value |= CURSOR_SRC_BLEND_K1_TIMES_SRC;
 937         value |= CURSOR_ALPHA;
 938         tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);
 939
 940         /* position the cursor */
 941         value = (state->crtc_y & 0x3fff) << 16 | (state->crtc_x & 0x3fff);
 942         tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);
 943 }
 944
 945 static void tegra_cursor_atomic_disable(struct drm_plane *plane,
 946                                         struct drm_plane_state *old_state)
 947 {
 948         struct tegra_dc *dc;
 949         u32 value;
 950
 951         /* rien ne va plus */
 952         if (!old_state || !old_state->crtc)
 953                 return;
 954
 955         dc = to_tegra_dc(old_state->crtc);
 956
 957         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
 958         value &= ~CURSOR_ENABLE;
 959         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
 960 }
 961
 962 static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = {
 963         .atomic_check = tegra_cursor_atomic_check,
 964         .atomic_update = tegra_cursor_atomic_update,
 965         .atomic_disable = tegra_cursor_atomic_disable,
 966 };
 967
 968 static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm,
 969                                                       struct tegra_dc *dc)
 970 {
 971         unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
 972         struct tegra_plane *plane;
 973         unsigned int num_formats;
 974         const u32 *formats;
 975         int err;
 976
 977         plane = kzalloc(sizeof(*plane), GFP_KERNEL);
 978         if (!plane)
 979                 return ERR_PTR(-ENOMEM);
 980
 981         /*
 982          * This index is kind of fake. The cursor isn't a regular plane, but
 983          * its update and activation request bits in DC_CMD_STATE_CONTROL do
 984          * use the same programming. Setting this fake index here allows the
 985          * code in tegra_add_plane_state() to do the right thing without the
 986          * need to special-casing the cursor plane.
 987          */
 988         plane->index = 6;
 989         plane->dc = dc;
 990
 991         num_formats = ARRAY_SIZE(tegra_cursor_plane_formats);
 992         formats = tegra_cursor_plane_formats;
 993
 994         err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
 995                                        &tegra_plane_funcs, formats,
 996                                        num_formats, NULL,
 997                                        DRM_PLANE_TYPE_CURSOR, NULL);
 998         if (err < 0) {
 999                 kfree(plane);
1000                 return ERR_PTR(err);
1001         }
1002
1003         drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs);
1004
1005         return &plane->base;
1006 }
1007
1008 static const u32 tegra20_overlay_formats[] = {
1009         DRM_FORMAT_ARGB4444,
1010         DRM_FORMAT_ARGB1555,
1011         DRM_FORMAT_RGB565,
1012         DRM_FORMAT_RGBA5551,
1013         DRM_FORMAT_ABGR8888,
1014         DRM_FORMAT_ARGB8888,
1015         /* non-native formats */
1016         DRM_FORMAT_XRGB1555,
1017         DRM_FORMAT_RGBX5551,
1018         DRM_FORMAT_XBGR8888,
1019         DRM_FORMAT_XRGB8888,
1020         /* planar formats */
1021         DRM_FORMAT_UYVY,
1022         DRM_FORMAT_YUYV,
1023         DRM_FORMAT_YUV420,
1024         DRM_FORMAT_YUV422,
1025 };
1026
1027 static const u32 tegra114_overlay_formats[] = {
1028         DRM_FORMAT_ARGB4444,
1029         DRM_FORMAT_ARGB1555,
1030         DRM_FORMAT_RGB565,
1031         DRM_FORMAT_RGBA5551,
1032         DRM_FORMAT_ABGR8888,
1033         DRM_FORMAT_ARGB8888,
1034         /* new on Tegra114 */
1035         DRM_FORMAT_ABGR4444,
1036         DRM_FORMAT_ABGR1555,
1037         DRM_FORMAT_BGRA5551,
1038         DRM_FORMAT_XRGB1555,
1039         DRM_FORMAT_RGBX5551,
1040         DRM_FORMAT_XBGR1555,
1041         DRM_FORMAT_BGRX5551,
1042         DRM_FORMAT_BGR565,
1043         DRM_FORMAT_BGRA8888,
1044         DRM_FORMAT_RGBA8888,
1045         DRM_FORMAT_XRGB8888,
1046         DRM_FORMAT_XBGR8888,
1047         /* planar formats */
1048         DRM_FORMAT_UYVY,
1049         DRM_FORMAT_YUYV,
1050         DRM_FORMAT_YUV420,
1051         DRM_FORMAT_YUV422,
1052 };
1053
1054 static const u32 tegra124_overlay_formats[] = {
1055         DRM_FORMAT_ARGB4444,
1056         DRM_FORMAT_ARGB1555,
1057         DRM_FORMAT_RGB565,
1058         DRM_FORMAT_RGBA5551,
1059         DRM_FORMAT_ABGR8888,
1060         DRM_FORMAT_ARGB8888,
1061         /* new on Tegra114 */
1062         DRM_FORMAT_ABGR4444,
1063         DRM_FORMAT_ABGR1555,
1064         DRM_FORMAT_BGRA5551,
1065         DRM_FORMAT_XRGB1555,
1066         DRM_FORMAT_RGBX5551,
1067         DRM_FORMAT_XBGR1555,
1068         DRM_FORMAT_BGRX5551,
1069         DRM_FORMAT_BGR565,
1070         DRM_FORMAT_BGRA8888,
1071         DRM_FORMAT_RGBA8888,
1072         DRM_FORMAT_XRGB8888,
1073         DRM_FORMAT_XBGR8888,
1074         /* new on Tegra124 */
1075         DRM_FORMAT_RGBX8888,
1076         DRM_FORMAT_BGRX8888,
1077         /* planar formats */
1078         DRM_FORMAT_UYVY,
1079         DRM_FORMAT_YUYV,
1080         DRM_FORMAT_YUV420,
1081         DRM_FORMAT_YUV422,
1082 };
1083
1084 static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm,
1085                                                        struct tegra_dc *dc,
1086                                                        unsigned int index,
1087                                                        bool cursor)
1088 {
1089         unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
1090         struct tegra_plane *plane;
1091         unsigned int num_formats;
1092         enum drm_plane_type type;
1093         const u32 *formats;
1094         int err;
1095
1096         plane = kzalloc(sizeof(*plane), GFP_KERNEL);
1097         if (!plane)
1098                 return ERR_PTR(-ENOMEM);
1099
1100         plane->offset = 0xa00 + 0x200 * index;
1101         plane->index = index;
1102         plane->dc = dc;
1103
1104         num_formats = dc->soc->num_overlay_formats;
1105         formats = dc->soc->overlay_formats;
1106
1107         if (!cursor)
1108                 type = DRM_PLANE_TYPE_OVERLAY;
1109         else
1110                 type = DRM_PLANE_TYPE_CURSOR;
1111
1112         err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
1113                                        &tegra_plane_funcs, formats,
1114                                        num_formats, NULL, type, NULL);
1115         if (err < 0) {
1116                 kfree(plane);
1117                 return ERR_PTR(err);
1118         }
1119
1120         drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs);
1121         drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255);
1122
1123         err = drm_plane_create_rotation_property(&plane->base,
1124                                                  DRM_MODE_ROTATE_0,
1125                                                  DRM_MODE_ROTATE_0 |
1126                                                  DRM_MODE_REFLECT_Y);
1127         if (err < 0)
1128                 dev_err(dc->dev, "failed to create rotation property: %d\n",
1129                         err);
1130
1131         return &plane->base;
1132 }
1133
1134 static struct drm_plane *tegra_dc_add_shared_planes(struct drm_device *drm,
1135                                                     struct tegra_dc *dc)
1136 {
1137         struct drm_plane *plane, *primary = NULL;
1138         unsigned int i, j;
1139
1140         for (i = 0; i < dc->soc->num_wgrps; i++) {
1141                 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i];
1142
1143                 if (wgrp->dc == dc->pipe) {
1144                         for (j = 0; j < wgrp->num_windows; j++) {
1145                                 unsigned int index = wgrp->windows[j];
1146
1147                                 plane = tegra_shared_plane_create(drm, dc,
1148                                                                   wgrp->index,
1149                                                                   index);
1150                                 if (IS_ERR(plane))
1151                                         return plane;
1152
1153                                 /*
1154                                  * Choose the first shared plane owned by this
1155                                  * head as the primary plane.
1156                                  */
1157                                 if (!primary) {
1158                                         plane->type = DRM_PLANE_TYPE_PRIMARY;
1159                                         primary = plane;
1160                                 }
1161                         }
1162                 }
1163         }
1164
1165         return primary;
1166 }
1167
1168 static struct drm_plane *tegra_dc_add_planes(struct drm_device *drm,
1169                                              struct tegra_dc *dc)
1170 {
1171         struct drm_plane *planes[2], *primary;
1172         unsigned int planes_num;
1173         unsigned int i;
1174         int err;
1175
1176         primary = tegra_primary_plane_create(drm, dc);
1177         if (IS_ERR(primary))
1178                 return primary;
1179
1180         if (dc->soc->supports_cursor)
1181                 planes_num = 2;
1182         else
1183                 planes_num = 1;
1184
1185         for (i = 0; i < planes_num; i++) {
1186                 planes[i] = tegra_dc_overlay_plane_create(drm, dc, 1 + i,
1187                                                           false);
1188                 if (IS_ERR(planes[i])) {
1189                         err = PTR_ERR(planes[i]);
1190
1191                         while (i--)
1192                                 tegra_plane_funcs.destroy(planes[i]);
1193
1194                         tegra_plane_funcs.destroy(primary);
1195                         return ERR_PTR(err);
1196                 }
1197         }
1198
1199         return primary;
1200 }
1201
1202 static void tegra_dc_destroy(struct drm_crtc *crtc)
1203 {
1204         drm_crtc_cleanup(crtc);
1205 }
1206
1207 static void tegra_crtc_reset(struct drm_crtc *crtc)
1208 {
1209         struct tegra_dc_state *state;
1210
1211         if (crtc->state)
1212                 __drm_atomic_helper_crtc_destroy_state(crtc->state);
1213
1214         kfree(crtc->state);
1215         crtc->state = NULL;
1216
1217         state = kzalloc(sizeof(*state), GFP_KERNEL);
1218         if (state) {
1219                 crtc->state = &state->base;
1220                 crtc->state->crtc = crtc;
1221         }
1222
1223         drm_crtc_vblank_reset(crtc);
1224 }
1225
1226 static struct drm_crtc_state *
1227 tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
1228 {
1229         struct tegra_dc_state *state = to_dc_state(crtc->state);
1230         struct tegra_dc_state *copy;
1231
1232         copy = kmalloc(sizeof(*copy), GFP_KERNEL);
1233         if (!copy)
1234                 return NULL;
1235
1236         __drm_atomic_helper_crtc_duplicate_state(crtc, &copy->base);
1237         copy->clk = state->clk;
1238         copy->pclk = state->pclk;
1239         copy->div = state->div;
1240         copy->planes = state->planes;
1241
1242         return &copy->base;
1243 }
1244
1245 static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc,
1246                                             struct drm_crtc_state *state)
1247 {
1248         __drm_atomic_helper_crtc_destroy_state(state);
1249         kfree(state);
1250 }
1251
1252 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
1253
1254 static const struct debugfs_reg32 tegra_dc_regs[] = {
1255         DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT),
1256         DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL),
1257         DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_ERROR),
1258         DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT),
1259         DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL),
1260         DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_ERROR),
1261         DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT),
1262         DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL),
1263         DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_ERROR),
1264         DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT),
1265         DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL),
1266         DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_ERROR),
1267         DEBUGFS_REG32(DC_CMD_CONT_SYNCPT_VSYNC),
1268         DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND_OPTION0),
1269         DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND),
1270         DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE),
1271         DEBUGFS_REG32(DC_CMD_DISPLAY_POWER_CONTROL),
1272         DEBUGFS_REG32(DC_CMD_INT_STATUS),
1273         DEBUGFS_REG32(DC_CMD_INT_MASK),
1274         DEBUGFS_REG32(DC_CMD_INT_ENABLE),
1275         DEBUGFS_REG32(DC_CMD_INT_TYPE),
1276         DEBUGFS_REG32(DC_CMD_INT_POLARITY),
1277         DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE1),
1278         DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE2),
1279         DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE3),
1280         DEBUGFS_REG32(DC_CMD_STATE_ACCESS),
1281         DEBUGFS_REG32(DC_CMD_STATE_CONTROL),
1282         DEBUGFS_REG32(DC_CMD_DISPLAY_WINDOW_HEADER),
1283         DEBUGFS_REG32(DC_CMD_REG_ACT_CONTROL),
1284         DEBUGFS_REG32(DC_COM_CRC_CONTROL),
1285         DEBUGFS_REG32(DC_COM_CRC_CHECKSUM),
1286         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(0)),
1287         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(1)),
1288         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(2)),
1289         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(3)),
1290         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(0)),
1291         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(1)),
1292         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(2)),
1293         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(3)),
1294         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(0)),
1295         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(1)),
1296         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(2)),
1297         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(3)),
1298         DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(0)),
1299         DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(1)),
1300         DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(2)),
1301         DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(3)),
1302         DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(0)),
1303         DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(1)),
1304         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(0)),
1305         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(1)),
1306         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(2)),
1307         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(3)),
1308         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(4)),
1309         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(5)),
1310         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(6)),
1311         DEBUGFS_REG32(DC_COM_PIN_MISC_CONTROL),
1312         DEBUGFS_REG32(DC_COM_PIN_PM0_CONTROL),
1313         DEBUGFS_REG32(DC_COM_PIN_PM0_DUTY_CYCLE),
1314         DEBUGFS_REG32(DC_COM_PIN_PM1_CONTROL),
1315         DEBUGFS_REG32(DC_COM_PIN_PM1_DUTY_CYCLE),
1316         DEBUGFS_REG32(DC_COM_SPI_CONTROL),
1317         DEBUGFS_REG32(DC_COM_SPI_START_BYTE),
1318         DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_AB),
1319         DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_CD),
1320         DEBUGFS_REG32(DC_COM_HSPI_CS_DC),
1321         DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_A),
1322         DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_B),
1323         DEBUGFS_REG32(DC_COM_GPIO_CTRL),
1324         DEBUGFS_REG32(DC_COM_GPIO_DEBOUNCE_COUNTER),
1325         DEBUGFS_REG32(DC_COM_CRC_CHECKSUM_LATCHED),
1326         DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS0),
1327         DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS1),
1328         DEBUGFS_REG32(DC_DISP_DISP_WIN_OPTIONS),
1329         DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY),
1330         DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER),
1331         DEBUGFS_REG32(DC_DISP_DISP_TIMING_OPTIONS),
1332         DEBUGFS_REG32(DC_DISP_REF_TO_SYNC),
1333         DEBUGFS_REG32(DC_DISP_SYNC_WIDTH),
1334         DEBUGFS_REG32(DC_DISP_BACK_PORCH),
1335         DEBUGFS_REG32(DC_DISP_ACTIVE),
1336         DEBUGFS_REG32(DC_DISP_FRONT_PORCH),
1337         DEBUGFS_REG32(DC_DISP_H_PULSE0_CONTROL),
1338         DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_A),
1339         DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_B),
1340         DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_C),
1341         DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_D),
1342         DEBUGFS_REG32(DC_DISP_H_PULSE1_CONTROL),
1343         DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_A),
1344         DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_B),
1345         DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_C),
1346         DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_D),
1347         DEBUGFS_REG32(DC_DISP_H_PULSE2_CONTROL),
1348         DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_A),
1349         DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_B),
1350         DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_C),
1351         DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_D),
1352         DEBUGFS_REG32(DC_DISP_V_PULSE0_CONTROL),
1353         DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_A),
1354         DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_B),
1355         DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_C),
1356         DEBUGFS_REG32(DC_DISP_V_PULSE1_CONTROL),
1357         DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_A),
1358         DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_B),
1359         DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_C),
1360         DEBUGFS_REG32(DC_DISP_V_PULSE2_CONTROL),
1361         DEBUGFS_REG32(DC_DISP_V_PULSE2_POSITION_A),
1362         DEBUGFS_REG32(DC_DISP_V_PULSE3_CONTROL),
1363         DEBUGFS_REG32(DC_DISP_V_PULSE3_POSITION_A),
1364         DEBUGFS_REG32(DC_DISP_M0_CONTROL),
1365         DEBUGFS_REG32(DC_DISP_M1_CONTROL),
1366         DEBUGFS_REG32(DC_DISP_DI_CONTROL),
1367         DEBUGFS_REG32(DC_DISP_PP_CONTROL),
1368         DEBUGFS_REG32(DC_DISP_PP_SELECT_A),
1369         DEBUGFS_REG32(DC_DISP_PP_SELECT_B),
1370         DEBUGFS_REG32(DC_DISP_PP_SELECT_C),
1371         DEBUGFS_REG32(DC_DISP_PP_SELECT_D),
1372         DEBUGFS_REG32(DC_DISP_DISP_CLOCK_CONTROL),
1373         DEBUGFS_REG32(DC_DISP_DISP_INTERFACE_CONTROL),
1374         DEBUGFS_REG32(DC_DISP_DISP_COLOR_CONTROL),
1375         DEBUGFS_REG32(DC_DISP_SHIFT_CLOCK_OPTIONS),
1376         DEBUGFS_REG32(DC_DISP_DATA_ENABLE_OPTIONS),
1377         DEBUGFS_REG32(DC_DISP_SERIAL_INTERFACE_OPTIONS),
1378         DEBUGFS_REG32(DC_DISP_LCD_SPI_OPTIONS),
1379         DEBUGFS_REG32(DC_DISP_BORDER_COLOR),
1380         DEBUGFS_REG32(DC_DISP_COLOR_KEY0_LOWER),
1381         DEBUGFS_REG32(DC_DISP_COLOR_KEY0_UPPER),
1382         DEBUGFS_REG32(DC_DISP_COLOR_KEY1_LOWER),
1383         DEBUGFS_REG32(DC_DISP_COLOR_KEY1_UPPER),
1384         DEBUGFS_REG32(DC_DISP_CURSOR_FOREGROUND),
1385         DEBUGFS_REG32(DC_DISP_CURSOR_BACKGROUND),
1386         DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR),
1387         DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_NS),
1388         DEBUGFS_REG32(DC_DISP_CURSOR_POSITION),
1389         DEBUGFS_REG32(DC_DISP_CURSOR_POSITION_NS),
1390         DEBUGFS_REG32(DC_DISP_INIT_SEQ_CONTROL),
1391         DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_A),
1392         DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_B),
1393         DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_C),
1394         DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_D),
1395         DEBUGFS_REG32(DC_DISP_DC_MCCIF_FIFOCTRL),
1396         DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0A_HYST),
1397         DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0B_HYST),
1398         DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1A_HYST),
1399         DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1B_HYST),
1400         DEBUGFS_REG32(DC_DISP_DAC_CRT_CTRL),
1401         DEBUGFS_REG32(DC_DISP_DISP_MISC_CONTROL),
1402         DEBUGFS_REG32(DC_DISP_SD_CONTROL),
1403         DEBUGFS_REG32(DC_DISP_SD_CSC_COEFF),
1404         DEBUGFS_REG32(DC_DISP_SD_LUT(0)),
1405         DEBUGFS_REG32(DC_DISP_SD_LUT(1)),
1406         DEBUGFS_REG32(DC_DISP_SD_LUT(2)),
1407         DEBUGFS_REG32(DC_DISP_SD_LUT(3)),
1408         DEBUGFS_REG32(DC_DISP_SD_LUT(4)),
1409         DEBUGFS_REG32(DC_DISP_SD_LUT(5)),
1410         DEBUGFS_REG32(DC_DISP_SD_LUT(6)),
1411         DEBUGFS_REG32(DC_DISP_SD_LUT(7)),
1412         DEBUGFS_REG32(DC_DISP_SD_LUT(8)),
1413         DEBUGFS_REG32(DC_DISP_SD_FLICKER_CONTROL),
1414         DEBUGFS_REG32(DC_DISP_DC_PIXEL_COUNT),
1415         DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(0)),
1416         DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(1)),
1417         DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(2)),
1418         DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(3)),
1419         DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(4)),
1420         DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(5)),
1421         DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(6)),
1422         DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(7)),
1423         DEBUGFS_REG32(DC_DISP_SD_BL_TF(0)),
1424         DEBUGFS_REG32(DC_DISP_SD_BL_TF(1)),
1425         DEBUGFS_REG32(DC_DISP_SD_BL_TF(2)),
1426         DEBUGFS_REG32(DC_DISP_SD_BL_TF(3)),
1427         DEBUGFS_REG32(DC_DISP_SD_BL_CONTROL),
1428         DEBUGFS_REG32(DC_DISP_SD_HW_K_VALUES),
1429         DEBUGFS_REG32(DC_DISP_SD_MAN_K_VALUES),
1430         DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_HI),
1431         DEBUGFS_REG32(DC_DISP_BLEND_CURSOR_CONTROL),
1432         DEBUGFS_REG32(DC_WIN_WIN_OPTIONS),
1433         DEBUGFS_REG32(DC_WIN_BYTE_SWAP),
1434         DEBUGFS_REG32(DC_WIN_BUFFER_CONTROL),
1435         DEBUGFS_REG32(DC_WIN_COLOR_DEPTH),
1436         DEBUGFS_REG32(DC_WIN_POSITION),
1437         DEBUGFS_REG32(DC_WIN_SIZE),
1438         DEBUGFS_REG32(DC_WIN_PRESCALED_SIZE),
1439         DEBUGFS_REG32(DC_WIN_H_INITIAL_DDA),
1440         DEBUGFS_REG32(DC_WIN_V_INITIAL_DDA),
1441         DEBUGFS_REG32(DC_WIN_DDA_INC),
1442         DEBUGFS_REG32(DC_WIN_LINE_STRIDE),
1443         DEBUGFS_REG32(DC_WIN_BUF_STRIDE),
1444         DEBUGFS_REG32(DC_WIN_UV_BUF_STRIDE),
1445         DEBUGFS_REG32(DC_WIN_BUFFER_ADDR_MODE),
1446         DEBUGFS_REG32(DC_WIN_DV_CONTROL),
1447         DEBUGFS_REG32(DC_WIN_BLEND_NOKEY),
1448         DEBUGFS_REG32(DC_WIN_BLEND_1WIN),
1449         DEBUGFS_REG32(DC_WIN_BLEND_2WIN_X),
1450         DEBUGFS_REG32(DC_WIN_BLEND_2WIN_Y),
1451         DEBUGFS_REG32(DC_WIN_BLEND_3WIN_XY),
1452         DEBUGFS_REG32(DC_WIN_HP_FETCH_CONTROL),
1453         DEBUGFS_REG32(DC_WINBUF_START_ADDR),
1454         DEBUGFS_REG32(DC_WINBUF_START_ADDR_NS),
1455         DEBUGFS_REG32(DC_WINBUF_START_ADDR_U),
1456         DEBUGFS_REG32(DC_WINBUF_START_ADDR_U_NS),
1457         DEBUGFS_REG32(DC_WINBUF_START_ADDR_V),
1458         DEBUGFS_REG32(DC_WINBUF_START_ADDR_V_NS),
1459         DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET),
1460         DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET_NS),
1461         DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET),
1462         DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET_NS),
1463         DEBUGFS_REG32(DC_WINBUF_UFLOW_STATUS),
1464         DEBUGFS_REG32(DC_WINBUF_AD_UFLOW_STATUS),
1465         DEBUGFS_REG32(DC_WINBUF_BD_UFLOW_STATUS),
1466         DEBUGFS_REG32(DC_WINBUF_CD_UFLOW_STATUS),
1467 };
1468
1469 static int tegra_dc_show_regs(struct seq_file *s, void *data)
1470 {
1471         struct drm_info_node *node = s->private;
1472         struct tegra_dc *dc = node->info_ent->data;
1473         unsigned int i;
1474         int err = 0;
1475
1476         drm_modeset_lock(&dc->base.mutex, NULL);
1477
1478         if (!dc->base.state->active) {
1479                 err = -EBUSY;
1480                 goto unlock;
1481         }
1482
1483         for (i = 0; i < ARRAY_SIZE(tegra_dc_regs); i++) {
1484                 unsigned int offset = tegra_dc_regs[i].offset;
1485
1486                 seq_printf(s, "%-40s %#05x %08x\n", tegra_dc_regs[i].name,
1487                            offset, tegra_dc_readl(dc, offset));
1488         }
1489
1490 unlock:
1491         drm_modeset_unlock(&dc->base.mutex);
1492         return err;
1493 }
1494
1495 static int tegra_dc_show_crc(struct seq_file *s, void *data)
1496 {
1497         struct drm_info_node *node = s->private;
1498         struct tegra_dc *dc = node->info_ent->data;
1499         int err = 0;
1500         u32 value;
1501
1502         drm_modeset_lock(&dc->base.mutex, NULL);
1503
1504         if (!dc->base.state->active) {
1505                 err = -EBUSY;
1506                 goto unlock;
1507         }
1508
1509         value = DC_COM_CRC_CONTROL_ACTIVE_DATA | DC_COM_CRC_CONTROL_ENABLE;
1510         tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL);
1511         tegra_dc_commit(dc);
1512
1513         drm_crtc_wait_one_vblank(&dc->base);
1514         drm_crtc_wait_one_vblank(&dc->base);
1515
1516         value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM);
1517         seq_printf(s, "%08x\n", value);
1518
1519         tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL);
1520
1521 unlock:
1522         drm_modeset_unlock(&dc->base.mutex);
1523         return err;
1524 }
1525
1526 static int tegra_dc_show_stats(struct seq_file *s, void *data)
1527 {
1528         struct drm_info_node *node = s->private;
1529         struct tegra_dc *dc = node->info_ent->data;
1530
1531         seq_printf(s, "frames: %lu\n", dc->stats.frames);
1532         seq_printf(s, "vblank: %lu\n", dc->stats.vblank);
1533         seq_printf(s, "underflow: %lu\n", dc->stats.underflow);
1534         seq_printf(s, "overflow: %lu\n", dc->stats.overflow);
1535
1536         return 0;
1537 }
1538
1539 static struct drm_info_list debugfs_files[] = {
1540         { "regs", tegra_dc_show_regs, 0, NULL },
1541         { "crc", tegra_dc_show_crc, 0, NULL },
1542         { "stats", tegra_dc_show_stats, 0, NULL },
1543 };
1544
1545 static int tegra_dc_late_register(struct drm_crtc *crtc)
1546 {
1547         unsigned int i, count = ARRAY_SIZE(debugfs_files);
1548         struct drm_minor *minor = crtc->dev->primary;
1549         struct dentry *root;
1550         struct tegra_dc *dc = to_tegra_dc(crtc);
1551         int err;
1552
1553 #ifdef CONFIG_DEBUG_FS
1554         root = crtc->debugfs_entry;
1555 #else
1556         root = NULL;
1557 #endif
1558
1559         dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1560                                     GFP_KERNEL);
1561         if (!dc->debugfs_files)
1562                 return -ENOMEM;
1563
1564         for (i = 0; i < count; i++)
1565                 dc->debugfs_files[i].data = dc;
1566
1567         err = drm_debugfs_create_files(dc->debugfs_files, count, root, minor);
1568         if (err < 0)
1569                 goto free;
1570
1571         return 0;
1572
1573 free:
1574         kfree(dc->debugfs_files);
1575         dc->debugfs_files = NULL;
1576
1577         return err;
1578 }
1579
1580 static void tegra_dc_early_unregister(struct drm_crtc *crtc)
1581 {
1582         unsigned int count = ARRAY_SIZE(debugfs_files);
1583         struct drm_minor *minor = crtc->dev->primary;
1584         struct tegra_dc *dc = to_tegra_dc(crtc);
1585
1586         drm_debugfs_remove_files(dc->debugfs_files, count, minor);
1587         kfree(dc->debugfs_files);
1588         dc->debugfs_files = NULL;
1589 }
1590
1591 static u32 tegra_dc_get_vblank_counter(struct drm_crtc *crtc)
1592 {
1593         struct tegra_dc *dc = to_tegra_dc(crtc);
1594
1595         /* XXX vblank syncpoints don't work with nvdisplay yet */
1596         if (dc->syncpt && !dc->soc->has_nvdisplay)
1597                 return host1x_syncpt_read(dc->syncpt);
1598
1599         /* fallback to software emulated VBLANK counter */
1600         return (u32)drm_crtc_vblank_count(&dc->base);
1601 }
1602
1603 static int tegra_dc_enable_vblank(struct drm_crtc *crtc)
1604 {
1605         struct tegra_dc *dc = to_tegra_dc(crtc);
1606         u32 value;
1607
1608         value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1609         value |= VBLANK_INT;
1610         tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1611
1612         return 0;
1613 }
1614
1615 static void tegra_dc_disable_vblank(struct drm_crtc *crtc)
1616 {
1617         struct tegra_dc *dc = to_tegra_dc(crtc);
1618         u32 value;
1619
1620         value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1621         value &= ~VBLANK_INT;
1622         tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1623 }
1624
1625 static const struct drm_crtc_funcs tegra_crtc_funcs = {
1626         .page_flip = drm_atomic_helper_page_flip,
1627         .set_config = drm_atomic_helper_set_config,
1628         .destroy = tegra_dc_destroy,
1629         .reset = tegra_crtc_reset,
1630         .atomic_duplicate_state = tegra_crtc_atomic_duplicate_state,
1631         .atomic_destroy_state = tegra_crtc_atomic_destroy_state,
1632         .late_register = tegra_dc_late_register,
1633         .early_unregister = tegra_dc_early_unregister,
1634         .get_vblank_counter = tegra_dc_get_vblank_counter,
1635         .enable_vblank = tegra_dc_enable_vblank,
1636         .disable_vblank = tegra_dc_disable_vblank,
1637 };
1638
1639 static int tegra_dc_set_timings(struct tegra_dc *dc,
1640                                 struct drm_display_mode *mode)
1641 {
1642         unsigned int h_ref_to_sync = 1;
1643         unsigned int v_ref_to_sync = 1;
1644         unsigned long value;
1645
1646         if (!dc->soc->has_nvdisplay) {
1647                 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1648
1649                 value = (v_ref_to_sync << 16) | h_ref_to_sync;
1650                 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
1651         }
1652
1653         value = ((mode->vsync_end - mode->vsync_start) << 16) |
1654                 ((mode->hsync_end - mode->hsync_start) <<  0);
1655         tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
1656
1657         value = ((mode->vtotal - mode->vsync_end) << 16) |
1658                 ((mode->htotal - mode->hsync_end) <<  0);
1659         tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
1660
1661         value = ((mode->vsync_start - mode->vdisplay) << 16) |
1662                 ((mode->hsync_start - mode->hdisplay) <<  0);
1663         tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
1664
1665         value = (mode->vdisplay << 16) | mode->hdisplay;
1666         tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
1667
1668         return 0;
1669 }
1670
1671 /**
1672  * tegra_dc_state_setup_clock - check clock settings and store them in atomic
1673  *     state
1674  * @dc: display controller
1675  * @crtc_state: CRTC atomic state
1676  * @clk: parent clock for display controller
1677  * @pclk: pixel clock
1678  * @div: shift clock divider
1679  *
1680  * Returns:
1681  * 0 on success or a negative error-code on failure.
1682  */
1683 int tegra_dc_state_setup_clock(struct tegra_dc *dc,
1684                                struct drm_crtc_state *crtc_state,
1685                                struct clk *clk, unsigned long pclk,
1686                                unsigned int div)
1687 {
1688         struct tegra_dc_state *state = to_dc_state(crtc_state);
1689
1690         if (!clk_has_parent(dc->clk, clk))
1691                 return -EINVAL;
1692
1693         state->clk = clk;
1694         state->pclk = pclk;
1695         state->div = div;
1696
1697         return 0;
1698 }
1699
1700 static void tegra_dc_commit_state(struct tegra_dc *dc,
1701                                   struct tegra_dc_state *state)
1702 {
1703         u32 value;
1704         int err;
1705
1706         err = clk_set_parent(dc->clk, state->clk);
1707         if (err < 0)
1708                 dev_err(dc->dev, "failed to set parent clock: %d\n", err);
1709
1710         /*
1711          * Outputs may not want to change the parent clock rate. This is only
1712          * relevant to Tegra20 where only a single display PLL is available.
1713          * Since that PLL would typically be used for HDMI, an internal LVDS
1714          * panel would need to be driven by some other clock such as PLL_P
1715          * which is shared with other peripherals. Changing the clock rate
1716          * should therefore be avoided.
1717          */
1718         if (state->pclk > 0) {
1719                 err = clk_set_rate(state->clk, state->pclk);
1720                 if (err < 0)
1721                         dev_err(dc->dev,
1722                                 "failed to set clock rate to %lu Hz\n",
1723                                 state->pclk);
1724         }
1725
1726         DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk),
1727                       state->div);
1728         DRM_DEBUG_KMS("pclk: %lu\n", state->pclk);
1729
1730         if (!dc->soc->has_nvdisplay) {
1731                 value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1;
1732                 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
1733         }
1734
1735         err = clk_set_rate(dc->clk, state->pclk);
1736         if (err < 0)
1737                 dev_err(dc->dev, "failed to set clock %pC to %lu Hz: %d\n",
1738                         dc->clk, state->pclk, err);
1739 }
1740
1741 static void tegra_dc_stop(struct tegra_dc *dc)
1742 {
1743         u32 value;
1744
1745         /* stop the display controller */
1746         value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1747         value &= ~DISP_CTRL_MODE_MASK;
1748         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1749
1750         tegra_dc_commit(dc);
1751 }
1752
1753 static bool tegra_dc_idle(struct tegra_dc *dc)
1754 {
1755         u32 value;
1756
1757         value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND);
1758
1759         return (value & DISP_CTRL_MODE_MASK) == 0;
1760 }
1761
1762 static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout)
1763 {
1764         timeout = jiffies + msecs_to_jiffies(timeout);
1765
1766         while (time_before(jiffies, timeout)) {
1767                 if (tegra_dc_idle(dc))
1768                         return 0;
1769
1770                 usleep_range(1000, 2000);
1771         }
1772
1773         dev_dbg(dc->dev, "timeout waiting for DC to become idle\n");
1774         return -ETIMEDOUT;
1775 }
1776
1777 static void tegra_crtc_atomic_disable(struct drm_crtc *crtc,
1778                                       struct drm_crtc_state *old_state)
1779 {
1780         struct tegra_dc *dc = to_tegra_dc(crtc);
1781         u32 value;
1782
1783         if (!tegra_dc_idle(dc)) {
1784                 tegra_dc_stop(dc);
1785
1786                 /*
1787                  * Ignore the return value, there isn't anything useful to do
1788                  * in case this fails.
1789                  */
1790                 tegra_dc_wait_idle(dc, 100);
1791         }
1792
1793         /*
1794          * This should really be part of the RGB encoder driver, but clearing
1795          * these bits has the side-effect of stopping the display controller.
1796          * When that happens no VBLANK interrupts will be raised. At the same
1797          * time the encoder is disabled before the display controller, so the
1798          * above code is always going to timeout waiting for the controller
1799          * to go idle.
1800          *
1801          * Given the close coupling between the RGB encoder and the display
1802          * controller doing it here is still kind of okay. None of the other
1803          * encoder drivers require these bits to be cleared.
1804          *
1805          * XXX: Perhaps given that the display controller is switched off at
1806          * this point anyway maybe clearing these bits isn't even useful for
1807          * the RGB encoder?
1808          */
1809         if (dc->rgb) {
1810                 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1811                 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1812                            PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
1813                 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1814         }
1815
1816         tegra_dc_stats_reset(&dc->stats);
1817         drm_crtc_vblank_off(crtc);
1818
1819         spin_lock_irq(&crtc->dev->event_lock);
1820
1821         if (crtc->state->event) {
1822                 drm_crtc_send_vblank_event(crtc, crtc->state->event);
1823                 crtc->state->event = NULL;
1824         }
1825
1826         spin_unlock_irq(&crtc->dev->event_lock);
1827
1828         pm_runtime_put_sync(dc->dev);
1829 }
1830
1831 static void tegra_crtc_atomic_enable(struct drm_crtc *crtc,
1832                                      struct drm_crtc_state *old_state)
1833 {
1834         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1835         struct tegra_dc_state *state = to_dc_state(crtc->state);
1836         struct tegra_dc *dc = to_tegra_dc(crtc);
1837         u32 value;
1838
1839         pm_runtime_get_sync(dc->dev);
1840
1841         /* initialize display controller */
1842         if (dc->syncpt) {
1843                 u32 syncpt = host1x_syncpt_id(dc->syncpt), enable;
1844
1845                 if (dc->soc->has_nvdisplay)
1846                         enable = 1 << 31;
1847                 else
1848                         enable = 1 << 8;
1849
1850                 value = SYNCPT_CNTRL_NO_STALL;
1851                 tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1852
1853                 value = enable | syncpt;
1854                 tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC);
1855         }
1856
1857         if (dc->soc->has_nvdisplay) {
1858                 value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT |
1859                         DSC_OBUF_UF_INT;
1860                 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
1861
1862                 value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT |
1863                         DSC_OBUF_UF_INT | SD3_BUCKET_WALK_DONE_INT |
1864                         HEAD_UF_INT | MSF_INT | REG_TMOUT_INT |
1865                         REGION_CRC_INT | V_PULSE2_INT | V_PULSE3_INT |
1866                         VBLANK_INT | FRAME_END_INT;
1867                 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1868
1869                 value = SD3_BUCKET_WALK_DONE_INT | HEAD_UF_INT | VBLANK_INT |
1870                         FRAME_END_INT;
1871                 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
1872
1873                 value = HEAD_UF_INT | REG_TMOUT_INT | FRAME_END_INT;
1874                 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1875
1876                 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
1877         } else {
1878                 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1879                         WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1880                 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
1881
1882                 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1883                         WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1884                 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1885
1886                 /* initialize timer */
1887                 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
1888                         WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
1889                 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
1890
1891                 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
1892                         WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
1893                 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1894
1895                 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1896                         WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1897                 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
1898
1899                 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1900                         WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1901                 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1902         }
1903
1904         if (dc->soc->supports_background_color)
1905                 tegra_dc_writel(dc, 0, DC_DISP_BLEND_BACKGROUND_COLOR);
1906         else
1907                 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
1908
1909         /* apply PLL and pixel clock changes */
1910         tegra_dc_commit_state(dc, state);
1911
1912         /* program display mode */
1913         tegra_dc_set_timings(dc, mode);
1914
1915         /* interlacing isn't supported yet, so disable it */
1916         if (dc->soc->supports_interlacing) {
1917                 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
1918                 value &= ~INTERLACE_ENABLE;
1919                 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
1920         }
1921
1922         value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1923         value &= ~DISP_CTRL_MODE_MASK;
1924         value |= DISP_CTRL_MODE_C_DISPLAY;
1925         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1926
1927         if (!dc->soc->has_nvdisplay) {
1928                 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1929                 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1930                          PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
1931                 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1932         }
1933
1934         /* enable underflow reporting and display red for missing pixels */
1935         if (dc->soc->has_nvdisplay) {
1936                 value = UNDERFLOW_MODE_RED | UNDERFLOW_REPORT_ENABLE;
1937                 tegra_dc_writel(dc, value, DC_COM_RG_UNDERFLOW);
1938         }
1939
1940         tegra_dc_commit(dc);
1941
1942         drm_crtc_vblank_on(crtc);
1943 }
1944
1945 static void tegra_crtc_atomic_begin(struct drm_crtc *crtc,
1946                                     struct drm_crtc_state *old_crtc_state)
1947 {
1948         unsigned long flags;
1949
1950         if (crtc->state->event) {
1951                 spin_lock_irqsave(&crtc->dev->event_lock, flags);
1952
1953                 if (drm_crtc_vblank_get(crtc) != 0)
1954                         drm_crtc_send_vblank_event(crtc, crtc->state->event);
1955                 else
1956                         drm_crtc_arm_vblank_event(crtc, crtc->state->event);
1957
1958                 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
1959
1960                 crtc->state->event = NULL;
1961         }
1962 }
1963
1964 static void tegra_crtc_atomic_flush(struct drm_crtc *crtc,
1965                                     struct drm_crtc_state *old_crtc_state)
1966 {
1967         struct tegra_dc_state *state = to_dc_state(crtc->state);
1968         struct tegra_dc *dc = to_tegra_dc(crtc);
1969         u32 value;
1970
1971         value = state->planes << 8 | GENERAL_UPDATE;
1972         tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
1973         value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1974
1975         value = state->planes | GENERAL_ACT_REQ;
1976         tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
1977         value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1978 }
1979
1980 static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
1981         .atomic_begin = tegra_crtc_atomic_begin,
1982         .atomic_flush = tegra_crtc_atomic_flush,
1983         .atomic_enable = tegra_crtc_atomic_enable,
1984         .atomic_disable = tegra_crtc_atomic_disable,
1985 };
1986
1987 static irqreturn_t tegra_dc_irq(int irq, void *data)
1988 {
1989         struct tegra_dc *dc = data;
1990         unsigned long status;
1991
1992         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1993         tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1994
1995         if (status & FRAME_END_INT) {
1996                 /*
1997                 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
1998                 */
1999                 dc->stats.frames++;
2000         }
2001
2002         if (status & VBLANK_INT) {
2003                 /*
2004                 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
2005                 */
2006                 drm_crtc_handle_vblank(&dc->base);
2007                 dc->stats.vblank++;
2008         }
2009
2010         if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
2011                 /*
2012                 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
2013                 */
2014                 dc->stats.underflow++;
2015         }
2016
2017         if (status & (WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT)) {
2018                 /*
2019                 dev_dbg(dc->dev, "%s(): overflow\n", __func__);
2020                 */
2021                 dc->stats.overflow++;
2022         }
2023
2024         if (status & HEAD_UF_INT) {
2025                 dev_dbg_ratelimited(dc->dev, "%s(): head underflow\n", __func__);
2026                 dc->stats.underflow++;
2027         }
2028
2029         return IRQ_HANDLED;
2030 }
2031
2032 static bool tegra_dc_has_window_groups(struct tegra_dc *dc)
2033 {
2034         unsigned int i;
2035
2036         if (!dc->soc->wgrps)
2037                 return true;
2038
2039         for (i = 0; i < dc->soc->num_wgrps; i++) {
2040                 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i];
2041
2042                 if (wgrp->dc == dc->pipe && wgrp->num_windows > 0)
2043                         return true;
2044         }
2045
2046         return false;
2047 }
2048
2049 static int tegra_dc_init(struct host1x_client *client)
2050 {
2051         struct drm_device *drm = dev_get_drvdata(client->parent);
2052         unsigned long flags = HOST1X_SYNCPT_CLIENT_MANAGED;
2053         struct tegra_dc *dc = host1x_client_to_dc(client);
2054         struct tegra_drm *tegra = drm->dev_private;
2055         struct drm_plane *primary = NULL;
2056         struct drm_plane *cursor = NULL;
2057         int err;
2058
2059         /*
2060          * XXX do not register DCs with no window groups because we cannot
2061          * assign a primary plane to them, which in turn will cause KMS to
2062          * crash.
2063          */
2064         if (!tegra_dc_has_window_groups(dc))
2065                 return 0;
2066
2067         dc->syncpt = host1x_syncpt_request(client, flags);
2068         if (!dc->syncpt)
2069                 dev_warn(dc->dev, "failed to allocate syncpoint\n");
2070
2071         dc->group = host1x_client_iommu_attach(client, true);
2072         if (IS_ERR(dc->group)) {
2073                 err = PTR_ERR(dc->group);
2074                 dev_err(client->dev, "failed to attach to domain: %d\n", err);
2075                 return err;
2076         }
2077
2078         if (dc->soc->wgrps)
2079                 primary = tegra_dc_add_shared_planes(drm, dc);
2080         else
2081                 primary = tegra_dc_add_planes(drm, dc);
2082
2083         if (IS_ERR(primary)) {
2084                 err = PTR_ERR(primary);
2085                 goto cleanup;
2086         }
2087
2088         if (dc->soc->supports_cursor) {
2089                 cursor = tegra_dc_cursor_plane_create(drm, dc);
2090                 if (IS_ERR(cursor)) {
2091                         err = PTR_ERR(cursor);
2092                         goto cleanup;
2093                 }
2094         } else {
2095                 /* dedicate one overlay to mouse cursor */
2096                 cursor = tegra_dc_overlay_plane_create(drm, dc, 2, true);
2097                 if (IS_ERR(cursor)) {
2098                         err = PTR_ERR(cursor);
2099                         goto cleanup;
2100                 }
2101         }
2102
2103         err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor,
2104                                         &tegra_crtc_funcs, NULL);
2105         if (err < 0)
2106                 goto cleanup;
2107
2108         drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
2109
2110         /*
2111          * Keep track of the minimum pitch alignment across all display
2112          * controllers.
2113          */
2114         if (dc->soc->pitch_align > tegra->pitch_align)
2115                 tegra->pitch_align = dc->soc->pitch_align;
2116
2117         err = tegra_dc_rgb_init(drm, dc);
2118         if (err < 0 && err != -ENODEV) {
2119                 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
2120                 goto cleanup;
2121         }
2122
2123         err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
2124                                dev_name(dc->dev), dc);
2125         if (err < 0) {
2126                 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
2127                         err);
2128                 goto cleanup;
2129         }
2130
2131         return 0;
2132
2133 cleanup:
2134         if (!IS_ERR_OR_NULL(cursor))
2135                 drm_plane_cleanup(cursor);
2136
2137         if (!IS_ERR(primary))
2138                 drm_plane_cleanup(primary);
2139
2140         host1x_client_iommu_detach(client, dc->group);
2141         host1x_syncpt_free(dc->syncpt);
2142
2143         return err;
2144 }
2145
2146 static int tegra_dc_exit(struct host1x_client *client)
2147 {
2148         struct tegra_dc *dc = host1x_client_to_dc(client);
2149         int err;
2150
2151         if (!tegra_dc_has_window_groups(dc))
2152                 return 0;
2153
2154         devm_free_irq(dc->dev, dc->irq, dc);
2155
2156         err = tegra_dc_rgb_exit(dc);
2157         if (err) {
2158                 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
2159                 return err;
2160         }
2161
2162         host1x_client_iommu_detach(client, dc->group);
2163         host1x_syncpt_free(dc->syncpt);
2164
2165         return 0;
2166 }
2167
2168 static const struct host1x_client_ops dc_client_ops = {
2169         .init = tegra_dc_init,
2170         .exit = tegra_dc_exit,
2171 };
2172
2173 static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
2174         .supports_background_color = false,
2175         .supports_interlacing = false,
2176         .supports_cursor = false,
2177         .supports_block_linear = false,
2178         .has_legacy_blending = true,
2179         .pitch_align = 8,
2180         .has_powergate = false,
2181         .coupled_pm = true,
2182         .has_nvdisplay = false,
2183         .num_primary_formats = ARRAY_SIZE(tegra20_primary_formats),
2184         .primary_formats = tegra20_primary_formats,
2185         .num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats),
2186         .overlay_formats = tegra20_overlay_formats,
2187         .modifiers = tegra20_modifiers,
2188         .has_win_a_without_filters = true,
2189         .has_win_c_without_vert_filter = true,
2190 };
2191
2192 static const struct tegra_dc_soc_info tegra30_dc_soc_info = {
2193         .supports_background_color = false,
2194         .supports_interlacing = false,
2195         .supports_cursor = false,
2196         .supports_block_linear = false,
2197         .has_legacy_blending = true,
2198         .pitch_align = 8,
2199         .has_powergate = false,
2200         .coupled_pm = false,
2201         .has_nvdisplay = false,
2202         .num_primary_formats = ARRAY_SIZE(tegra20_primary_formats),
2203         .primary_formats = tegra20_primary_formats,
2204         .num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats),
2205         .overlay_formats = tegra20_overlay_formats,
2206         .modifiers = tegra20_modifiers,
2207         .has_win_a_without_filters = false,
2208         .has_win_c_without_vert_filter = false,
2209 };
2210
2211 static const struct tegra_dc_soc_info tegra114_dc_soc_info = {
2212         .supports_background_color = false,
2213         .supports_interlacing = false,
2214         .supports_cursor = false,
2215         .supports_block_linear = false,
2216         .has_legacy_blending = true,
2217         .pitch_align = 64,
2218         .has_powergate = true,
2219         .coupled_pm = false,
2220         .has_nvdisplay = false,
2221         .num_primary_formats = ARRAY_SIZE(tegra114_primary_formats),
2222         .primary_formats = tegra114_primary_formats,
2223         .num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats),
2224         .overlay_formats = tegra114_overlay_formats,
2225         .modifiers = tegra20_modifiers,
2226         .has_win_a_without_filters = false,
2227         .has_win_c_without_vert_filter = false,
2228 };
2229
2230 static const struct tegra_dc_soc_info tegra124_dc_soc_info = {
2231         .supports_background_color = true,
2232         .supports_interlacing = true,
2233         .supports_cursor = true,
2234         .supports_block_linear = true,
2235         .has_legacy_blending = false,
2236         .pitch_align = 64,
2237         .has_powergate = true,
2238         .coupled_pm = false,
2239         .has_nvdisplay = false,
2240         .num_primary_formats = ARRAY_SIZE(tegra124_primary_formats),
2241         .primary_formats = tegra124_primary_formats,
2242         .num_overlay_formats = ARRAY_SIZE(tegra124_overlay_formats),
2243         .overlay_formats = tegra124_overlay_formats,
2244         .modifiers = tegra124_modifiers,
2245         .has_win_a_without_filters = false,
2246         .has_win_c_without_vert_filter = false,
2247 };
2248
2249 static const struct tegra_dc_soc_info tegra210_dc_soc_info = {
2250         .supports_background_color = true,
2251         .supports_interlacing = true,
2252         .supports_cursor = true,
2253         .supports_block_linear = true,
2254         .has_legacy_blending = false,
2255         .pitch_align = 64,
2256         .has_powergate = true,
2257         .coupled_pm = false,
2258         .has_nvdisplay = false,
2259         .num_primary_formats = ARRAY_SIZE(tegra114_primary_formats),
2260         .primary_formats = tegra114_primary_formats,
2261         .num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats),
2262         .overlay_formats = tegra114_overlay_formats,
2263         .modifiers = tegra124_modifiers,
2264         .has_win_a_without_filters = false,
2265         .has_win_c_without_vert_filter = false,
2266 };
2267
2268 static const struct tegra_windowgroup_soc tegra186_dc_wgrps[] = {
2269         {
2270                 .index = 0,
2271                 .dc = 0,
2272                 .windows = (const unsigned int[]) { 0 },
2273                 .num_windows = 1,
2274         }, {
2275                 .index = 1,
2276                 .dc = 1,
2277                 .windows = (const unsigned int[]) { 1 },
2278                 .num_windows = 1,
2279         }, {
2280                 .index = 2,
2281                 .dc = 1,
2282                 .windows = (const unsigned int[]) { 2 },
2283                 .num_windows = 1,
2284         }, {
2285                 .index = 3,
2286                 .dc = 2,
2287                 .windows = (const unsigned int[]) { 3 },
2288                 .num_windows = 1,
2289         }, {
2290                 .index = 4,
2291                 .dc = 2,
2292                 .windows = (const unsigned int[]) { 4 },
2293                 .num_windows = 1,
2294         }, {
2295                 .index = 5,
2296                 .dc = 2,
2297                 .windows = (const unsigned int[]) { 5 },
2298                 .num_windows = 1,
2299         },
2300 };
2301
2302 static const struct tegra_dc_soc_info tegra186_dc_soc_info = {
2303         .supports_background_color = true,
2304         .supports_interlacing = true,
2305         .supports_cursor = true,
2306         .supports_block_linear = true,
2307         .has_legacy_blending = false,
2308         .pitch_align = 64,
2309         .has_powergate = false,
2310         .coupled_pm = false,
2311         .has_nvdisplay = true,
2312         .wgrps = tegra186_dc_wgrps,
2313         .num_wgrps = ARRAY_SIZE(tegra186_dc_wgrps),
2314 };
2315
2316 static const struct tegra_windowgroup_soc tegra194_dc_wgrps[] = {
2317         {
2318                 .index = 0,
2319                 .dc = 0,
2320                 .windows = (const unsigned int[]) { 0 },
2321                 .num_windows = 1,
2322         }, {
2323                 .index = 1,
2324                 .dc = 1,
2325                 .windows = (const unsigned int[]) { 1 },
2326                 .num_windows = 1,
2327         }, {
2328                 .index = 2,
2329                 .dc = 1,
2330                 .windows = (const unsigned int[]) { 2 },
2331                 .num_windows = 1,
2332         }, {
2333                 .index = 3,
2334                 .dc = 2,
2335                 .windows = (const unsigned int[]) { 3 },
2336                 .num_windows = 1,
2337         }, {
2338                 .index = 4,
2339                 .dc = 2,
2340                 .windows = (const unsigned int[]) { 4 },
2341                 .num_windows = 1,
2342         }, {
2343                 .index = 5,
2344                 .dc = 2,
2345                 .windows = (const unsigned int[]) { 5 },
2346                 .num_windows = 1,
2347         },
2348 };
2349
2350 static const struct tegra_dc_soc_info tegra194_dc_soc_info = {
2351         .supports_background_color = true,
2352         .supports_interlacing = true,
2353         .supports_cursor = true,
2354         .supports_block_linear = true,
2355         .has_legacy_blending = false,
2356         .pitch_align = 64,
2357         .has_powergate = false,
2358         .coupled_pm = false,
2359         .has_nvdisplay = true,
2360         .wgrps = tegra194_dc_wgrps,
2361         .num_wgrps = ARRAY_SIZE(tegra194_dc_wgrps),
2362 };
2363
2364 static const struct of_device_id tegra_dc_of_match[] = {
2365         {
2366                 .compatible = "nvidia,tegra194-dc",
2367                 .data = &tegra194_dc_soc_info,
2368         }, {
2369                 .compatible = "nvidia,tegra186-dc",
2370                 .data = &tegra186_dc_soc_info,
2371         }, {
2372                 .compatible = "nvidia,tegra210-dc",
2373                 .data = &tegra210_dc_soc_info,
2374         }, {
2375                 .compatible = "nvidia,tegra124-dc",
2376                 .data = &tegra124_dc_soc_info,
2377         }, {
2378                 .compatible = "nvidia,tegra114-dc",
2379                 .data = &tegra114_dc_soc_info,
2380         }, {
2381                 .compatible = "nvidia,tegra30-dc",
2382                 .data = &tegra30_dc_soc_info,
2383         }, {
2384                 .compatible = "nvidia,tegra20-dc",
2385                 .data = &tegra20_dc_soc_info,
2386         }, {
2387                 /* sentinel */
2388         }
2389 };
2390 MODULE_DEVICE_TABLE(of, tegra_dc_of_match);
2391
2392 static int tegra_dc_parse_dt(struct tegra_dc *dc)
2393 {
2394         struct device_node *np;
2395         u32 value = 0;
2396         int err;
2397
2398         err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value);
2399         if (err < 0) {
2400                 dev_err(dc->dev, "missing \"nvidia,head\" property\n");
2401
2402                 /*
2403                  * If the nvidia,head property isn't present, try to find the
2404                  * correct head number by looking up the position of this
2405                  * display controller's node within the device tree. Assuming
2406                  * that the nodes are ordered properly in the DTS file and
2407                  * that the translation into a flattened device tree blob
2408                  * preserves that ordering this will actually yield the right
2409                  * head number.
2410                  *
2411                  * If those assumptions don't hold, this will still work for
2412                  * cases where only a single display controller is used.
2413                  */
2414                 for_each_matching_node(np, tegra_dc_of_match) {
2415                         if (np == dc->dev->of_node) {
2416                                 of_node_put(np);
2417                                 break;
2418                         }
2419
2420                         value++;
2421                 }
2422         }
2423
2424         dc->pipe = value;
2425
2426         return 0;
2427 }
2428
2429 static int tegra_dc_match_by_pipe(struct device *dev, void *data)
2430 {
2431         struct tegra_dc *dc = dev_get_drvdata(dev);
2432         unsigned int pipe = (unsigned long)data;
2433
2434         return dc->pipe == pipe;
2435 }
2436
2437 static int tegra_dc_couple(struct tegra_dc *dc)
2438 {
2439         /*
2440          * On Tegra20, DC1 requires DC0 to be taken out of reset in order to
2441          * be enabled, otherwise CPU hangs on writing to CMD_DISPLAY_COMMAND /
2442          * POWER_CONTROL registers during CRTC enabling.
2443          */
2444         if (dc->soc->coupled_pm && dc->pipe == 1) {
2445                 u32 flags = DL_FLAG_PM_RUNTIME | DL_FLAG_AUTOREMOVE_CONSUMER;
2446                 struct device_link *link;
2447                 struct device *partner;
2448
2449                 partner = driver_find_device(dc->dev->driver, NULL, NULL,
2450                                              tegra_dc_match_by_pipe);
2451                 if (!partner)
2452                         return -EPROBE_DEFER;
2453
2454                 link = device_link_add(dc->dev, partner, flags);
2455                 if (!link) {
2456                         dev_err(dc->dev, "failed to link controllers\n");
2457                         return -EINVAL;
2458                 }
2459
2460                 dev_dbg(dc->dev, "coupled to %s\n", dev_name(partner));
2461         }
2462
2463         return 0;
2464 }
2465
2466 static int tegra_dc_probe(struct platform_device *pdev)
2467 {
2468         struct resource *regs;
2469         struct tegra_dc *dc;
2470         int err;
2471
2472         dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
2473         if (!dc)
2474                 return -ENOMEM;
2475
2476         dc->soc = of_device_get_match_data(&pdev->dev);
2477
2478         INIT_LIST_HEAD(&dc->list);
2479         dc->dev = &pdev->dev;
2480
2481         err = tegra_dc_parse_dt(dc);
2482         if (err < 0)
2483                 return err;
2484
2485         err = tegra_dc_couple(dc);
2486         if (err < 0)
2487                 return err;
2488
2489         dc->clk = devm_clk_get(&pdev->dev, NULL);
2490         if (IS_ERR(dc->clk)) {
2491                 dev_err(&pdev->dev, "failed to get clock\n");
2492                 return PTR_ERR(dc->clk);
2493         }
2494
2495         dc->rst = devm_reset_control_get(&pdev->dev, "dc");
2496         if (IS_ERR(dc->rst)) {
2497                 dev_err(&pdev->dev, "failed to get reset\n");
2498                 return PTR_ERR(dc->rst);
2499         }
2500
2501         /* assert reset and disable clock */
2502         err = clk_prepare_enable(dc->clk);
2503         if (err < 0)
2504                 return err;
2505
2506         usleep_range(2000, 4000);
2507
2508         err = reset_control_assert(dc->rst);
2509         if (err < 0)
2510                 return err;
2511
2512         usleep_range(2000, 4000);
2513
2514         clk_disable_unprepare(dc->clk);
2515
2516         if (dc->soc->has_powergate) {
2517                 if (dc->pipe == 0)
2518                         dc->powergate = TEGRA_POWERGATE_DIS;
2519                 else
2520                         dc->powergate = TEGRA_POWERGATE_DISB;
2521
2522                 tegra_powergate_power_off(dc->powergate);
2523         }
2524
2525         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2526         dc->regs = devm_ioremap_resource(&pdev->dev, regs);
2527         if (IS_ERR(dc->regs))
2528                 return PTR_ERR(dc->regs);
2529
2530         dc->irq = platform_get_irq(pdev, 0);
2531         if (dc->irq < 0) {
2532                 dev_err(&pdev->dev, "failed to get IRQ\n");
2533                 return -ENXIO;
2534         }
2535
2536         err = tegra_dc_rgb_probe(dc);
2537         if (err < 0 && err != -ENODEV) {
2538                 dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err);
2539                 return err;
2540         }
2541
2542         platform_set_drvdata(pdev, dc);
2543         pm_runtime_enable(&pdev->dev);
2544
2545         INIT_LIST_HEAD(&dc->client.list);
2546         dc->client.ops = &dc_client_ops;
2547         dc->client.dev = &pdev->dev;
2548
2549         err = host1x_client_register(&dc->client);
2550         if (err < 0) {
2551                 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
2552                         err);
2553                 return err;
2554         }
2555
2556         return 0;
2557 }
2558
2559 static int tegra_dc_remove(struct platform_device *pdev)
2560 {
2561         struct tegra_dc *dc = platform_get_drvdata(pdev);
2562         int err;
2563
2564         err = host1x_client_unregister(&dc->client);
2565         if (err < 0) {
2566                 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
2567                         err);
2568                 return err;
2569         }
2570
2571         err = tegra_dc_rgb_remove(dc);
2572         if (err < 0) {
2573                 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err);
2574                 return err;
2575         }
2576
2577         pm_runtime_disable(&pdev->dev);
2578
2579         return 0;
2580 }
2581
2582 #ifdef CONFIG_PM
2583 static int tegra_dc_suspend(struct device *dev)
2584 {
2585         struct tegra_dc *dc = dev_get_drvdata(dev);
2586         int err;
2587
2588         err = reset_control_assert(dc->rst);
2589         if (err < 0) {
2590                 dev_err(dev, "failed to assert reset: %d\n", err);
2591                 return err;
2592         }
2593
2594         if (dc->soc->has_powergate)
2595                 tegra_powergate_power_off(dc->powergate);
2596
2597         clk_disable_unprepare(dc->clk);
2598
2599         return 0;
2600 }
2601
2602 static int tegra_dc_resume(struct device *dev)
2603 {
2604         struct tegra_dc *dc = dev_get_drvdata(dev);
2605         int err;
2606
2607         if (dc->soc->has_powergate) {
2608                 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk,
2609                                                         dc->rst);
2610                 if (err < 0) {
2611                         dev_err(dev, "failed to power partition: %d\n", err);
2612                         return err;
2613                 }
2614         } else {
2615                 err = clk_prepare_enable(dc->clk);
2616                 if (err < 0) {
2617                         dev_err(dev, "failed to enable clock: %d\n", err);
2618                         return err;
2619                 }
2620
2621                 err = reset_control_deassert(dc->rst);
2622                 if (err < 0) {
2623                         dev_err(dev, "failed to deassert reset: %d\n", err);
2624                         return err;
2625                 }
2626         }
2627
2628         return 0;
2629 }
2630 #endif
2631
2632 static const struct dev_pm_ops tegra_dc_pm_ops = {
2633         SET_RUNTIME_PM_OPS(tegra_dc_suspend, tegra_dc_resume, NULL)
2634 };
2635
2636 struct platform_driver tegra_dc_driver = {
2637         .driver = {
2638                 .name = "tegra-dc",
2639                 .of_match_table = tegra_dc_of_match,
2640                 .pm = &tegra_dc_pm_ops,
2641         },
2642         .probe = tegra_dc_probe,
2643         .remove = tegra_dc_remove,
2644 };