drivers/ide/arm/icside.c

   1 /*
   2  * linux/drivers/ide/arm/icside.c
   3  *
   4  * Copyright (c) 1996-2004 Russell King.
   5  *
   6  * Please note that this platform does not support 32-bit IDE IO.
   7  */
   8
   9 #include <linux/string.h>
  10 #include <linux/module.h>
  11 #include <linux/ioport.h>
  12 #include <linux/slab.h>
  13 #include <linux/blkdev.h>
  14 #include <linux/errno.h>
  15 #include <linux/hdreg.h>
  16 #include <linux/ide.h>
  17 #include <linux/dma-mapping.h>
  18 #include <linux/device.h>
  19 #include <linux/init.h>
  20 #include <linux/scatterlist.h>
  21
  22 #include <asm/dma.h>
  23 #include <asm/ecard.h>
  24 #include <asm/io.h>
  25
  26 #define ICS_IDENT_OFFSET                0x2280
  27
  28 #define ICS_ARCIN_V5_INTRSTAT           0x0000
  29 #define ICS_ARCIN_V5_INTROFFSET         0x0004
  30 #define ICS_ARCIN_V5_IDEOFFSET          0x2800
  31 #define ICS_ARCIN_V5_IDEALTOFFSET       0x2b80
  32 #define ICS_ARCIN_V5_IDESTEPPING        6
  33
  34 #define ICS_ARCIN_V6_IDEOFFSET_1        0x2000
  35 #define ICS_ARCIN_V6_INTROFFSET_1       0x2200
  36 #define ICS_ARCIN_V6_INTRSTAT_1         0x2290
  37 #define ICS_ARCIN_V6_IDEALTOFFSET_1     0x2380
  38 #define ICS_ARCIN_V6_IDEOFFSET_2        0x3000
  39 #define ICS_ARCIN_V6_INTROFFSET_2       0x3200
  40 #define ICS_ARCIN_V6_INTRSTAT_2         0x3290
  41 #define ICS_ARCIN_V6_IDEALTOFFSET_2     0x3380
  42 #define ICS_ARCIN_V6_IDESTEPPING        6
  43
  44 struct cardinfo {
  45         unsigned int dataoffset;
  46         unsigned int ctrloffset;
  47         unsigned int stepping;
  48 };
  49
  50 static struct cardinfo icside_cardinfo_v5 = {
  51         .dataoffset     = ICS_ARCIN_V5_IDEOFFSET,
  52         .ctrloffset     = ICS_ARCIN_V5_IDEALTOFFSET,
  53         .stepping       = ICS_ARCIN_V5_IDESTEPPING,
  54 };
  55
  56 static struct cardinfo icside_cardinfo_v6_1 = {
  57         .dataoffset     = ICS_ARCIN_V6_IDEOFFSET_1,
  58         .ctrloffset     = ICS_ARCIN_V6_IDEALTOFFSET_1,
  59         .stepping       = ICS_ARCIN_V6_IDESTEPPING,
  60 };
  61
  62 static struct cardinfo icside_cardinfo_v6_2 = {
  63         .dataoffset     = ICS_ARCIN_V6_IDEOFFSET_2,
  64         .ctrloffset     = ICS_ARCIN_V6_IDEALTOFFSET_2,
  65         .stepping       = ICS_ARCIN_V6_IDESTEPPING,
  66 };
  67
  68 struct icside_state {
  69         unsigned int channel;
  70         unsigned int enabled;
  71         void __iomem *irq_port;
  72         void __iomem *ioc_base;
  73         unsigned int type;
  74         /* parent device... until the IDE core gets one of its own */
  75         struct device *dev;
  76         ide_hwif_t *hwif[2];
  77 };
  78
  79 #define ICS_TYPE_A3IN   0
  80 #define ICS_TYPE_A3USER 1
  81 #define ICS_TYPE_V6     3
  82 #define ICS_TYPE_V5     15
  83 #define ICS_TYPE_NOTYPE ((unsigned int)-1)
  84
  85 /* ---------------- Version 5 PCB Support Functions --------------------- */
  86 /* Prototype: icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
  87  * Purpose  : enable interrupts from card
  88  */
  89 static void icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
  90 {
  91         struct icside_state *state = ec->irq_data;
  92
  93         writeb(0, state->irq_port + ICS_ARCIN_V5_INTROFFSET);
  94 }
  95
  96 /* Prototype: icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
  97  * Purpose  : disable interrupts from card
  98  */
  99 static void icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
 100 {
 101         struct icside_state *state = ec->irq_data;
 102
 103         readb(state->irq_port + ICS_ARCIN_V5_INTROFFSET);
 104 }
 105
 106 static const expansioncard_ops_t icside_ops_arcin_v5 = {
 107         .irqenable      = icside_irqenable_arcin_v5,
 108         .irqdisable     = icside_irqdisable_arcin_v5,
 109 };
 110
 111
 112 /* ---------------- Version 6 PCB Support Functions --------------------- */
 113 /* Prototype: icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
 114  * Purpose  : enable interrupts from card
 115  */
 116 static void icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
 117 {
 118         struct icside_state *state = ec->irq_data;
 119         void __iomem *base = state->irq_port;
 120
 121         state->enabled = 1;
 122
 123         switch (state->channel) {
 124         case 0:
 125                 writeb(0, base + ICS_ARCIN_V6_INTROFFSET_1);
 126                 readb(base + ICS_ARCIN_V6_INTROFFSET_2);
 127                 break;
 128         case 1:
 129                 writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2);
 130                 readb(base + ICS_ARCIN_V6_INTROFFSET_1);
 131                 break;
 132         }
 133 }
 134
 135 /* Prototype: icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
 136  * Purpose  : disable interrupts from card
 137  */
 138 static void icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
 139 {
 140         struct icside_state *state = ec->irq_data;
 141
 142         state->enabled = 0;
 143
 144         readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
 145         readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
 146 }
 147
 148 /* Prototype: icside_irqprobe(struct expansion_card *ec)
 149  * Purpose  : detect an active interrupt from card
 150  */
 151 static int icside_irqpending_arcin_v6(struct expansion_card *ec)
 152 {
 153         struct icside_state *state = ec->irq_data;
 154
 155         return readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_1) & 1 ||
 156                readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_2) & 1;
 157 }
 158
 159 static const expansioncard_ops_t icside_ops_arcin_v6 = {
 160         .irqenable      = icside_irqenable_arcin_v6,
 161         .irqdisable     = icside_irqdisable_arcin_v6,
 162         .irqpending     = icside_irqpending_arcin_v6,
 163 };
 164
 165 /*
 166  * Handle routing of interrupts.  This is called before
 167  * we write the command to the drive.
 168  */
 169 static void icside_maskproc(ide_drive_t *drive, int mask)
 170 {
 171         ide_hwif_t *hwif = HWIF(drive);
 172         struct icside_state *state = hwif->hwif_data;
 173         unsigned long flags;
 174
 175         local_irq_save(flags);
 176
 177         state->channel = hwif->channel;
 178
 179         if (state->enabled && !mask) {
 180                 switch (hwif->channel) {
 181                 case 0:
 182                         writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
 183                         readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
 184                         break;
 185                 case 1:
 186                         writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
 187                         readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
 188                         break;
 189                 }
 190         } else {
 191                 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
 192                 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
 193         }
 194
 195         local_irq_restore(flags);
 196 }
 197
 198 #ifdef CONFIG_BLK_DEV_IDEDMA_ICS
 199
 200 #ifndef CONFIG_IDEDMA_ICS_AUTO
 201 #warning CONFIG_IDEDMA_ICS_AUTO=n support is obsolete, and will be removed soon.
 202 #endif
 203
 204 /*
 205  * SG-DMA support.
 206  *
 207  * Similar to the BM-DMA, but we use the RiscPCs IOMD DMA controllers.
 208  * There is only one DMA controller per card, which means that only
 209  * one drive can be accessed at one time.  NOTE! We do not enforce that
 210  * here, but we rely on the main IDE driver spotting that both
 211  * interfaces use the same IRQ, which should guarantee this.
 212  */
 213
 214 static void icside_build_sglist(ide_drive_t *drive, struct request *rq)
 215 {
 216         ide_hwif_t *hwif = drive->hwif;
 217         struct icside_state *state = hwif->hwif_data;
 218         struct scatterlist *sg = hwif->sg_table;
 219
 220         ide_map_sg(drive, rq);
 221
 222         if (rq_data_dir(rq) == READ)
 223                 hwif->sg_dma_direction = DMA_FROM_DEVICE;
 224         else
 225                 hwif->sg_dma_direction = DMA_TO_DEVICE;
 226
 227         hwif->sg_nents = dma_map_sg(state->dev, sg, hwif->sg_nents,
 228                                     hwif->sg_dma_direction);
 229 }
 230
 231 /*
 232  * Configure the IOMD to give the appropriate timings for the transfer
 233  * mode being requested.  We take the advice of the ATA standards, and
 234  * calculate the cycle time based on the transfer mode, and the EIDE
 235  * MW DMA specs that the drive provides in the IDENTIFY command.
 236  *
 237  * We have the following IOMD DMA modes to choose from:
 238  *
 239  *      Type    Active          Recovery        Cycle
 240  *      A       250 (250)       312 (550)       562 (800)
 241  *      B       187             250             437
 242  *      C       125 (125)       125 (375)       250 (500)
 243  *      D       62              125             187
 244  *
 245  * (figures in brackets are actual measured timings)
 246  *
 247  * However, we also need to take care of the read/write active and
 248  * recovery timings:
 249  *
 250  *                      Read    Write
 251  *      Mode    Active  -- Recovery --  Cycle   IOMD type
 252  *      MW0     215     50      215     480     A
 253  *      MW1     80      50      50      150     C
 254  *      MW2     70      25      25      120     C
 255  */
 256 static int icside_set_speed(ide_drive_t *drive, u8 xfer_mode)
 257 {
 258         int on = 0, cycle_time = 0, use_dma_info = 0;
 259
 260         /*
 261          * Limit the transfer speed to MW_DMA_2.
 262          */
 263         if (xfer_mode > XFER_MW_DMA_2)
 264                 xfer_mode = XFER_MW_DMA_2;
 265
 266         switch (xfer_mode) {
 267         case XFER_MW_DMA_2:
 268                 cycle_time = 250;
 269                 use_dma_info = 1;
 270                 break;
 271
 272         case XFER_MW_DMA_1:
 273                 cycle_time = 250;
 274                 use_dma_info = 1;
 275                 break;
 276
 277         case XFER_MW_DMA_0:
 278                 cycle_time = 480;
 279                 break;
 280
 281         case XFER_SW_DMA_2:
 282         case XFER_SW_DMA_1:
 283         case XFER_SW_DMA_0:
 284                 cycle_time = 480;
 285                 break;
 286         }
 287
 288         /*
 289          * If we're going to be doing MW_DMA_1 or MW_DMA_2, we should
 290          * take care to note the values in the ID...
 291          */
 292         if (use_dma_info && drive->id->eide_dma_time > cycle_time)
 293                 cycle_time = drive->id->eide_dma_time;
 294
 295         drive->drive_data = cycle_time;
 296
 297         if (cycle_time && ide_config_drive_speed(drive, xfer_mode) == 0)
 298                 on = 1;
 299         else
 300                 drive->drive_data = 480;
 301
 302         printk("%s: %s selected (peak %dMB/s)\n", drive->name,
 303                 ide_xfer_verbose(xfer_mode), 2000 / drive->drive_data);
 304
 305         drive->current_speed = xfer_mode;
 306
 307         return on;
 308 }
 309
 310 static int icside_dma_host_off(ide_drive_t *drive)
 311 {
 312         return 0;
 313 }
 314
 315 static int icside_dma_off_quietly(ide_drive_t *drive)
 316 {
 317         drive->using_dma = 0;
 318         return icside_dma_host_off(drive);
 319 }
 320
 321 static int icside_dma_host_on(ide_drive_t *drive)
 322 {
 323         return 0;
 324 }
 325
 326 static int icside_dma_on(ide_drive_t *drive)
 327 {
 328         drive->using_dma = 1;
 329         return icside_dma_host_on(drive);
 330 }
 331
 332 static int icside_dma_check(ide_drive_t *drive)
 333 {
 334         struct hd_driveid *id = drive->id;
 335         ide_hwif_t *hwif = HWIF(drive);
 336         int xfer_mode = XFER_PIO_2;
 337         int on;
 338
 339         if (!(id->capability & 1) || !hwif->autodma)
 340                 goto out;
 341
 342         /*
 343          * Consult the list of known "bad" drives
 344          */
 345         if (__ide_dma_bad_drive(drive))
 346                 goto out;
 347
 348         /*
 349          * Enable DMA on any drive that has multiword DMA
 350          */
 351         if (id->field_valid & 2) {
 352                 xfer_mode = ide_dma_speed(drive, 0);
 353                 goto out;
 354         }
 355
 356         /*
 357          * Consult the list of known "good" drives
 358          */
 359         if (__ide_dma_good_drive(drive)) {
 360                 if (id->eide_dma_time > 150)
 361                         goto out;
 362                 xfer_mode = XFER_MW_DMA_1;
 363         }
 364
 365 out:
 366         on = icside_set_speed(drive, xfer_mode);
 367
 368         return on ? 0 : -1;
 369 }
 370
 371 static int icside_dma_end(ide_drive_t *drive)
 372 {
 373         ide_hwif_t *hwif = HWIF(drive);
 374         struct icside_state *state = hwif->hwif_data;
 375
 376         drive->waiting_for_dma = 0;
 377
 378         disable_dma(hwif->hw.dma);
 379
 380         /* Teardown mappings after DMA has completed. */
 381         dma_unmap_sg(state->dev, hwif->sg_table, hwif->sg_nents,
 382                      hwif->sg_dma_direction);
 383
 384         return get_dma_residue(hwif->hw.dma) != 0;
 385 }
 386
 387 static void icside_dma_start(ide_drive_t *drive)
 388 {
 389         ide_hwif_t *hwif = HWIF(drive);
 390
 391         /* We can not enable DMA on both channels simultaneously. */
 392         BUG_ON(dma_channel_active(hwif->hw.dma));
 393         enable_dma(hwif->hw.dma);
 394 }
 395
 396 static int icside_dma_setup(ide_drive_t *drive)
 397 {
 398         ide_hwif_t *hwif = HWIF(drive);
 399         struct request *rq = hwif->hwgroup->rq;
 400         unsigned int dma_mode;
 401
 402         if (rq_data_dir(rq))
 403                 dma_mode = DMA_MODE_WRITE;
 404         else
 405                 dma_mode = DMA_MODE_READ;
 406
 407         /*
 408          * We can not enable DMA on both channels.
 409          */
 410         BUG_ON(dma_channel_active(hwif->hw.dma));
 411
 412         icside_build_sglist(drive, rq);
 413
 414         /*
 415          * Ensure that we have the right interrupt routed.
 416          */
 417         icside_maskproc(drive, 0);
 418
 419         /*
 420          * Route the DMA signals to the correct interface.
 421          */
 422         writeb(hwif->select_data, hwif->config_data);
 423
 424         /*
 425          * Select the correct timing for this drive.
 426          */
 427         set_dma_speed(hwif->hw.dma, drive->drive_data);
 428
 429         /*
 430          * Tell the DMA engine about the SG table and
 431          * data direction.
 432          */
 433         set_dma_sg(hwif->hw.dma, hwif->sg_table, hwif->sg_nents);
 434         set_dma_mode(hwif->hw.dma, dma_mode);
 435
 436         drive->waiting_for_dma = 1;
 437
 438         return 0;
 439 }
 440
 441 static void icside_dma_exec_cmd(ide_drive_t *drive, u8 cmd)
 442 {
 443         /* issue cmd to drive */
 444         ide_execute_command(drive, cmd, ide_dma_intr, 2 * WAIT_CMD, NULL);
 445 }
 446
 447 static int icside_dma_test_irq(ide_drive_t *drive)
 448 {
 449         ide_hwif_t *hwif = HWIF(drive);
 450         struct icside_state *state = hwif->hwif_data;
 451
 452         return readb(state->irq_port +
 453                      (hwif->channel ?
 454                         ICS_ARCIN_V6_INTRSTAT_2 :
 455                         ICS_ARCIN_V6_INTRSTAT_1)) & 1;
 456 }
 457
 458 static int icside_dma_timeout(ide_drive_t *drive)
 459 {
 460         printk(KERN_ERR "%s: DMA timeout occurred: ", drive->name);
 461
 462         if (icside_dma_test_irq(drive))
 463                 return 0;
 464
 465         ide_dump_status(drive, "DMA timeout",
 466                 HWIF(drive)->INB(IDE_STATUS_REG));
 467
 468         return icside_dma_end(drive);
 469 }
 470
 471 static int icside_dma_lostirq(ide_drive_t *drive)
 472 {
 473         printk(KERN_ERR "%s: IRQ lost\n", drive->name);
 474         return 1;
 475 }
 476
 477 static void icside_dma_init(ide_hwif_t *hwif)
 478 {
 479         int autodma = 0;
 480
 481 #ifdef CONFIG_IDEDMA_ICS_AUTO
 482         autodma = 1;
 483 #endif
 484
 485         printk("    %s: SG-DMA", hwif->name);
 486
 487         hwif->atapi_dma         = 1;
 488         hwif->mwdma_mask        = 7; /* MW0..2 */
 489         hwif->swdma_mask        = 7; /* SW0..2 */
 490
 491         hwif->dmatable_cpu      = NULL;
 492         hwif->dmatable_dma      = 0;
 493         hwif->speedproc         = icside_set_speed;
 494         hwif->autodma           = autodma;
 495
 496         hwif->ide_dma_check     = icside_dma_check;
 497         hwif->ide_dma_host_off  = icside_dma_host_off;
 498         hwif->ide_dma_off_quietly = icside_dma_off_quietly;
 499         hwif->ide_dma_host_on   = icside_dma_host_on;
 500         hwif->ide_dma_on        = icside_dma_on;
 501         hwif->dma_setup         = icside_dma_setup;
 502         hwif->dma_exec_cmd      = icside_dma_exec_cmd;
 503         hwif->dma_start         = icside_dma_start;
 504         hwif->ide_dma_end       = icside_dma_end;
 505         hwif->ide_dma_test_irq  = icside_dma_test_irq;
 506         hwif->ide_dma_timeout   = icside_dma_timeout;
 507         hwif->ide_dma_lostirq   = icside_dma_lostirq;
 508
 509         hwif->drives[0].autodma = hwif->autodma;
 510         hwif->drives[1].autodma = hwif->autodma;
 511
 512         printk(" capable%s\n", hwif->autodma ? ", auto-enable" : "");
 513 }
 514 #else
 515 #define icside_dma_init(hwif)   (0)
 516 #endif
 517
 518 static ide_hwif_t *icside_find_hwif(unsigned long dataport)
 519 {
 520         ide_hwif_t *hwif;
 521         int index;
 522
 523         for (index = 0; index < MAX_HWIFS; ++index) {
 524                 hwif = &ide_hwifs[index];
 525                 if (hwif->io_ports[IDE_DATA_OFFSET] == dataport)
 526                         goto found;
 527         }
 528
 529         for (index = 0; index < MAX_HWIFS; ++index) {
 530                 hwif = &ide_hwifs[index];
 531                 if (!hwif->io_ports[IDE_DATA_OFFSET])
 532                         goto found;
 533         }
 534
 535         hwif = NULL;
 536 found:
 537         return hwif;
 538 }
 539
 540 static ide_hwif_t *
 541 icside_setup(void __iomem *base, struct cardinfo *info, struct expansion_card *ec)
 542 {
 543         unsigned long port = (unsigned long)base + info->dataoffset;
 544         ide_hwif_t *hwif;
 545
 546         hwif = icside_find_hwif(port);
 547         if (hwif) {
 548                 int i;
 549
 550                 memset(&hwif->hw, 0, sizeof(hw_regs_t));
 551
 552                 /*
 553                  * Ensure we're using MMIO
 554                  */
 555                 default_hwif_mmiops(hwif);
 556                 hwif->mmio = 1;
 557
 558                 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
 559                         hwif->hw.io_ports[i] = port;
 560                         hwif->io_ports[i] = port;
 561                         port += 1 << info->stepping;
 562                 }
 563                 hwif->hw.io_ports[IDE_CONTROL_OFFSET] = (unsigned long)base + info->ctrloffset;
 564                 hwif->io_ports[IDE_CONTROL_OFFSET] = (unsigned long)base + info->ctrloffset;
 565                 hwif->hw.irq  = ec->irq;
 566                 hwif->irq     = ec->irq;
 567                 hwif->noprobe = 0;
 568                 hwif->chipset = ide_acorn;
 569                 hwif->gendev.parent = &ec->dev;
 570         }
 571
 572         return hwif;
 573 }
 574
 575 static int __init
 576 icside_register_v5(struct icside_state *state, struct expansion_card *ec)
 577 {
 578         ide_hwif_t *hwif;
 579         void __iomem *base;
 580
 581         base = ioremap(ecard_resource_start(ec, ECARD_RES_MEMC),
 582                        ecard_resource_len(ec, ECARD_RES_MEMC));
 583         if (!base)
 584                 return -ENOMEM;
 585
 586         state->irq_port = base;
 587
 588         ec->irqaddr  = base + ICS_ARCIN_V5_INTRSTAT;
 589         ec->irqmask  = 1;
 590         ec->irq_data = state;
 591         ec->ops      = &icside_ops_arcin_v5;
 592
 593         /*
 594          * Be on the safe side - disable interrupts
 595          */
 596         icside_irqdisable_arcin_v5(ec, 0);
 597
 598         hwif = icside_setup(base, &icside_cardinfo_v5, ec);
 599         if (!hwif) {
 600                 iounmap(base);
 601                 return -ENODEV;
 602         }
 603
 604         state->hwif[0] = hwif;
 605
 606         probe_hwif_init(hwif);
 607         create_proc_ide_interfaces();
 608
 609         return 0;
 610 }
 611
 612 static int __init
 613 icside_register_v6(struct icside_state *state, struct expansion_card *ec)
 614 {
 615         ide_hwif_t *hwif, *mate;
 616         void __iomem *ioc_base, *easi_base;
 617         unsigned int sel = 0;
 618         int ret;
 619
 620         ioc_base = ioremap(ecard_resource_start(ec, ECARD_RES_IOCFAST),
 621                            ecard_resource_len(ec, ECARD_RES_IOCFAST));
 622         if (!ioc_base) {
 623                 ret = -ENOMEM;
 624                 goto out;
 625         }
 626
 627         easi_base = ioc_base;
 628
 629         if (ecard_resource_flags(ec, ECARD_RES_EASI)) {
 630                 easi_base = ioremap(ecard_resource_start(ec, ECARD_RES_EASI),
 631                                     ecard_resource_len(ec, ECARD_RES_EASI));
 632                 if (!easi_base) {
 633                         ret = -ENOMEM;
 634                         goto unmap_slot;
 635                 }
 636
 637                 /*
 638                  * Enable access to the EASI region.
 639                  */
 640                 sel = 1 << 5;
 641         }
 642
 643         writeb(sel, ioc_base);
 644
 645         ec->irq_data      = state;
 646         ec->ops           = &icside_ops_arcin_v6;
 647
 648         state->irq_port   = easi_base;
 649         state->ioc_base   = ioc_base;
 650
 651         /*
 652          * Be on the safe side - disable interrupts
 653          */
 654         icside_irqdisable_arcin_v6(ec, 0);
 655
 656         /*
 657          * Find and register the interfaces.
 658          */
 659         hwif = icside_setup(easi_base, &icside_cardinfo_v6_1, ec);
 660         mate = icside_setup(easi_base, &icside_cardinfo_v6_2, ec);
 661
 662         if (!hwif || !mate) {
 663                 ret = -ENODEV;
 664                 goto unmap_port;
 665         }
 666
 667         state->hwif[0]    = hwif;
 668         state->hwif[1]    = mate;
 669
 670         hwif->maskproc    = icside_maskproc;
 671         hwif->channel     = 0;
 672         hwif->hwif_data   = state;
 673         hwif->mate        = mate;
 674         hwif->serialized  = 1;
 675         hwif->config_data = (unsigned long)ioc_base;
 676         hwif->select_data = sel;
 677         hwif->hw.dma      = ec->dma;
 678
 679         mate->maskproc    = icside_maskproc;
 680         mate->channel     = 1;
 681         mate->hwif_data   = state;
 682         mate->mate        = hwif;
 683         mate->serialized  = 1;
 684         mate->config_data = (unsigned long)ioc_base;
 685         mate->select_data = sel | 1;
 686         mate->hw.dma      = ec->dma;
 687
 688         if (ec->dma != NO_DMA && !request_dma(ec->dma, hwif->name)) {
 689                 icside_dma_init(hwif);
 690                 icside_dma_init(mate);
 691         }
 692
 693         probe_hwif_init(hwif);
 694         probe_hwif_init(mate);
 695         create_proc_ide_interfaces();
 696
 697         return 0;
 698
 699  unmap_port:
 700         if (easi_base != ioc_base)
 701                 iounmap(easi_base);
 702  unmap_slot:
 703         iounmap(ioc_base);
 704  out:
 705         return ret;
 706 }
 707
 708 static int __devinit
 709 icside_probe(struct expansion_card *ec, const struct ecard_id *id)
 710 {
 711         struct icside_state *state;
 712         void __iomem *idmem;
 713         int ret;
 714
 715         ret = ecard_request_resources(ec);
 716         if (ret)
 717                 goto out;
 718
 719         state = kmalloc(sizeof(struct icside_state), GFP_KERNEL);
 720         if (!state) {
 721                 ret = -ENOMEM;
 722                 goto release;
 723         }
 724
 725         memset(state, 0, sizeof(state));
 726         state->type     = ICS_TYPE_NOTYPE;
 727         state->dev      = &ec->dev;
 728
 729         idmem = ioremap(ecard_resource_start(ec, ECARD_RES_IOCFAST),
 730                         ecard_resource_len(ec, ECARD_RES_IOCFAST));
 731         if (idmem) {
 732                 unsigned int type;
 733
 734                 type = readb(idmem + ICS_IDENT_OFFSET) & 1;
 735                 type |= (readb(idmem + ICS_IDENT_OFFSET + 4) & 1) << 1;
 736                 type |= (readb(idmem + ICS_IDENT_OFFSET + 8) & 1) << 2;
 737                 type |= (readb(idmem + ICS_IDENT_OFFSET + 12) & 1) << 3;
 738                 iounmap(idmem);
 739
 740                 state->type = type;
 741         }
 742
 743         switch (state->type) {
 744         case ICS_TYPE_A3IN:
 745                 dev_warn(&ec->dev, "A3IN unsupported\n");
 746                 ret = -ENODEV;
 747                 break;
 748
 749         case ICS_TYPE_A3USER:
 750                 dev_warn(&ec->dev, "A3USER unsupported\n");
 751                 ret = -ENODEV;
 752                 break;
 753
 754         case ICS_TYPE_V5:
 755                 ret = icside_register_v5(state, ec);
 756                 break;
 757
 758         case ICS_TYPE_V6:
 759                 ret = icside_register_v6(state, ec);
 760                 break;
 761
 762         default:
 763                 dev_warn(&ec->dev, "unknown interface type\n");
 764                 ret = -ENODEV;
 765                 break;
 766         }
 767
 768         if (ret == 0) {
 769                 ecard_set_drvdata(ec, state);
 770                 goto out;
 771         }
 772
 773         kfree(state);
 774  release:
 775         ecard_release_resources(ec);
 776  out:
 777         return ret;
 778 }
 779
 780 static void __devexit icside_remove(struct expansion_card *ec)
 781 {
 782         struct icside_state *state = ecard_get_drvdata(ec);
 783
 784         switch (state->type) {
 785         case ICS_TYPE_V5:
 786                 /* FIXME: tell IDE to stop using the interface */
 787
 788                 /* Disable interrupts */
 789                 icside_irqdisable_arcin_v5(ec, 0);
 790                 break;
 791
 792         case ICS_TYPE_V6:
 793                 /* FIXME: tell IDE to stop using the interface */
 794                 if (ec->dma != NO_DMA)
 795                         free_dma(ec->dma);
 796
 797                 /* Disable interrupts */
 798                 icside_irqdisable_arcin_v6(ec, 0);
 799
 800                 /* Reset the ROM pointer/EASI selection */
 801                 writeb(0, state->ioc_base);
 802                 break;
 803         }
 804
 805         ecard_set_drvdata(ec, NULL);
 806         ec->ops = NULL;
 807         ec->irq_data = NULL;
 808
 809         if (state->ioc_base)
 810                 iounmap(state->ioc_base);
 811         if (state->ioc_base != state->irq_port)
 812                 iounmap(state->irq_port);
 813
 814         kfree(state);
 815         ecard_release_resources(ec);
 816 }
 817
 818 static void icside_shutdown(struct expansion_card *ec)
 819 {
 820         struct icside_state *state = ecard_get_drvdata(ec);
 821         unsigned long flags;
 822
 823         /*
 824          * Disable interrupts from this card.  We need to do
 825          * this before disabling EASI since we may be accessing
 826          * this register via that region.
 827          */
 828         local_irq_save(flags);
 829         ec->ops->irqdisable(ec, 0);
 830         local_irq_restore(flags);
 831
 832         /*
 833          * Reset the ROM pointer so that we can read the ROM
 834          * after a soft reboot.  This also disables access to
 835          * the IDE taskfile via the EASI region.
 836          */
 837         if (state->ioc_base)
 838                 writeb(0, state->ioc_base);
 839 }
 840
 841 static const struct ecard_id icside_ids[] = {
 842         { MANU_ICS,  PROD_ICS_IDE  },
 843         { MANU_ICS2, PROD_ICS2_IDE },
 844         { 0xffff, 0xffff }
 845 };
 846
 847 static struct ecard_driver icside_driver = {
 848         .probe          = icside_probe,
 849         .remove         = __devexit_p(icside_remove),
 850         .shutdown       = icside_shutdown,
 851         .id_table       = icside_ids,
 852         .drv = {
 853                 .name   = "icside",
 854         },
 855 };
 856
 857 static int __init icside_init(void)
 858 {
 859         return ecard_register_driver(&icside_driver);
 860 }
 861
 862 MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
 863 MODULE_LICENSE("GPL");
 864 MODULE_DESCRIPTION("ICS IDE driver");
 865
 866 module_init(icside_init);