2 * linux/drivers/ide/pci/aec62xx.c Version 0.21 Apr 21, 2007
4 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
5 * Copyright (C) 2007 MontaVista Software, Inc. <source@mvista.com>
9 #include <linux/module.h>
10 #include <linux/types.h>
11 #include <linux/pci.h>
12 #include <linux/delay.h>
13 #include <linux/hdreg.h>
14 #include <linux/ide.h>
15 #include <linux/init.h>
19 struct chipset_bus_clock_list_entry {
25 static const struct chipset_bus_clock_list_entry aec6xxx_33_base [] = {
26 { XFER_UDMA_6, 0x31, 0x07 },
27 { XFER_UDMA_5, 0x31, 0x06 },
28 { XFER_UDMA_4, 0x31, 0x05 },
29 { XFER_UDMA_3, 0x31, 0x04 },
30 { XFER_UDMA_2, 0x31, 0x03 },
31 { XFER_UDMA_1, 0x31, 0x02 },
32 { XFER_UDMA_0, 0x31, 0x01 },
34 { XFER_MW_DMA_2, 0x31, 0x00 },
35 { XFER_MW_DMA_1, 0x31, 0x00 },
36 { XFER_MW_DMA_0, 0x0a, 0x00 },
37 { XFER_PIO_4, 0x31, 0x00 },
38 { XFER_PIO_3, 0x33, 0x00 },
39 { XFER_PIO_2, 0x08, 0x00 },
40 { XFER_PIO_1, 0x0a, 0x00 },
41 { XFER_PIO_0, 0x00, 0x00 },
45 static const struct chipset_bus_clock_list_entry aec6xxx_34_base [] = {
46 { XFER_UDMA_6, 0x41, 0x06 },
47 { XFER_UDMA_5, 0x41, 0x05 },
48 { XFER_UDMA_4, 0x41, 0x04 },
49 { XFER_UDMA_3, 0x41, 0x03 },
50 { XFER_UDMA_2, 0x41, 0x02 },
51 { XFER_UDMA_1, 0x41, 0x01 },
52 { XFER_UDMA_0, 0x41, 0x01 },
54 { XFER_MW_DMA_2, 0x41, 0x00 },
55 { XFER_MW_DMA_1, 0x42, 0x00 },
56 { XFER_MW_DMA_0, 0x7a, 0x00 },
57 { XFER_PIO_4, 0x41, 0x00 },
58 { XFER_PIO_3, 0x43, 0x00 },
59 { XFER_PIO_2, 0x78, 0x00 },
60 { XFER_PIO_1, 0x7a, 0x00 },
61 { XFER_PIO_0, 0x70, 0x00 },
66 ((struct chipset_bus_clock_list_entry *) pci_get_drvdata((D)))
70 * TO DO: active tuning and correction of cards without a bios.
72 static u8 pci_bus_clock_list (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
74 for ( ; chipset_table->xfer_speed ; chipset_table++)
75 if (chipset_table->xfer_speed == speed) {
76 return chipset_table->chipset_settings;
78 return chipset_table->chipset_settings;
81 static u8 pci_bus_clock_list_ultra (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
83 for ( ; chipset_table->xfer_speed ; chipset_table++)
84 if (chipset_table->xfer_speed == speed) {
85 return chipset_table->ultra_settings;
87 return chipset_table->ultra_settings;
90 static int aec6210_tune_chipset (ide_drive_t *drive, u8 xferspeed)
92 ide_hwif_t *hwif = HWIF(drive);
93 struct pci_dev *dev = hwif->pci_dev;
95 u8 speed = ide_rate_filter(drive, xferspeed);
96 u8 ultra = 0, ultra_conf = 0;
97 u8 tmp0 = 0, tmp1 = 0, tmp2 = 0;
100 local_irq_save(flags);
101 /* 0x40|(2*drive->dn): Active, 0x41|(2*drive->dn): Recovery */
102 pci_read_config_word(dev, 0x40|(2*drive->dn), &d_conf);
103 tmp0 = pci_bus_clock_list(speed, BUSCLOCK(dev));
104 d_conf = ((tmp0 & 0xf0) << 4) | (tmp0 & 0xf);
105 pci_write_config_word(dev, 0x40|(2*drive->dn), d_conf);
109 pci_read_config_byte(dev, 0x54, &ultra);
110 tmp1 = ((0x00 << (2*drive->dn)) | (ultra & ~(3 << (2*drive->dn))));
111 ultra_conf = pci_bus_clock_list_ultra(speed, BUSCLOCK(dev));
112 tmp2 = ((ultra_conf << (2*drive->dn)) | (tmp1 & ~(3 << (2*drive->dn))));
113 pci_write_config_byte(dev, 0x54, tmp2);
114 local_irq_restore(flags);
115 return(ide_config_drive_speed(drive, speed));
118 static int aec6260_tune_chipset (ide_drive_t *drive, u8 xferspeed)
120 ide_hwif_t *hwif = HWIF(drive);
121 struct pci_dev *dev = hwif->pci_dev;
122 u8 speed = ide_rate_filter(drive, xferspeed);
123 u8 unit = (drive->select.b.unit & 0x01);
124 u8 tmp1 = 0, tmp2 = 0;
125 u8 ultra = 0, drive_conf = 0, ultra_conf = 0;
128 local_irq_save(flags);
129 /* high 4-bits: Active, low 4-bits: Recovery */
130 pci_read_config_byte(dev, 0x40|drive->dn, &drive_conf);
131 drive_conf = pci_bus_clock_list(speed, BUSCLOCK(dev));
132 pci_write_config_byte(dev, 0x40|drive->dn, drive_conf);
134 pci_read_config_byte(dev, (0x44|hwif->channel), &ultra);
135 tmp1 = ((0x00 << (4*unit)) | (ultra & ~(7 << (4*unit))));
136 ultra_conf = pci_bus_clock_list_ultra(speed, BUSCLOCK(dev));
137 tmp2 = ((ultra_conf << (4*unit)) | (tmp1 & ~(7 << (4*unit))));
138 pci_write_config_byte(dev, (0x44|hwif->channel), tmp2);
139 local_irq_restore(flags);
140 return(ide_config_drive_speed(drive, speed));
143 static int aec62xx_tune_chipset (ide_drive_t *drive, u8 speed)
145 switch (HWIF(drive)->pci_dev->device) {
146 case PCI_DEVICE_ID_ARTOP_ATP865:
147 case PCI_DEVICE_ID_ARTOP_ATP865R:
148 case PCI_DEVICE_ID_ARTOP_ATP860:
149 case PCI_DEVICE_ID_ARTOP_ATP860R:
150 return ((int) aec6260_tune_chipset(drive, speed));
151 case PCI_DEVICE_ID_ARTOP_ATP850UF:
152 return ((int) aec6210_tune_chipset(drive, speed));
158 static int config_chipset_for_dma (ide_drive_t *drive)
160 u8 speed = ide_max_dma_mode(drive);
165 (void) aec62xx_tune_chipset(drive, speed);
166 return ide_dma_enable(drive);
169 static void aec62xx_tune_drive (ide_drive_t *drive, u8 pio)
171 pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
172 (void) aec62xx_tune_chipset(drive, pio + XFER_PIO_0);
175 static int aec62xx_config_drive_xfer_rate (ide_drive_t *drive)
177 if (ide_use_dma(drive) && config_chipset_for_dma(drive))
180 if (ide_use_fast_pio(drive))
181 aec62xx_tune_drive(drive, 255);
186 static int aec62xx_irq_timeout (ide_drive_t *drive)
188 ide_hwif_t *hwif = HWIF(drive);
189 struct pci_dev *dev = hwif->pci_dev;
191 switch(dev->device) {
192 case PCI_DEVICE_ID_ARTOP_ATP860:
193 case PCI_DEVICE_ID_ARTOP_ATP860R:
194 case PCI_DEVICE_ID_ARTOP_ATP865:
195 case PCI_DEVICE_ID_ARTOP_ATP865R:
196 printk(" AEC62XX time out ");
203 static unsigned int __devinit init_chipset_aec62xx(struct pci_dev *dev, const char *name)
205 int bus_speed = system_bus_clock();
207 if (dev->resource[PCI_ROM_RESOURCE].start) {
208 pci_write_config_dword(dev, PCI_ROM_ADDRESS, dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
209 printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n", name,
210 (unsigned long)dev->resource[PCI_ROM_RESOURCE].start);
214 pci_set_drvdata(dev, (void *) aec6xxx_33_base);
216 pci_set_drvdata(dev, (void *) aec6xxx_34_base);
218 /* These are necessary to get AEC6280 Macintosh cards to work */
219 if ((dev->device == PCI_DEVICE_ID_ARTOP_ATP865) ||
220 (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R)) {
221 u8 reg49h = 0, reg4ah = 0;
222 /* Clear reset and test bits. */
223 pci_read_config_byte(dev, 0x49, ®49h);
224 pci_write_config_byte(dev, 0x49, reg49h & ~0x30);
225 /* Enable chip interrupt output. */
226 pci_read_config_byte(dev, 0x4a, ®4ah);
227 pci_write_config_byte(dev, 0x4a, reg4ah & ~0x01);
228 /* Enable burst mode. */
229 pci_read_config_byte(dev, 0x4a, ®4ah);
230 pci_write_config_byte(dev, 0x4a, reg4ah | 0x80);
236 static void __devinit init_hwif_aec62xx(ide_hwif_t *hwif)
238 struct pci_dev *dev = hwif->pci_dev;
241 hwif->tuneproc = &aec62xx_tune_drive;
242 hwif->speedproc = &aec62xx_tune_chipset;
244 if (dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF)
245 hwif->serialized = hwif->channel;
248 hwif->mate->serialized = hwif->serialized;
250 if (!hwif->dma_base) {
251 hwif->drives[0].autotune = 1;
252 hwif->drives[1].autotune = 1;
256 hwif->ultra_mask = hwif->cds->udma_mask;
258 /* atp865 and atp865r */
259 if (hwif->ultra_mask == 0x3f) {
260 /* check bit 0x10 of DMA status register */
261 if (inb(pci_resource_start(dev, 4) + 2) & 0x10)
262 hwif->ultra_mask = 0x7f; /* udma0-6 */
265 hwif->mwdma_mask = 0x07;
267 hwif->ide_dma_check = &aec62xx_config_drive_xfer_rate;
268 hwif->ide_dma_lostirq = &aec62xx_irq_timeout;
272 hwif->drives[0].autodma = hwif->autodma;
273 hwif->drives[1].autodma = hwif->autodma;
276 static void __devinit init_dma_aec62xx(ide_hwif_t *hwif, unsigned long dmabase)
278 struct pci_dev *dev = hwif->pci_dev;
280 if (dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF) {
284 spin_lock_irqsave(&ide_lock, flags);
285 pci_read_config_byte(dev, 0x54, ®54h);
286 pci_write_config_byte(dev, 0x54, reg54h & ~(hwif->channel ? 0xF0 : 0x0F));
287 spin_unlock_irqrestore(&ide_lock, flags);
290 pci_read_config_byte(hwif->pci_dev, 0x49, &ata66);
291 if (!(hwif->udma_four))
292 hwif->udma_four = (ata66&(hwif->channel?0x02:0x01))?0:1;
295 ide_setup_dma(hwif, dmabase, 8);
298 static int __devinit init_setup_aec62xx(struct pci_dev *dev, ide_pci_device_t *d)
300 return ide_setup_pci_device(dev, d);
303 static int __devinit init_setup_aec6x80(struct pci_dev *dev, ide_pci_device_t *d)
305 unsigned long bar4reg = pci_resource_start(dev, 4);
307 if (inb(bar4reg+2) & 0x10) {
308 strcpy(d->name, "AEC6880");
309 if (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R)
310 strcpy(d->name, "AEC6880R");
312 strcpy(d->name, "AEC6280");
313 if (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R)
314 strcpy(d->name, "AEC6280R");
317 return ide_setup_pci_device(dev, d);
320 static ide_pci_device_t aec62xx_chipsets[] __devinitdata = {
323 .init_setup = init_setup_aec62xx,
324 .init_chipset = init_chipset_aec62xx,
325 .init_hwif = init_hwif_aec62xx,
326 .init_dma = init_dma_aec62xx,
329 .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
330 .bootable = OFF_BOARD,
331 .udma_mask = 0x07, /* udma0-2 */
334 .init_setup = init_setup_aec62xx,
335 .init_chipset = init_chipset_aec62xx,
336 .init_hwif = init_hwif_aec62xx,
337 .init_dma = init_dma_aec62xx,
339 .autodma = NOAUTODMA,
340 .bootable = OFF_BOARD,
341 .udma_mask = 0x1f, /* udma0-4 */
344 .init_setup = init_setup_aec62xx,
345 .init_chipset = init_chipset_aec62xx,
346 .init_hwif = init_hwif_aec62xx,
347 .init_dma = init_dma_aec62xx,
350 .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
351 .bootable = NEVER_BOARD,
352 .udma_mask = 0x1f, /* udma0-4 */
355 .init_setup = init_setup_aec6x80,
356 .init_chipset = init_chipset_aec62xx,
357 .init_hwif = init_hwif_aec62xx,
358 .init_dma = init_dma_aec62xx,
361 .bootable = OFF_BOARD,
362 .udma_mask = 0x3f, /* udma0-5 */
365 .init_setup = init_setup_aec6x80,
366 .init_chipset = init_chipset_aec62xx,
367 .init_hwif = init_hwif_aec62xx,
368 .init_dma = init_dma_aec62xx,
371 .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
372 .bootable = OFF_BOARD,
373 .udma_mask = 0x3f, /* udma0-5 */
378 * aec62xx_init_one - called when a AEC is found
379 * @dev: the aec62xx device
380 * @id: the matching pci id
382 * Called when the PCI registration layer (or the IDE initialization)
383 * finds a device matching our IDE device tables.
386 static int __devinit aec62xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
388 ide_pci_device_t *d = &aec62xx_chipsets[id->driver_data];
390 return d->init_setup(dev, d);
393 static struct pci_device_id aec62xx_pci_tbl[] = {
394 { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP850UF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
395 { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
396 { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP860R, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
397 { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP865, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 },
398 { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP865R, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
401 MODULE_DEVICE_TABLE(pci, aec62xx_pci_tbl);
403 static struct pci_driver driver = {
404 .name = "AEC62xx_IDE",
405 .id_table = aec62xx_pci_tbl,
406 .probe = aec62xx_init_one,
409 static int __init aec62xx_ide_init(void)
411 return ide_pci_register_driver(&driver);
414 module_init(aec62xx_ide_init);
416 MODULE_AUTHOR("Andre Hedrick");
417 MODULE_DESCRIPTION("PCI driver module for ARTOP AEC62xx IDE");
418 MODULE_LICENSE("GPL");