2 * linux/drivers/ide/pci/pdc202xx_old.c Version 0.50 Mar 3, 2007
4 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
5 * Copyright (C) 2006-2007 MontaVista Software, Inc.
6 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
8 * Promise Ultra33 cards with BIOS v1.20 through 1.28 will need this
9 * compiled into the kernel if you have more than one card installed.
10 * Note that BIOS v1.29 is reported to fix the problem. Since this is
11 * safe chipset tuning, including this support is harmless
13 * Promise Ultra66 cards with BIOS v1.11 this
14 * compiled into the kernel if you have more than one card installed.
16 * Promise Ultra100 cards.
18 * The latest chipset code will support the following ::
19 * Three Ultra33 controllers and 12 drives.
20 * 8 are UDMA supported and 4 are limited to DMA mode 2 multi-word.
21 * The 8/4 ratio is a BIOS code limit by promise.
23 * UNLESS you enable "CONFIG_PDC202XX_BURST"
28 * Portions Copyright (C) 1999 Promise Technology, Inc.
29 * Author: Frank Tiernan (frankt@promise.com)
30 * Released under terms of General Public License
33 #include <linux/types.h>
34 #include <linux/module.h>
35 #include <linux/kernel.h>
36 #include <linux/delay.h>
37 #include <linux/timer.h>
39 #include <linux/ioport.h>
40 #include <linux/blkdev.h>
41 #include <linux/hdreg.h>
42 #include <linux/interrupt.h>
43 #include <linux/pci.h>
44 #include <linux/init.h>
45 #include <linux/ide.h>
50 #define PDC202XX_DEBUG_DRIVE_INFO 0
52 static const char *pdc_quirk_drives[] = {
53 "QUANTUM FIREBALLlct08 08",
54 "QUANTUM FIREBALLP KA6.4",
55 "QUANTUM FIREBALLP KA9.1",
56 "QUANTUM FIREBALLP LM20.4",
57 "QUANTUM FIREBALLP KX13.6",
58 "QUANTUM FIREBALLP KX20.5",
59 "QUANTUM FIREBALLP KX27.3",
60 "QUANTUM FIREBALLP LM20.5",
64 static void pdc_old_disable_66MHz_clock(ide_hwif_t *);
66 static int pdc202xx_tune_chipset (ide_drive_t *drive, u8 xferspeed)
68 ide_hwif_t *hwif = HWIF(drive);
69 struct pci_dev *dev = hwif->pci_dev;
70 u8 drive_pci = 0x60 + (drive->dn << 2);
71 u8 speed = ide_rate_filter(drive, xferspeed);
73 u8 AP = 0, BP = 0, CP = 0;
74 u8 TA = 0, TB = 0, TC = 0;
76 #if PDC202XX_DEBUG_DRIVE_INFO
78 pci_read_config_dword(dev, drive_pci, &drive_conf);
82 * TODO: do this once per channel
84 if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
85 pdc_old_disable_66MHz_clock(hwif);
87 pci_read_config_byte(dev, drive_pci, &AP);
88 pci_read_config_byte(dev, drive_pci + 1, &BP);
89 pci_read_config_byte(dev, drive_pci + 2, &CP);
93 case XFER_UDMA_4: TB = 0x20; TC = 0x01; break;
94 case XFER_UDMA_2: TB = 0x20; TC = 0x01; break;
96 case XFER_UDMA_1: TB = 0x40; TC = 0x02; break;
98 case XFER_MW_DMA_2: TB = 0x60; TC = 0x03; break;
99 case XFER_MW_DMA_1: TB = 0x60; TC = 0x04; break;
100 case XFER_MW_DMA_0: TB = 0xE0; TC = 0x0F; break;
101 case XFER_SW_DMA_2: TB = 0x60; TC = 0x05; break;
102 case XFER_SW_DMA_1: TB = 0x80; TC = 0x06; break;
103 case XFER_SW_DMA_0: TB = 0xC0; TC = 0x0B; break;
104 case XFER_PIO_4: TA = 0x01; TB = 0x04; break;
105 case XFER_PIO_3: TA = 0x02; TB = 0x06; break;
106 case XFER_PIO_2: TA = 0x03; TB = 0x08; break;
107 case XFER_PIO_1: TA = 0x05; TB = 0x0C; break;
109 default: TA = 0x09; TB = 0x13; break;
112 if (speed < XFER_SW_DMA_0) {
114 * preserve SYNC_INT / ERDDY_EN bits while clearing
115 * Prefetch_EN / IORDY_EN / PA[3:0] bits of register A
118 if (drive->id->capability & 4)
119 AP |= 0x20; /* set IORDY_EN bit */
120 if (drive->media == ide_disk)
121 AP |= 0x10; /* set Prefetch_EN bit */
122 /* clear PB[4:0] bits of register B */
124 pci_write_config_byte(dev, drive_pci, AP | TA);
125 pci_write_config_byte(dev, drive_pci + 1, BP | TB);
127 /* clear MB[2:0] bits of register B */
129 /* clear MC[3:0] bits of register C */
131 pci_write_config_byte(dev, drive_pci + 1, BP | TB);
132 pci_write_config_byte(dev, drive_pci + 2, CP | TC);
135 #if PDC202XX_DEBUG_DRIVE_INFO
136 printk(KERN_DEBUG "%s: %s drive%d 0x%08x ",
137 drive->name, ide_xfer_verbose(speed),
138 drive->dn, drive_conf);
139 pci_read_config_dword(dev, drive_pci, &drive_conf);
140 printk("0x%08x\n", drive_conf);
143 return ide_config_drive_speed(drive, speed);
146 static void pdc202xx_tune_drive(ide_drive_t *drive, u8 pio)
148 pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
149 pdc202xx_tune_chipset(drive, XFER_PIO_0 + pio);
152 static u8 pdc202xx_old_cable_detect (ide_hwif_t *hwif)
154 u16 CIS = 0, mask = (hwif->channel) ? (1<<11) : (1<<10);
155 pci_read_config_word(hwif->pci_dev, 0x50, &CIS);
156 return (CIS & mask) ? 1 : 0;
160 * Set the control register to use the 66MHz system
161 * clock for UDMA 3/4/5 mode operation when necessary.
163 * FIXME: this register is shared by both channels, some locking is needed
165 * It may also be possible to leave the 66MHz clock on
166 * and readjust the timing parameters.
168 static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
170 unsigned long clock_reg = hwif->dma_master + 0x11;
171 u8 clock = inb(clock_reg);
173 outb(clock | (hwif->channel ? 0x08 : 0x02), clock_reg);
176 static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
178 unsigned long clock_reg = hwif->dma_master + 0x11;
179 u8 clock = inb(clock_reg);
181 outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
184 static int pdc202xx_config_drive_xfer_rate (ide_drive_t *drive)
186 drive->init_speed = 0;
188 if (ide_tune_dma(drive))
191 if (ide_use_fast_pio(drive))
192 pdc202xx_tune_drive(drive, 255);
197 static int pdc202xx_quirkproc (ide_drive_t *drive)
199 const char **list, *model = drive->id->model;
201 for (list = pdc_quirk_drives; *list != NULL; list++)
202 if (strstr(model, *list) != NULL)
207 static void pdc202xx_old_ide_dma_start(ide_drive_t *drive)
209 if (drive->current_speed > XFER_UDMA_2)
210 pdc_old_enable_66MHz_clock(drive->hwif);
211 if (drive->media != ide_disk || drive->addressing == 1) {
212 struct request *rq = HWGROUP(drive)->rq;
213 ide_hwif_t *hwif = HWIF(drive);
214 unsigned long high_16 = hwif->dma_master;
215 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
217 u8 clock = inb(high_16 + 0x11);
219 outb(clock | (hwif->channel ? 0x08 : 0x02), high_16 + 0x11);
220 word_count = (rq->nr_sectors << 8);
221 word_count = (rq_data_dir(rq) == READ) ?
222 word_count | 0x05000000 :
223 word_count | 0x06000000;
224 outl(word_count, atapi_reg);
226 ide_dma_start(drive);
229 static int pdc202xx_old_ide_dma_end(ide_drive_t *drive)
231 if (drive->media != ide_disk || drive->addressing == 1) {
232 ide_hwif_t *hwif = HWIF(drive);
233 unsigned long high_16 = hwif->dma_master;
234 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
237 outl(0, atapi_reg); /* zero out extra */
238 clock = inb(high_16 + 0x11);
239 outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11);
241 if (drive->current_speed > XFER_UDMA_2)
242 pdc_old_disable_66MHz_clock(drive->hwif);
243 return __ide_dma_end(drive);
246 static int pdc202xx_old_ide_dma_test_irq(ide_drive_t *drive)
248 ide_hwif_t *hwif = HWIF(drive);
249 unsigned long high_16 = hwif->dma_master;
250 u8 dma_stat = inb(hwif->dma_status);
251 u8 sc1d = inb(high_16 + 0x001d);
254 /* bit7: Error, bit6: Interrupting, bit5: FIFO Full, bit4: FIFO Empty */
255 if ((sc1d & 0x50) == 0x50)
257 else if ((sc1d & 0x40) == 0x40)
258 return (dma_stat & 4) == 4;
260 /* bit3: Error, bit2: Interrupting, bit1: FIFO Full, bit0: FIFO Empty */
261 if ((sc1d & 0x05) == 0x05)
263 else if ((sc1d & 0x04) == 0x04)
264 return (dma_stat & 4) == 4;
267 return (dma_stat & 4) == 4; /* return 1 if INTR asserted */
270 static void pdc202xx_dma_lost_irq(ide_drive_t *drive)
272 ide_hwif_t *hwif = HWIF(drive);
274 if (hwif->resetproc != NULL)
275 hwif->resetproc(drive);
277 ide_dma_lost_irq(drive);
280 static int pdc202xx_ide_dma_timeout(ide_drive_t *drive)
282 if (HWIF(drive)->resetproc != NULL)
283 HWIF(drive)->resetproc(drive);
284 return __ide_dma_timeout(drive);
287 static void pdc202xx_reset_host (ide_hwif_t *hwif)
289 unsigned long high_16 = hwif->dma_master;
290 u8 udma_speed_flag = inb(high_16 | 0x001f);
292 outb(udma_speed_flag | 0x10, high_16 | 0x001f);
294 outb(udma_speed_flag & ~0x10, high_16 | 0x001f);
295 mdelay(2000); /* 2 seconds ?! */
297 printk(KERN_WARNING "PDC202XX: %s channel reset.\n",
298 hwif->channel ? "Secondary" : "Primary");
301 static void pdc202xx_reset (ide_drive_t *drive)
303 ide_hwif_t *hwif = HWIF(drive);
304 ide_hwif_t *mate = hwif->mate;
306 pdc202xx_reset_host(hwif);
307 pdc202xx_reset_host(mate);
308 pdc202xx_tune_drive(drive, 255);
311 static unsigned int __devinit init_chipset_pdc202xx(struct pci_dev *dev,
314 /* This doesn't appear needed */
315 if (dev->resource[PCI_ROM_RESOURCE].start) {
316 pci_write_config_dword(dev, PCI_ROM_ADDRESS,
317 dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
318 printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n", name,
319 (unsigned long)dev->resource[PCI_ROM_RESOURCE].start);
325 static void __devinit init_hwif_pdc202xx(ide_hwif_t *hwif)
327 struct pci_dev *dev = hwif->pci_dev;
329 /* PDC20265 has problems with large LBA48 requests */
330 if ((dev->device == PCI_DEVICE_ID_PROMISE_20267) ||
331 (dev->device == PCI_DEVICE_ID_PROMISE_20265))
335 hwif->tuneproc = &pdc202xx_tune_drive;
336 hwif->quirkproc = &pdc202xx_quirkproc;
338 if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246)
339 hwif->resetproc = &pdc202xx_reset;
341 hwif->speedproc = &pdc202xx_tune_chipset;
343 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
345 hwif->ultra_mask = hwif->cds->udma_mask;
346 hwif->mwdma_mask = 0x07;
347 hwif->swdma_mask = 0x07;
350 hwif->err_stops_fifo = 1;
352 hwif->ide_dma_check = &pdc202xx_config_drive_xfer_rate;
353 hwif->dma_lost_irq = &pdc202xx_dma_lost_irq;
354 hwif->ide_dma_timeout = &pdc202xx_ide_dma_timeout;
356 if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246) {
357 if (!(hwif->udma_four))
358 hwif->udma_four = (pdc202xx_old_cable_detect(hwif)) ? 0 : 1;
359 hwif->dma_start = &pdc202xx_old_ide_dma_start;
360 hwif->ide_dma_end = &pdc202xx_old_ide_dma_end;
362 hwif->ide_dma_test_irq = &pdc202xx_old_ide_dma_test_irq;
366 hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
369 static void __devinit init_dma_pdc202xx(ide_hwif_t *hwif, unsigned long dmabase)
371 u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;
374 ide_setup_dma(hwif, dmabase, 8);
378 udma_speed_flag = inb(dmabase | 0x1f);
379 primary_mode = inb(dmabase | 0x1a);
380 secondary_mode = inb(dmabase | 0x1b);
381 printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
383 "Secondary %s Mode.\n", hwif->cds->name,
384 (udma_speed_flag & 1) ? "EN" : "DIS",
385 (primary_mode & 1) ? "MASTER" : "PCI",
386 (secondary_mode & 1) ? "MASTER" : "PCI" );
388 #ifdef CONFIG_PDC202XX_BURST
389 if (!(udma_speed_flag & 1)) {
390 printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
391 hwif->cds->name, udma_speed_flag,
392 (udma_speed_flag|1));
393 outb(udma_speed_flag | 1, dmabase | 0x1f);
394 printk("%sACTIVE\n", (inb(dmabase | 0x1f) & 1) ? "" : "IN");
396 #endif /* CONFIG_PDC202XX_BURST */
398 ide_setup_dma(hwif, dmabase, 8);
401 static int __devinit init_setup_pdc202ata4(struct pci_dev *dev,
404 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
405 u8 irq = 0, irq2 = 0;
406 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
408 pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2);
410 pci_write_config_byte(dev,
411 (PCI_INTERRUPT_LINE)|0x80, irq); /* 0xbc */
412 printk(KERN_INFO "%s: pci-config space interrupt "
413 "mirror fixed.\n", d->name);
416 return ide_setup_pci_device(dev, d);
419 static int __devinit init_setup_pdc20265(struct pci_dev *dev,
422 if ((dev->bus->self) &&
423 (dev->bus->self->vendor == PCI_VENDOR_ID_INTEL) &&
424 ((dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960) ||
425 (dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960RM))) {
426 printk(KERN_INFO "ide: Skipping Promise PDC20265 "
427 "attached to I2O RAID controller.\n");
430 return ide_setup_pci_device(dev, d);
433 static int __devinit init_setup_pdc202xx(struct pci_dev *dev,
436 return ide_setup_pci_device(dev, d);
439 static ide_pci_device_t pdc202xx_chipsets[] __devinitdata = {
442 .init_setup = init_setup_pdc202ata4,
443 .init_chipset = init_chipset_pdc202xx,
444 .init_hwif = init_hwif_pdc202xx,
445 .init_dma = init_dma_pdc202xx,
448 .bootable = OFF_BOARD,
450 .udma_mask = 0x07, /* udma0-2 */
453 .init_setup = init_setup_pdc202ata4,
454 .init_chipset = init_chipset_pdc202xx,
455 .init_hwif = init_hwif_pdc202xx,
456 .init_dma = init_dma_pdc202xx,
459 .bootable = OFF_BOARD,
461 .udma_mask = 0x1f, /* udma0-4 */
464 .init_setup = init_setup_pdc202ata4,
465 .init_chipset = init_chipset_pdc202xx,
466 .init_hwif = init_hwif_pdc202xx,
467 .init_dma = init_dma_pdc202xx,
470 .bootable = OFF_BOARD,
472 .udma_mask = 0x1f, /* udma0-4 */
475 .init_setup = init_setup_pdc20265,
476 .init_chipset = init_chipset_pdc202xx,
477 .init_hwif = init_hwif_pdc202xx,
478 .init_dma = init_dma_pdc202xx,
481 .bootable = OFF_BOARD,
483 .udma_mask = 0x3f, /* udma0-5 */
486 .init_setup = init_setup_pdc202xx,
487 .init_chipset = init_chipset_pdc202xx,
488 .init_hwif = init_hwif_pdc202xx,
489 .init_dma = init_dma_pdc202xx,
492 .bootable = OFF_BOARD,
494 .udma_mask = 0x3f, /* udma0-5 */
499 * pdc202xx_init_one - called when a PDC202xx is found
500 * @dev: the pdc202xx device
501 * @id: the matching pci id
503 * Called when the PCI registration layer (or the IDE initialization)
504 * finds a device matching our IDE device tables.
507 static int __devinit pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
509 ide_pci_device_t *d = &pdc202xx_chipsets[id->driver_data];
511 return d->init_setup(dev, d);
514 static struct pci_device_id pdc202xx_pci_tbl[] = {
515 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20246, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
516 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20262, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
517 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
518 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20265, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
519 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20267, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
522 MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);
524 static struct pci_driver driver = {
525 .name = "Promise_Old_IDE",
526 .id_table = pdc202xx_pci_tbl,
527 .probe = pdc202xx_init_one,
530 static int __init pdc202xx_ide_init(void)
532 return ide_pci_register_driver(&driver);
535 module_init(pdc202xx_ide_init);
537 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
538 MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
539 MODULE_LICENSE("GPL");