2 * linux/drivers/ide/pci/slc90e66.c Version 0.14 February 8, 2007
4 * Copyright (C) 2000-2002 Andre Hedrick <andre@linux-ide.org>
5 * Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
7 * This is a look-alike variation of the ICH0 PIIX4 Ultra-66,
8 * but this keeps the ISA-Bridge and slots alive.
12 #include <linux/types.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/ioport.h>
16 #include <linux/pci.h>
17 #include <linux/hdreg.h>
18 #include <linux/ide.h>
19 #include <linux/delay.h>
20 #include <linux/init.h>
24 static u8 slc90e66_dma_2_pio (u8 xfer_rate) {
51 static void slc90e66_tune_pio (ide_drive_t *drive, u8 pio)
53 ide_hwif_t *hwif = HWIF(drive);
54 struct pci_dev *dev = hwif->pci_dev;
55 int is_slave = drive->dn & 1;
56 int master_port = hwif->channel ? 0x42 : 0x40;
57 int slave_port = 0x44;
63 static const u8 timings[][2]= {
70 spin_lock_irqsave(&ide_lock, flags);
71 pci_read_config_word(dev, master_port, &master_data);
74 control |= 1; /* Programmable timing on */
75 if (drive->media == ide_disk)
76 control |= 4; /* Prefetch, post write */
78 control |= 2; /* IORDY */
80 master_data |= 0x4000;
81 master_data &= ~0x0070;
83 /* Set PPE, IE and TIME */
84 master_data |= control << 4;
86 pci_read_config_byte(dev, slave_port, &slave_data);
87 slave_data &= hwif->channel ? 0x0f : 0xf0;
88 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) <<
89 (hwif->channel ? 4 : 0);
91 master_data &= ~0x3307;
93 /* enable PPE, IE and TIME */
94 master_data |= control;
96 master_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
98 pci_write_config_word(dev, master_port, master_data);
100 pci_write_config_byte(dev, slave_port, slave_data);
101 spin_unlock_irqrestore(&ide_lock, flags);
104 static void slc90e66_tune_drive (ide_drive_t *drive, u8 pio)
106 pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
107 slc90e66_tune_pio(drive, pio);
108 (void) ide_config_drive_speed(drive, XFER_PIO_0 + pio);
111 static int slc90e66_tune_chipset (ide_drive_t *drive, u8 xferspeed)
113 ide_hwif_t *hwif = HWIF(drive);
114 struct pci_dev *dev = hwif->pci_dev;
115 u8 maslave = hwif->channel ? 0x42 : 0x40;
116 u8 speed = ide_rate_filter(drive, xferspeed);
117 int sitre = 0, a_speed = 7 << (drive->dn * 4);
118 int u_speed = 0, u_flag = 1 << drive->dn;
119 u16 reg4042, reg44, reg48, reg4a;
121 pci_read_config_word(dev, maslave, ®4042);
122 sitre = (reg4042 & 0x4000) ? 1 : 0;
123 pci_read_config_word(dev, 0x44, ®44);
124 pci_read_config_word(dev, 0x48, ®48);
125 pci_read_config_word(dev, 0x4a, ®4a);
128 case XFER_UDMA_4: u_speed = 4 << (drive->dn * 4); break;
129 case XFER_UDMA_3: u_speed = 3 << (drive->dn * 4); break;
130 case XFER_UDMA_2: u_speed = 2 << (drive->dn * 4); break;
131 case XFER_UDMA_1: u_speed = 1 << (drive->dn * 4); break;
132 case XFER_UDMA_0: u_speed = 0 << (drive->dn * 4); break;
135 case XFER_SW_DMA_2: break;
139 case XFER_PIO_0: break;
143 if (speed >= XFER_UDMA_0) {
144 if (!(reg48 & u_flag))
145 pci_write_config_word(dev, 0x48, reg48|u_flag);
146 /* FIXME: (reg4a & a_speed) ? */
147 if ((reg4a & u_speed) != u_speed) {
148 pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
149 pci_read_config_word(dev, 0x4a, ®4a);
150 pci_write_config_word(dev, 0x4a, reg4a|u_speed);
154 pci_write_config_word(dev, 0x48, reg48 & ~u_flag);
156 pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
159 slc90e66_tune_pio(drive, slc90e66_dma_2_pio(speed));
160 return ide_config_drive_speed(drive, speed);
163 static int slc90e66_config_drive_for_dma (ide_drive_t *drive)
165 u8 speed = ide_max_dma_mode(drive);
170 (void) slc90e66_tune_chipset(drive, speed);
171 return ide_dma_enable(drive);
174 static int slc90e66_config_drive_xfer_rate (ide_drive_t *drive)
176 drive->init_speed = 0;
178 if (ide_use_dma(drive) && slc90e66_config_drive_for_dma(drive))
181 if (ide_use_fast_pio(drive))
182 slc90e66_tune_drive(drive, 255);
187 static void __devinit init_hwif_slc90e66 (ide_hwif_t *hwif)
190 u8 mask = hwif->channel ? 0x01 : 0x02; /* bit0:Primary */
195 hwif->irq = hwif->channel ? 15 : 14;
197 hwif->speedproc = &slc90e66_tune_chipset;
198 hwif->tuneproc = &slc90e66_tune_drive;
200 pci_read_config_byte(hwif->pci_dev, 0x47, ®47);
202 if (!hwif->dma_base) {
203 hwif->drives[0].autotune = 1;
204 hwif->drives[1].autotune = 1;
209 hwif->ultra_mask = 0x1f;
210 hwif->mwdma_mask = 0x06;
211 hwif->swdma_mask = 0x04;
213 if (!hwif->udma_four) {
214 /* bit[0(1)]: 0:80, 1:40 */
215 hwif->udma_four = (reg47 & mask) ? 0 : 1;
218 hwif->ide_dma_check = &slc90e66_config_drive_xfer_rate;
222 hwif->drives[0].autodma = hwif->autodma;
223 hwif->drives[1].autodma = hwif->autodma;
226 static ide_pci_device_t slc90e66_chipset __devinitdata = {
228 .init_hwif = init_hwif_slc90e66,
231 .enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}},
232 .bootable = ON_BOARD,
235 static int __devinit slc90e66_init_one(struct pci_dev *dev, const struct pci_device_id *id)
237 return ide_setup_pci_device(dev, &slc90e66_chipset);
240 static struct pci_device_id slc90e66_pci_tbl[] = {
241 { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1), 0},
244 MODULE_DEVICE_TABLE(pci, slc90e66_pci_tbl);
246 static struct pci_driver driver = {
247 .name = "SLC90e66_IDE",
248 .id_table = slc90e66_pci_tbl,
249 .probe = slc90e66_init_one,
252 static int __init slc90e66_ide_init(void)
254 return ide_pci_register_driver(&driver);
257 module_init(slc90e66_ide_init);
259 MODULE_AUTHOR("Andre Hedrick");
260 MODULE_DESCRIPTION("PCI driver module for SLC90E66 IDE");
261 MODULE_LICENSE("GPL");