drivers/ide/ppc/scc_pata.c

   1 /*
   2  * Support for IDE interfaces on Celleb platform
   3  *
   4  * (C) Copyright 2006 TOSHIBA CORPORATION
   5  *
   6  * This code is based on drivers/ide/pci/siimage.c:
   7  * Copyright (C) 2001-2002      Andre Hedrick <andre@linux-ide.org>
   8  * Copyright (C) 2003           Red Hat <alan@redhat.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License along
  21  * with this program; if not, write to the Free Software Foundation, Inc.,
  22  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  23  */
  24
  25 #include <linux/types.h>
  26 #include <linux/module.h>
  27 #include <linux/pci.h>
  28 #include <linux/delay.h>
  29 #include <linux/hdreg.h>
  30 #include <linux/ide.h>
  31 #include <linux/init.h>
  32
  33 #define PCI_DEVICE_ID_TOSHIBA_SCC_ATA            0x01b4
  34
  35 #define SCC_PATA_NAME           "scc IDE"
  36
  37 #define TDVHSEL_MASTER          0x00000001
  38 #define TDVHSEL_SLAVE           0x00000004
  39
  40 #define MODE_JCUSFEN            0x00000080
  41
  42 #define CCKCTRL_ATARESET        0x00040000
  43 #define CCKCTRL_BUFCNT          0x00020000
  44 #define CCKCTRL_CRST            0x00010000
  45 #define CCKCTRL_OCLKEN          0x00000100
  46 #define CCKCTRL_ATACLKOEN       0x00000002
  47 #define CCKCTRL_LCLKEN          0x00000001
  48
  49 #define QCHCD_IOS_SS            0x00000001
  50
  51 #define QCHSD_STPDIAG           0x00020000
  52
  53 #define INTMASK_MSK             0xD1000012
  54 #define INTSTS_SERROR           0x80000000
  55 #define INTSTS_PRERR            0x40000000
  56 #define INTSTS_RERR             0x10000000
  57 #define INTSTS_ICERR            0x01000000
  58 #define INTSTS_BMSINT           0x00000010
  59 #define INTSTS_BMHE             0x00000008
  60 #define INTSTS_IOIRQS           0x00000004
  61 #define INTSTS_INTRQ            0x00000002
  62 #define INTSTS_ACTEINT          0x00000001
  63
  64 #define ECMODE_VALUE 0x01
  65
  66 static struct scc_ports {
  67         unsigned long ctl, dma;
  68         unsigned char hwif_id;  /* for removing hwif from system */
  69 } scc_ports[MAX_HWIFS];
  70
  71 /* PIO transfer mode  table */
  72 /* JCHST */
  73 static unsigned long JCHSTtbl[2][7] = {
  74         {0x0E, 0x05, 0x02, 0x03, 0x02, 0x00, 0x00},   /* 100MHz */
  75         {0x13, 0x07, 0x04, 0x04, 0x03, 0x00, 0x00}    /* 133MHz */
  76 };
  77
  78 /* JCHHT */
  79 static unsigned long JCHHTtbl[2][7] = {
  80         {0x0E, 0x02, 0x02, 0x02, 0x02, 0x00, 0x00},   /* 100MHz */
  81         {0x13, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00}    /* 133MHz */
  82 };
  83
  84 /* JCHCT */
  85 static unsigned long JCHCTtbl[2][7] = {
  86         {0x1D, 0x1D, 0x1C, 0x0B, 0x06, 0x00, 0x00},   /* 100MHz */
  87         {0x27, 0x26, 0x26, 0x0E, 0x09, 0x00, 0x00}    /* 133MHz */
  88 };
  89
  90
  91 /* DMA transfer mode  table */
  92 /* JCHDCTM/JCHDCTS */
  93 static unsigned long JCHDCTxtbl[2][7] = {
  94         {0x0A, 0x06, 0x04, 0x03, 0x01, 0x00, 0x00},   /* 100MHz */
  95         {0x0E, 0x09, 0x06, 0x04, 0x02, 0x01, 0x00}    /* 133MHz */
  96 };
  97
  98 /* JCSTWTM/JCSTWTS  */
  99 static unsigned long JCSTWTxtbl[2][7] = {
 100         {0x06, 0x04, 0x03, 0x02, 0x02, 0x02, 0x00},   /* 100MHz */
 101         {0x09, 0x06, 0x04, 0x02, 0x02, 0x02, 0x02}    /* 133MHz */
 102 };
 103
 104 /* JCTSS */
 105 static unsigned long JCTSStbl[2][7] = {
 106         {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x00},   /* 100MHz */
 107         {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05}    /* 133MHz */
 108 };
 109
 110 /* JCENVT */
 111 static unsigned long JCENVTtbl[2][7] = {
 112         {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00},   /* 100MHz */
 113         {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02}    /* 133MHz */
 114 };
 115
 116 /* JCACTSELS/JCACTSELM */
 117 static unsigned long JCACTSELtbl[2][7] = {
 118         {0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00},   /* 100MHz */
 119         {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01}    /* 133MHz */
 120 };
 121
 122
 123 static u8 scc_ide_inb(unsigned long port)
 124 {
 125         u32 data = in_be32((void*)port);
 126         return (u8)data;
 127 }
 128
 129 static u16 scc_ide_inw(unsigned long port)
 130 {
 131         u32 data = in_be32((void*)port);
 132         return (u16)data;
 133 }
 134
 135 static u32 scc_ide_inl(unsigned long port)
 136 {
 137         u32 data = in_be32((void*)port);
 138         return data;
 139 }
 140
 141 static void scc_ide_insw(unsigned long port, void *addr, u32 count)
 142 {
 143         u16 *ptr = (u16 *)addr;
 144         while (count--) {
 145                 *ptr++ = le16_to_cpu(in_be32((void*)port));
 146         }
 147 }
 148
 149 static void scc_ide_insl(unsigned long port, void *addr, u32 count)
 150 {
 151         u16 *ptr = (u16 *)addr;
 152         while (count--) {
 153                 *ptr++ = le16_to_cpu(in_be32((void*)port));
 154                 *ptr++ = le16_to_cpu(in_be32((void*)port));
 155         }
 156 }
 157
 158 static void scc_ide_outb(u8 addr, unsigned long port)
 159 {
 160         out_be32((void*)port, addr);
 161 }
 162
 163 static void scc_ide_outw(u16 addr, unsigned long port)
 164 {
 165         out_be32((void*)port, addr);
 166 }
 167
 168 static void scc_ide_outl(u32 addr, unsigned long port)
 169 {
 170         out_be32((void*)port, addr);
 171 }
 172
 173 static void
 174 scc_ide_outbsync(ide_drive_t * drive, u8 addr, unsigned long port)
 175 {
 176         ide_hwif_t *hwif = HWIF(drive);
 177
 178         out_be32((void*)port, addr);
 179         __asm__ __volatile__("eieio":::"memory");
 180         in_be32((void*)(hwif->dma_base + 0x01c));
 181         __asm__ __volatile__("eieio":::"memory");
 182 }
 183
 184 static void
 185 scc_ide_outsw(unsigned long port, void *addr, u32 count)
 186 {
 187         u16 *ptr = (u16 *)addr;
 188         while (count--) {
 189                 out_be32((void*)port, cpu_to_le16(*ptr++));
 190         }
 191 }
 192
 193 static void
 194 scc_ide_outsl(unsigned long port, void *addr, u32 count)
 195 {
 196         u16 *ptr = (u16 *)addr;
 197         while (count--) {
 198                 out_be32((void*)port, cpu_to_le16(*ptr++));
 199                 out_be32((void*)port, cpu_to_le16(*ptr++));
 200         }
 201 }
 202
 203 /**
 204  *      scc_ratemask    -       Compute available modes
 205  *      @drive: IDE drive
 206  *
 207  *      Compute the available speeds for the devices on the interface.
 208  *      Enforce UDMA33 as a limit if there is no 80pin cable present.
 209  */
 210
 211 static u8 scc_ratemask(ide_drive_t *drive)
 212 {
 213         u8 mode = 4;
 214
 215         if (!eighty_ninty_three(drive))
 216                 mode = min(mode, (u8)1);
 217         return mode;
 218 }
 219
 220 /**
 221  *      scc_tuneproc    -       tune a drive PIO mode
 222  *      @drive: drive to tune
 223  *      @mode_wanted: the target operating mode
 224  *
 225  *      Load the timing settings for this device mode into the
 226  *      controller.
 227  */
 228
 229 static void scc_tuneproc(ide_drive_t *drive, byte mode_wanted)
 230 {
 231         ide_hwif_t *hwif = HWIF(drive);
 232         struct scc_ports *ports = ide_get_hwifdata(hwif);
 233         unsigned long ctl_base = ports->ctl;
 234         unsigned long cckctrl_port = ctl_base + 0xff0;
 235         unsigned long piosht_port = ctl_base + 0x000;
 236         unsigned long pioct_port = ctl_base + 0x004;
 237         unsigned long reg;
 238         unsigned char speed = XFER_PIO_0;
 239         int offset;
 240
 241         mode_wanted = ide_get_best_pio_mode(drive, mode_wanted, 4, NULL);
 242         switch (mode_wanted) {
 243         case 4:
 244                 speed = XFER_PIO_4;
 245                 break;
 246         case 3:
 247                 speed = XFER_PIO_3;
 248                 break;
 249         case 2:
 250                 speed = XFER_PIO_2;
 251                 break;
 252         case 1:
 253                 speed = XFER_PIO_1;
 254                 break;
 255         case 0:
 256         default:
 257                 speed = XFER_PIO_0;
 258                 break;
 259         }
 260
 261         reg = hwif->INL(cckctrl_port);
 262         if (reg & CCKCTRL_ATACLKOEN) {
 263                 offset = 1; /* 133MHz */
 264         } else {
 265                 offset = 0; /* 100MHz */
 266         }
 267         reg = JCHSTtbl[offset][mode_wanted] << 16 | JCHHTtbl[offset][mode_wanted];
 268         hwif->OUTL(reg, piosht_port);
 269         reg = JCHCTtbl[offset][mode_wanted];
 270         hwif->OUTL(reg, pioct_port);
 271
 272         ide_config_drive_speed(drive, speed);
 273 }
 274
 275 /**
 276  *      scc_tune_chipset        -       tune a drive DMA mode
 277  *      @drive: Drive to set up
 278  *      @xferspeed: speed we want to achieve
 279  *
 280  *      Load the timing settings for this device mode into the
 281  *      controller.
 282  */
 283
 284 static int scc_tune_chipset(ide_drive_t *drive, byte xferspeed)
 285 {
 286         ide_hwif_t *hwif = HWIF(drive);
 287         u8 speed = ide_rate_filter(scc_ratemask(drive), xferspeed);
 288         struct scc_ports *ports = ide_get_hwifdata(hwif);
 289         unsigned long ctl_base = ports->ctl;
 290         unsigned long cckctrl_port = ctl_base + 0xff0;
 291         unsigned long mdmact_port = ctl_base + 0x008;
 292         unsigned long mcrcst_port = ctl_base + 0x00c;
 293         unsigned long sdmact_port = ctl_base + 0x010;
 294         unsigned long scrcst_port = ctl_base + 0x014;
 295         unsigned long udenvt_port = ctl_base + 0x018;
 296         unsigned long tdvhsel_port   = ctl_base + 0x020;
 297         int is_slave = (&hwif->drives[1] == drive);
 298         int offset, idx;
 299         unsigned long reg;
 300         unsigned long jcactsel;
 301
 302         reg = hwif->INL(cckctrl_port);
 303         if (reg & CCKCTRL_ATACLKOEN) {
 304                 offset = 1; /* 133MHz */
 305         } else {
 306                 offset = 0; /* 100MHz */
 307         }
 308
 309         switch (speed) {
 310         case XFER_UDMA_6:
 311                 idx = 6;
 312                 break;
 313         case XFER_UDMA_5:
 314                 idx = 5;
 315                 break;
 316         case XFER_UDMA_4:
 317                 idx = 4;
 318                 break;
 319         case XFER_UDMA_3:
 320                 idx = 3;
 321                 break;
 322         case XFER_UDMA_2:
 323                 idx = 2;
 324                 break;
 325         case XFER_UDMA_1:
 326                 idx = 1;
 327                 break;
 328         case XFER_UDMA_0:
 329                 idx = 0;
 330                 break;
 331         default:
 332                 return 1;
 333         }
 334
 335         jcactsel = JCACTSELtbl[offset][idx];
 336         if (is_slave) {
 337                 hwif->OUTL(JCHDCTxtbl[offset][idx], sdmact_port);
 338                 hwif->OUTL(JCSTWTxtbl[offset][idx], scrcst_port);
 339                 jcactsel = jcactsel << 2 ;
 340                 hwif->OUTL( (hwif->INL( tdvhsel_port ) & ~TDVHSEL_SLAVE) | jcactsel, tdvhsel_port );
 341         } else {
 342                 hwif->OUTL(JCHDCTxtbl[offset][idx], mdmact_port);
 343                 hwif->OUTL(JCSTWTxtbl[offset][idx], mcrcst_port);
 344                 hwif->OUTL( (hwif->INL( tdvhsel_port ) & ~TDVHSEL_MASTER) | jcactsel, tdvhsel_port );
 345         }
 346         reg = JCTSStbl[offset][idx] << 16 | JCENVTtbl[offset][idx];
 347         hwif->OUTL(reg, udenvt_port);
 348
 349         return ide_config_drive_speed(drive, speed);
 350 }
 351
 352 /**
 353  *      scc_config_chipset_for_dma      -       configure for DMA
 354  *      @drive: drive to configure
 355  *
 356  *      Called by scc_config_drive_for_dma().
 357  */
 358
 359 static int scc_config_chipset_for_dma(ide_drive_t *drive)
 360 {
 361         u8 speed = ide_dma_speed(drive, scc_ratemask(drive));
 362
 363         if (!speed)
 364                 return 0;
 365
 366         if (scc_tune_chipset(drive, speed))
 367                 return 0;
 368
 369         return ide_dma_enable(drive);
 370 }
 371
 372 /**
 373  *      scc_configure_drive_for_dma     -       set up for DMA transfers
 374  *      @drive: drive we are going to set up
 375  *
 376  *      Set up the drive for DMA, tune the controller and drive as
 377  *      required.
 378  *      If the drive isn't suitable for DMA or we hit other problems
 379  *      then we will drop down to PIO and set up PIO appropriately.
 380  *      (return 1)
 381  */
 382
 383 static int scc_config_drive_for_dma(ide_drive_t *drive)
 384 {
 385         ide_hwif_t *hwif = HWIF(drive);
 386
 387         if (ide_use_dma(drive) && scc_config_chipset_for_dma(drive))
 388                 return hwif->ide_dma_on(drive);
 389
 390         if (ide_use_fast_pio(drive)) {
 391                 hwif->tuneproc(drive, 4);
 392                 hwif->ide_dma_off_quietly(drive);
 393         }
 394         return 1; /* DMA is not supported */
 395 }
 396
 397 /**
 398  *      scc_ide_dma_end -       Stop DMA
 399  *      @drive: IDE drive
 400  *
 401  *      Check and clear INT Status register.
 402  *      Then call __ide_dma_end().
 403  */
 404
 405 static int scc_ide_dma_end(ide_drive_t * drive)
 406 {
 407         ide_hwif_t *hwif = HWIF(drive);
 408         unsigned long intsts_port = hwif->dma_base + 0x014;
 409         u32 reg;
 410
 411         while (1) {
 412                 reg = hwif->INL(intsts_port);
 413
 414                 if (reg & INTSTS_SERROR) {
 415                         printk(KERN_WARNING "%s: SERROR\n", SCC_PATA_NAME);
 416                         hwif->OUTL(INTSTS_SERROR|INTSTS_BMSINT, intsts_port);
 417
 418                         hwif->OUTB(hwif->INB(hwif->dma_command) & ~QCHCD_IOS_SS,
 419                                    hwif->dma_command);
 420                         continue;
 421                 }
 422
 423                 if (reg & INTSTS_PRERR) {
 424                         u32 maea0, maec0;
 425                         unsigned long ctl_base = hwif->config_data;
 426
 427                         maea0 = hwif->INL(ctl_base + 0xF50);
 428                         maec0 = hwif->INL(ctl_base + 0xF54);
 429
 430                         printk(KERN_WARNING "%s: PRERR [addr:%x cmd:%x]\n", SCC_PATA_NAME, maea0, maec0);
 431
 432                         hwif->OUTL(INTSTS_PRERR|INTSTS_BMSINT, intsts_port);
 433
 434                         hwif->OUTB(hwif->INB(hwif->dma_command) & ~QCHCD_IOS_SS,
 435                                    hwif->dma_command);
 436                         continue;
 437                 }
 438
 439                 if (reg & INTSTS_RERR) {
 440                         printk(KERN_WARNING "%s: Response Error\n", SCC_PATA_NAME);
 441                         hwif->OUTL(INTSTS_RERR|INTSTS_BMSINT, intsts_port);
 442
 443                         hwif->OUTB(hwif->INB(hwif->dma_command) & ~QCHCD_IOS_SS,
 444                                    hwif->dma_command);
 445                         continue;
 446                 }
 447
 448                 if (reg & INTSTS_ICERR) {
 449                         hwif->OUTB(hwif->INB(hwif->dma_command) & ~QCHCD_IOS_SS,
 450                                    hwif->dma_command);
 451
 452                         printk(KERN_WARNING "%s: Illegal Configuration\n", SCC_PATA_NAME);
 453                         hwif->OUTL(INTSTS_ICERR|INTSTS_BMSINT, intsts_port);
 454                         continue;
 455                 }
 456
 457                 if (reg & INTSTS_BMSINT) {
 458                         printk(KERN_WARNING "%s: Internal Bus Error\n", SCC_PATA_NAME);
 459                         hwif->OUTL(INTSTS_BMSINT, intsts_port);
 460
 461                         ide_do_reset(drive);
 462                         continue;
 463                 }
 464
 465                 if (reg & INTSTS_BMHE) {
 466                         hwif->OUTL(INTSTS_BMHE, intsts_port);
 467                         continue;
 468                 }
 469
 470                 if (reg & INTSTS_ACTEINT) {
 471                         hwif->OUTL(INTSTS_ACTEINT, intsts_port);
 472                         continue;
 473                 }
 474
 475                 if (reg & INTSTS_IOIRQS) {
 476                         hwif->OUTL(INTSTS_IOIRQS, intsts_port);
 477                         continue;
 478                 }
 479                 break;
 480         }
 481
 482         return __ide_dma_end(drive);
 483 }
 484
 485 /**
 486  *      setup_mmio_scc  -       map CTRL/BMID region
 487  *      @dev: PCI device we are configuring
 488  *      @name: device name
 489  *
 490  */
 491
 492 static int setup_mmio_scc (struct pci_dev *dev, const char *name)
 493 {
 494         unsigned long ctl_base = pci_resource_start(dev, 0);
 495         unsigned long dma_base = pci_resource_start(dev, 1);
 496         unsigned long ctl_size = pci_resource_len(dev, 0);
 497         unsigned long dma_size = pci_resource_len(dev, 1);
 498         void *ctl_addr;
 499         void *dma_addr;
 500         int i;
 501
 502         for (i = 0; i < MAX_HWIFS; i++) {
 503                 if (scc_ports[i].ctl == 0)
 504                         break;
 505         }
 506         if (i >= MAX_HWIFS)
 507                 return -ENOMEM;
 508
 509         if (!request_mem_region(ctl_base, ctl_size, name)) {
 510                 printk(KERN_WARNING "%s: IDE controller MMIO ports not available.\n", SCC_PATA_NAME);
 511                 goto fail_0;
 512         }
 513
 514         if (!request_mem_region(dma_base, dma_size, name)) {
 515                 printk(KERN_WARNING "%s: IDE controller MMIO ports not available.\n", SCC_PATA_NAME);
 516                 goto fail_1;
 517         }
 518
 519         if ((ctl_addr = ioremap(ctl_base, ctl_size)) == NULL)
 520                 goto fail_2;
 521
 522         if ((dma_addr = ioremap(dma_base, dma_size)) == NULL)
 523                 goto fail_3;
 524
 525         pci_set_master(dev);
 526         scc_ports[i].ctl = (unsigned long)ctl_addr;
 527         scc_ports[i].dma = (unsigned long)dma_addr;
 528         pci_set_drvdata(dev, (void *) &scc_ports[i]);
 529
 530         return 1;
 531
 532  fail_3:
 533         iounmap(ctl_addr);
 534  fail_2:
 535         release_mem_region(dma_base, dma_size);
 536  fail_1:
 537         release_mem_region(ctl_base, ctl_size);
 538  fail_0:
 539         return -ENOMEM;
 540 }
 541
 542 /**
 543  *      init_setup_scc  -       set up an SCC PATA Controller
 544  *      @dev: PCI device
 545  *      @d: IDE PCI device
 546  *
 547  *      Perform the initial set up for this device.
 548  */
 549
 550 static int __devinit init_setup_scc(struct pci_dev *dev, ide_pci_device_t *d)
 551 {
 552         unsigned long ctl_base;
 553         unsigned long dma_base;
 554         unsigned long cckctrl_port;
 555         unsigned long intmask_port;
 556         unsigned long mode_port;
 557         unsigned long ecmode_port;
 558         unsigned long dma_status_port;
 559         u32 reg = 0;
 560         struct scc_ports *ports;
 561         int rc;
 562
 563         rc = setup_mmio_scc(dev, d->name);
 564         if (rc < 0) {
 565                 return rc;
 566         }
 567
 568         ports = pci_get_drvdata(dev);
 569         ctl_base = ports->ctl;
 570         dma_base = ports->dma;
 571         cckctrl_port = ctl_base + 0xff0;
 572         intmask_port = dma_base + 0x010;
 573         mode_port = ctl_base + 0x024;
 574         ecmode_port = ctl_base + 0xf00;
 575         dma_status_port = dma_base + 0x004;
 576
 577         /* controller initialization */
 578         reg = 0;
 579         out_be32((void*)cckctrl_port, reg);
 580         reg |= CCKCTRL_ATACLKOEN;
 581         out_be32((void*)cckctrl_port, reg);
 582         reg |= CCKCTRL_LCLKEN | CCKCTRL_OCLKEN;
 583         out_be32((void*)cckctrl_port, reg);
 584         reg |= CCKCTRL_CRST;
 585         out_be32((void*)cckctrl_port, reg);
 586
 587         for (;;) {
 588                 reg = in_be32((void*)cckctrl_port);
 589                 if (reg & CCKCTRL_CRST)
 590                         break;
 591                 udelay(5000);
 592         }
 593
 594         reg |= CCKCTRL_ATARESET;
 595         out_be32((void*)cckctrl_port, reg);
 596
 597         out_be32((void*)ecmode_port, ECMODE_VALUE);
 598         out_be32((void*)mode_port, MODE_JCUSFEN);
 599         out_be32((void*)intmask_port, INTMASK_MSK);
 600
 601         return ide_setup_pci_device(dev, d);
 602 }
 603
 604 /**
 605  *      init_mmio_iops_scc      -       set up the iops for MMIO
 606  *      @hwif: interface to set up
 607  *
 608  */
 609
 610 static void __devinit init_mmio_iops_scc(ide_hwif_t *hwif)
 611 {
 612         struct pci_dev *dev = hwif->pci_dev;
 613         struct scc_ports *ports = pci_get_drvdata(dev);
 614         unsigned long dma_base = ports->dma;
 615
 616         ide_set_hwifdata(hwif, ports);
 617
 618         hwif->INB = scc_ide_inb;
 619         hwif->INW = scc_ide_inw;
 620         hwif->INL = scc_ide_inl;
 621         hwif->INSW = scc_ide_insw;
 622         hwif->INSL = scc_ide_insl;
 623         hwif->OUTB = scc_ide_outb;
 624         hwif->OUTBSYNC = scc_ide_outbsync;
 625         hwif->OUTW = scc_ide_outw;
 626         hwif->OUTL = scc_ide_outl;
 627         hwif->OUTSW = scc_ide_outsw;
 628         hwif->OUTSL = scc_ide_outsl;
 629
 630         hwif->io_ports[IDE_DATA_OFFSET] = dma_base + 0x20;
 631         hwif->io_ports[IDE_ERROR_OFFSET] = dma_base + 0x24;
 632         hwif->io_ports[IDE_NSECTOR_OFFSET] = dma_base + 0x28;
 633         hwif->io_ports[IDE_SECTOR_OFFSET] = dma_base + 0x2c;
 634         hwif->io_ports[IDE_LCYL_OFFSET] = dma_base + 0x30;
 635         hwif->io_ports[IDE_HCYL_OFFSET] = dma_base + 0x34;
 636         hwif->io_ports[IDE_SELECT_OFFSET] = dma_base + 0x38;
 637         hwif->io_ports[IDE_STATUS_OFFSET] = dma_base + 0x3c;
 638         hwif->io_ports[IDE_CONTROL_OFFSET] = dma_base + 0x40;
 639
 640         hwif->irq = hwif->pci_dev->irq;
 641         hwif->dma_base = dma_base;
 642         hwif->config_data = ports->ctl;
 643         hwif->mmio = 2;
 644 }
 645
 646 /**
 647  *      init_iops_scc   -       set up iops
 648  *      @hwif: interface to set up
 649  *
 650  *      Do the basic setup for the SCC hardware interface
 651  *      and then do the MMIO setup.
 652  */
 653
 654 static void __devinit init_iops_scc(ide_hwif_t *hwif)
 655 {
 656         struct pci_dev *dev =  hwif->pci_dev;
 657         hwif->hwif_data = NULL;
 658         if (pci_get_drvdata(dev) == NULL)
 659                 return;
 660         init_mmio_iops_scc(hwif);
 661 }
 662
 663 /**
 664  *      init_hwif_scc   -       set up hwif
 665  *      @hwif: interface to set up
 666  *
 667  *      We do the basic set up of the interface structure. The SCC
 668  *      requires several custom handlers so we override the default
 669  *      ide DMA handlers appropriately.
 670  */
 671
 672 static void __devinit init_hwif_scc(ide_hwif_t *hwif)
 673 {
 674         struct scc_ports *ports = ide_get_hwifdata(hwif);
 675
 676         ports->hwif_id = hwif->index;
 677
 678         hwif->dma_command = hwif->dma_base;
 679         hwif->dma_status = hwif->dma_base + 0x04;
 680         hwif->dma_prdtable = hwif->dma_base + 0x08;
 681
 682         hwif->OUTL(hwif->dmatable_dma, (hwif->dma_base + 0x018)); /* PTERADD */
 683
 684         hwif->ide_dma_end = scc_ide_dma_end;
 685         hwif->speedproc = scc_tune_chipset;
 686         hwif->tuneproc = scc_tuneproc;
 687         hwif->ide_dma_check = scc_config_drive_for_dma;
 688
 689         hwif->drives[0].autotune = IDE_TUNE_AUTO;
 690         hwif->drives[1].autotune = IDE_TUNE_AUTO;
 691
 692         if (hwif->INL(hwif->config_data + 0xff0) & CCKCTRL_ATACLKOEN) {
 693                 hwif->ultra_mask = 0x7f; /* 133MHz */
 694         } else {
 695                 hwif->ultra_mask = 0x3f; /* 100MHz */
 696         }
 697         hwif->mwdma_mask = 0x00;
 698         hwif->swdma_mask = 0x00;
 699         hwif->atapi_dma = 1;
 700
 701         /* we support 80c cable only. */
 702         hwif->udma_four = 1;
 703
 704         hwif->autodma = 0;
 705         if (!noautodma)
 706                 hwif->autodma = 1;
 707         hwif->drives[0].autodma = hwif->autodma;
 708         hwif->drives[1].autodma = hwif->autodma;
 709 }
 710
 711 #define DECLARE_SCC_DEV(name_str)                       \
 712   {                                                     \
 713       .name             = name_str,                     \
 714       .init_setup       = init_setup_scc,               \
 715       .init_iops        = init_iops_scc,                \
 716       .init_hwif        = init_hwif_scc,                \
 717       .channels = 1,                                    \
 718       .autodma  = AUTODMA,                              \
 719       .bootable = ON_BOARD,                             \
 720   }
 721
 722 static ide_pci_device_t scc_chipsets[] __devinitdata = {
 723         /* 0 */ DECLARE_SCC_DEV("sccIDE"),
 724 };
 725
 726 /**
 727  *      scc_init_one    -       pci layer discovery entry
 728  *      @dev: PCI device
 729  *      @id: ident table entry
 730  *
 731  *      Called by the PCI code when it finds an SCC PATA controller.
 732  *      We then use the IDE PCI generic helper to do most of the work.
 733  */
 734
 735 static int __devinit scc_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 736 {
 737         ide_pci_device_t *d = &scc_chipsets[id->driver_data];
 738         return d->init_setup(dev, d);
 739 }
 740
 741 /**
 742  *      scc_remove      -       pci layer remove entry
 743  *      @dev: PCI device
 744  *
 745  *      Called by the PCI code when it removes an SCC PATA controller.
 746  */
 747
 748 static void __devexit scc_remove(struct pci_dev *dev)
 749 {
 750         struct scc_ports *ports = pci_get_drvdata(dev);
 751         ide_hwif_t *hwif = &ide_hwifs[ports->hwif_id];
 752         unsigned long ctl_base = pci_resource_start(dev, 0);
 753         unsigned long dma_base = pci_resource_start(dev, 1);
 754         unsigned long ctl_size = pci_resource_len(dev, 0);
 755         unsigned long dma_size = pci_resource_len(dev, 1);
 756
 757         if (hwif->dmatable_cpu) {
 758                 pci_free_consistent(hwif->pci_dev,
 759                                     PRD_ENTRIES * PRD_BYTES,
 760                                     hwif->dmatable_cpu,
 761                                     hwif->dmatable_dma);
 762                 hwif->dmatable_cpu = NULL;
 763         }
 764
 765         ide_unregister(hwif->index);
 766
 767         hwif->chipset = ide_unknown;
 768         iounmap((void*)ports->dma);
 769         iounmap((void*)ports->ctl);
 770         release_mem_region(dma_base, dma_size);
 771         release_mem_region(ctl_base, ctl_size);
 772         memset(ports, 0, sizeof(*ports));
 773 }
 774
 775 static struct pci_device_id scc_pci_tbl[] = {
 776         { PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_SCC_ATA,  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 777         { 0, },
 778 };
 779 MODULE_DEVICE_TABLE(pci, scc_pci_tbl);
 780
 781 static struct pci_driver driver = {
 782         .name = "SCC IDE",
 783         .id_table = scc_pci_tbl,
 784         .probe = scc_init_one,
 785         .remove = scc_remove,
 786 };
 787
 788 static int scc_ide_init(void)
 789 {
 790         return ide_pci_register_driver(&driver);
 791 }
 792
 793 module_init(scc_ide_init);
 794 /* -- No exit code?
 795 static void scc_ide_exit(void)
 796 {
 797         ide_pci_unregister_driver(&driver);
 798 }
 799 module_exit(scc_ide_exit);
 800  */
 801
 802
 803 MODULE_DESCRIPTION("PCI driver module for Toshiba SCC IDE");
 804 MODULE_LICENSE("GPL");