git.rot13.org Git - linux/blob - drivers/infiniband/hw/bnxt_re/ib_verbs.c

   1 /*
   2  * Broadcom NetXtreme-E RoCE driver.
   3  *
   4  * Copyright (c) 2016 - 2017, Broadcom. All rights reserved.  The term
   5  * Broadcom refers to Broadcom Limited and/or its subsidiaries.
   6  *
   7  * This software is available to you under a choice of one of two
   8  * licenses.  You may choose to be licensed under the terms of the GNU
   9  * General Public License (GPL) Version 2, available from the file
  10  * COPYING in the main directory of this source tree, or the
  11  * BSD license below:
  12  *
  13  * Redistribution and use in source and binary forms, with or without
  14  * modification, are permitted provided that the following conditions
  15  * are met:
  16  *
  17  * 1. Redistributions of source code must retain the above copyright
  18  *    notice, this list of conditions and the following disclaimer.
  19  * 2. Redistributions in binary form must reproduce the above copyright
  20  *    notice, this list of conditions and the following disclaimer in
  21  *    the documentation and/or other materials provided with the
  22  *    distribution.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
  25  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  26  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
  28  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  29  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  30  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  31  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  32  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  33  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  34  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35  *
  36  * Description: IB Verbs interpreter
  37  */
  38
  39 #include <linux/interrupt.h>
  40 #include <linux/types.h>
  41 #include <linux/pci.h>
  42 #include <linux/netdevice.h>
  43 #include <linux/if_ether.h>
  44
  45 #include <rdma/ib_verbs.h>
  46 #include <rdma/ib_user_verbs.h>
  47 #include <rdma/ib_umem.h>
  48 #include <rdma/ib_addr.h>
  49 #include <rdma/ib_mad.h>
  50 #include <rdma/ib_cache.h>
  51
  52 #include "bnxt_ulp.h"
  53
  54 #include "roce_hsi.h"
  55 #include "qplib_res.h"
  56 #include "qplib_sp.h"
  57 #include "qplib_fp.h"
  58 #include "qplib_rcfw.h"
  59
  60 #include "bnxt_re.h"
  61 #include "ib_verbs.h"
  62 #include <rdma/bnxt_re-abi.h>
  63
  64 static int __from_ib_access_flags(int iflags)
  65 {
  66         int qflags = 0;
  67
  68         if (iflags & IB_ACCESS_LOCAL_WRITE)
  69                 qflags |= BNXT_QPLIB_ACCESS_LOCAL_WRITE;
  70         if (iflags & IB_ACCESS_REMOTE_READ)
  71                 qflags |= BNXT_QPLIB_ACCESS_REMOTE_READ;
  72         if (iflags & IB_ACCESS_REMOTE_WRITE)
  73                 qflags |= BNXT_QPLIB_ACCESS_REMOTE_WRITE;
  74         if (iflags & IB_ACCESS_REMOTE_ATOMIC)
  75                 qflags |= BNXT_QPLIB_ACCESS_REMOTE_ATOMIC;
  76         if (iflags & IB_ACCESS_MW_BIND)
  77                 qflags |= BNXT_QPLIB_ACCESS_MW_BIND;
  78         if (iflags & IB_ZERO_BASED)
  79                 qflags |= BNXT_QPLIB_ACCESS_ZERO_BASED;
  80         if (iflags & IB_ACCESS_ON_DEMAND)
  81                 qflags |= BNXT_QPLIB_ACCESS_ON_DEMAND;
  82         return qflags;
  83 };
  84
  85 static enum ib_access_flags __to_ib_access_flags(int qflags)
  86 {
  87         enum ib_access_flags iflags = 0;
  88
  89         if (qflags & BNXT_QPLIB_ACCESS_LOCAL_WRITE)
  90                 iflags |= IB_ACCESS_LOCAL_WRITE;
  91         if (qflags & BNXT_QPLIB_ACCESS_REMOTE_WRITE)
  92                 iflags |= IB_ACCESS_REMOTE_WRITE;
  93         if (qflags & BNXT_QPLIB_ACCESS_REMOTE_READ)
  94                 iflags |= IB_ACCESS_REMOTE_READ;
  95         if (qflags & BNXT_QPLIB_ACCESS_REMOTE_ATOMIC)
  96                 iflags |= IB_ACCESS_REMOTE_ATOMIC;
  97         if (qflags & BNXT_QPLIB_ACCESS_MW_BIND)
  98                 iflags |= IB_ACCESS_MW_BIND;
  99         if (qflags & BNXT_QPLIB_ACCESS_ZERO_BASED)
 100                 iflags |= IB_ZERO_BASED;
 101         if (qflags & BNXT_QPLIB_ACCESS_ON_DEMAND)
 102                 iflags |= IB_ACCESS_ON_DEMAND;
 103         return iflags;
 104 };
 105
 106 static int bnxt_re_build_sgl(struct ib_sge *ib_sg_list,
 107                              struct bnxt_qplib_sge *sg_list, int num)
 108 {
 109         int i, total = 0;
 110
 111         for (i = 0; i < num; i++) {
 112                 sg_list[i].addr = ib_sg_list[i].addr;
 113                 sg_list[i].lkey = ib_sg_list[i].lkey;
 114                 sg_list[i].size = ib_sg_list[i].length;
 115                 total += sg_list[i].size;
 116         }
 117         return total;
 118 }
 119
 120 /* Device */
 121 struct net_device *bnxt_re_get_netdev(struct ib_device *ibdev, u8 port_num)
 122 {
 123         struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
 124         struct net_device *netdev = NULL;
 125
 126         rcu_read_lock();
 127         if (rdev)
 128                 netdev = rdev->netdev;
 129         if (netdev)
 130                 dev_hold(netdev);
 131
 132         rcu_read_unlock();
 133         return netdev;
 134 }
 135
 136 int bnxt_re_query_device(struct ib_device *ibdev,
 137                          struct ib_device_attr *ib_attr,
 138                          struct ib_udata *udata)
 139 {
 140         struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
 141         struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
 142
 143         memset(ib_attr, 0, sizeof(*ib_attr));
 144
 145         ib_attr->fw_ver = (u64)(unsigned long)(dev_attr->fw_ver);
 146         bnxt_qplib_get_guid(rdev->netdev->dev_addr,
 147                             (u8 *)&ib_attr->sys_image_guid);
 148         ib_attr->max_mr_size = ~0ull;
 149         ib_attr->page_size_cap = BNXT_RE_PAGE_SIZE_4K | BNXT_RE_PAGE_SIZE_8K |
 150                                  BNXT_RE_PAGE_SIZE_64K | BNXT_RE_PAGE_SIZE_2M |
 151                                  BNXT_RE_PAGE_SIZE_8M | BNXT_RE_PAGE_SIZE_1G;
 152
 153         ib_attr->vendor_id = rdev->en_dev->pdev->vendor;
 154         ib_attr->vendor_part_id = rdev->en_dev->pdev->device;
 155         ib_attr->hw_ver = rdev->en_dev->pdev->subsystem_device;
 156         ib_attr->max_qp = dev_attr->max_qp;
 157         ib_attr->max_qp_wr = dev_attr->max_qp_wqes;
 158         ib_attr->device_cap_flags =
 159                                     IB_DEVICE_CURR_QP_STATE_MOD
 160                                     | IB_DEVICE_RC_RNR_NAK_GEN
 161                                     | IB_DEVICE_SHUTDOWN_PORT
 162                                     | IB_DEVICE_SYS_IMAGE_GUID
 163                                     | IB_DEVICE_LOCAL_DMA_LKEY
 164                                     | IB_DEVICE_RESIZE_MAX_WR
 165                                     | IB_DEVICE_PORT_ACTIVE_EVENT
 166                                     | IB_DEVICE_N_NOTIFY_CQ
 167                                     | IB_DEVICE_MEM_WINDOW
 168                                     | IB_DEVICE_MEM_WINDOW_TYPE_2B
 169                                     | IB_DEVICE_MEM_MGT_EXTENSIONS;
 170         ib_attr->max_sge = dev_attr->max_qp_sges;
 171         ib_attr->max_sge_rd = dev_attr->max_qp_sges;
 172         ib_attr->max_cq = dev_attr->max_cq;
 173         ib_attr->max_cqe = dev_attr->max_cq_wqes;
 174         ib_attr->max_mr = dev_attr->max_mr;
 175         ib_attr->max_pd = dev_attr->max_pd;
 176         ib_attr->max_qp_rd_atom = dev_attr->max_qp_rd_atom;
 177         ib_attr->max_qp_init_rd_atom = dev_attr->max_qp_rd_atom;
 178         ib_attr->atomic_cap = IB_ATOMIC_HCA;
 179         ib_attr->masked_atomic_cap = IB_ATOMIC_HCA;
 180
 181         ib_attr->max_ee_rd_atom = 0;
 182         ib_attr->max_res_rd_atom = 0;
 183         ib_attr->max_ee_init_rd_atom = 0;
 184         ib_attr->max_ee = 0;
 185         ib_attr->max_rdd = 0;
 186         ib_attr->max_mw = dev_attr->max_mw;
 187         ib_attr->max_raw_ipv6_qp = 0;
 188         ib_attr->max_raw_ethy_qp = dev_attr->max_raw_ethy_qp;
 189         ib_attr->max_mcast_grp = 0;
 190         ib_attr->max_mcast_qp_attach = 0;
 191         ib_attr->max_total_mcast_qp_attach = 0;
 192         ib_attr->max_ah = dev_attr->max_ah;
 193
 194         ib_attr->max_fmr = 0;
 195         ib_attr->max_map_per_fmr = 0;
 196
 197         ib_attr->max_srq = dev_attr->max_srq;
 198         ib_attr->max_srq_wr = dev_attr->max_srq_wqes;
 199         ib_attr->max_srq_sge = dev_attr->max_srq_sges;
 200
 201         ib_attr->max_fast_reg_page_list_len = MAX_PBL_LVL_1_PGS;
 202
 203         ib_attr->max_pkeys = 1;
 204         ib_attr->local_ca_ack_delay = 0;
 205         return 0;
 206 }
 207
 208 int bnxt_re_modify_device(struct ib_device *ibdev,
 209                           int device_modify_mask,
 210                           struct ib_device_modify *device_modify)
 211 {
 212         switch (device_modify_mask) {
 213         case IB_DEVICE_MODIFY_SYS_IMAGE_GUID:
 214                 /* Modify the GUID requires the modification of the GID table */
 215                 /* GUID should be made as READ-ONLY */
 216                 break;
 217         case IB_DEVICE_MODIFY_NODE_DESC:
 218                 /* Node Desc should be made as READ-ONLY */
 219                 break;
 220         default:
 221                 break;
 222         }
 223         return 0;
 224 }
 225
 226 static void __to_ib_speed_width(struct net_device *netdev, u8 *speed, u8 *width)
 227 {
 228         struct ethtool_link_ksettings lksettings;
 229         u32 espeed;
 230
 231         if (netdev->ethtool_ops && netdev->ethtool_ops->get_link_ksettings) {
 232                 memset(&lksettings, 0, sizeof(lksettings));
 233                 rtnl_lock();
 234                 netdev->ethtool_ops->get_link_ksettings(netdev, &lksettings);
 235                 rtnl_unlock();
 236                 espeed = lksettings.base.speed;
 237         } else {
 238                 espeed = SPEED_UNKNOWN;
 239         }
 240         switch (espeed) {
 241         case SPEED_1000:
 242                 *speed = IB_SPEED_SDR;
 243                 *width = IB_WIDTH_1X;
 244                 break;
 245         case SPEED_10000:
 246                 *speed = IB_SPEED_QDR;
 247                 *width = IB_WIDTH_1X;
 248                 break;
 249         case SPEED_20000:
 250                 *speed = IB_SPEED_DDR;
 251                 *width = IB_WIDTH_4X;
 252                 break;
 253         case SPEED_25000:
 254                 *speed = IB_SPEED_EDR;
 255                 *width = IB_WIDTH_1X;
 256                 break;
 257         case SPEED_40000:
 258                 *speed = IB_SPEED_QDR;
 259                 *width = IB_WIDTH_4X;
 260                 break;
 261         case SPEED_50000:
 262                 break;
 263         default:
 264                 *speed = IB_SPEED_SDR;
 265                 *width = IB_WIDTH_1X;
 266                 break;
 267         }
 268 }
 269
 270 /* Port */
 271 int bnxt_re_query_port(struct ib_device *ibdev, u8 port_num,
 272                        struct ib_port_attr *port_attr)
 273 {
 274         struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
 275         struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
 276
 277         memset(port_attr, 0, sizeof(*port_attr));
 278
 279         if (netif_running(rdev->netdev) && netif_carrier_ok(rdev->netdev)) {
 280                 port_attr->state = IB_PORT_ACTIVE;
 281                 port_attr->phys_state = 5;
 282         } else {
 283                 port_attr->state = IB_PORT_DOWN;
 284                 port_attr->phys_state = 3;
 285         }
 286         port_attr->max_mtu = IB_MTU_4096;
 287         port_attr->active_mtu = iboe_get_mtu(rdev->netdev->mtu);
 288         port_attr->gid_tbl_len = dev_attr->max_sgid;
 289         port_attr->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP |
 290                                     IB_PORT_DEVICE_MGMT_SUP |
 291                                     IB_PORT_VENDOR_CLASS_SUP |
 292                                     IB_PORT_IP_BASED_GIDS;
 293
 294         /* Max MSG size set to 2G for now */
 295         port_attr->max_msg_sz = 0x80000000;
 296         port_attr->bad_pkey_cntr = 0;
 297         port_attr->qkey_viol_cntr = 0;
 298         port_attr->pkey_tbl_len = dev_attr->max_pkey;
 299         port_attr->lid = 0;
 300         port_attr->sm_lid = 0;
 301         port_attr->lmc = 0;
 302         port_attr->max_vl_num = 4;
 303         port_attr->sm_sl = 0;
 304         port_attr->subnet_timeout = 0;
 305         port_attr->init_type_reply = 0;
 306         /* call the underlying netdev's ethtool hooks to query speed settings
 307          * for which we acquire rtnl_lock _only_ if it's registered with
 308          * IB stack to avoid race in the NETDEV_UNREG path
 309          */
 310         if (test_bit(BNXT_RE_FLAG_IBDEV_REGISTERED, &rdev->flags))
 311                 __to_ib_speed_width(rdev->netdev, &port_attr->active_speed,
 312                                     &port_attr->active_width);
 313         return 0;
 314 }
 315
 316 int bnxt_re_modify_port(struct ib_device *ibdev, u8 port_num,
 317                         int port_modify_mask,
 318                         struct ib_port_modify *port_modify)
 319 {
 320         switch (port_modify_mask) {
 321         case IB_PORT_SHUTDOWN:
 322                 break;
 323         case IB_PORT_INIT_TYPE:
 324                 break;
 325         case IB_PORT_RESET_QKEY_CNTR:
 326                 break;
 327         default:
 328                 break;
 329         }
 330         return 0;
 331 }
 332
 333 int bnxt_re_get_port_immutable(struct ib_device *ibdev, u8 port_num,
 334                                struct ib_port_immutable *immutable)
 335 {
 336         struct ib_port_attr port_attr;
 337
 338         if (bnxt_re_query_port(ibdev, port_num, &port_attr))
 339                 return -EINVAL;
 340
 341         immutable->pkey_tbl_len = port_attr.pkey_tbl_len;
 342         immutable->gid_tbl_len = port_attr.gid_tbl_len;
 343         immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
 344         immutable->core_cap_flags |= RDMA_CORE_CAP_PROT_ROCE_UDP_ENCAP;
 345         immutable->max_mad_size = IB_MGMT_MAD_SIZE;
 346         return 0;
 347 }
 348
 349 int bnxt_re_query_pkey(struct ib_device *ibdev, u8 port_num,
 350                        u16 index, u16 *pkey)
 351 {
 352         struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
 353
 354         /* Ignore port_num */
 355
 356         memset(pkey, 0, sizeof(*pkey));
 357         return bnxt_qplib_get_pkey(&rdev->qplib_res,
 358                                    &rdev->qplib_res.pkey_tbl, index, pkey);
 359 }
 360
 361 int bnxt_re_query_gid(struct ib_device *ibdev, u8 port_num,
 362                       int index, union ib_gid *gid)
 363 {
 364         struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
 365         int rc = 0;
 366
 367         /* Ignore port_num */
 368         memset(gid, 0, sizeof(*gid));
 369         rc = bnxt_qplib_get_sgid(&rdev->qplib_res,
 370                                  &rdev->qplib_res.sgid_tbl, index,
 371                                  (struct bnxt_qplib_gid *)gid);
 372         return rc;
 373 }
 374
 375 int bnxt_re_del_gid(struct ib_device *ibdev, u8 port_num,
 376                     unsigned int index, void **context)
 377 {
 378         int rc = 0;
 379         struct bnxt_re_gid_ctx *ctx, **ctx_tbl;
 380         struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
 381         struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl;
 382
 383         /* Delete the entry from the hardware */
 384         ctx = *context;
 385         if (!ctx)
 386                 return -EINVAL;
 387
 388         if (sgid_tbl && sgid_tbl->active) {
 389                 if (ctx->idx >= sgid_tbl->max)
 390                         return -EINVAL;
 391                 ctx->refcnt--;
 392                 if (!ctx->refcnt) {
 393                         rc = bnxt_qplib_del_sgid(sgid_tbl,
 394                                                  &sgid_tbl->tbl[ctx->idx],
 395                                                  true);
 396                         if (rc) {
 397                                 dev_err(rdev_to_dev(rdev),
 398                                         "Failed to remove GID: %#x", rc);
 399                         } else {
 400                                 ctx_tbl = sgid_tbl->ctx;
 401                                 ctx_tbl[ctx->idx] = NULL;
 402                                 kfree(ctx);
 403                         }
 404                 }
 405         } else {
 406                 return -EINVAL;
 407         }
 408         return rc;
 409 }
 410
 411 int bnxt_re_add_gid(struct ib_device *ibdev, u8 port_num,
 412                     unsigned int index, const union ib_gid *gid,
 413                     const struct ib_gid_attr *attr, void **context)
 414 {
 415         int rc;
 416         u32 tbl_idx = 0;
 417         u16 vlan_id = 0xFFFF;
 418         struct bnxt_re_gid_ctx *ctx, **ctx_tbl;
 419         struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
 420         struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl;
 421
 422         if ((attr->ndev) && is_vlan_dev(attr->ndev))
 423                 vlan_id = vlan_dev_vlan_id(attr->ndev);
 424
 425         rc = bnxt_qplib_add_sgid(sgid_tbl, (struct bnxt_qplib_gid *)gid,
 426                                  rdev->qplib_res.netdev->dev_addr,
 427                                  vlan_id, true, &tbl_idx);
 428         if (rc == -EALREADY) {
 429                 ctx_tbl = sgid_tbl->ctx;
 430                 ctx_tbl[tbl_idx]->refcnt++;
 431                 *context = ctx_tbl[tbl_idx];
 432                 return 0;
 433         }
 434
 435         if (rc < 0) {
 436                 dev_err(rdev_to_dev(rdev), "Failed to add GID: %#x", rc);
 437                 return rc;
 438         }
 439
 440         ctx = kmalloc(sizeof(*ctx), GFP_KERNEL);
 441         if (!ctx)
 442                 return -ENOMEM;
 443         ctx_tbl = sgid_tbl->ctx;
 444         ctx->idx = tbl_idx;
 445         ctx->refcnt = 1;
 446         ctx_tbl[tbl_idx] = ctx;
 447
 448         return rc;
 449 }
 450
 451 enum rdma_link_layer bnxt_re_get_link_layer(struct ib_device *ibdev,
 452                                             u8 port_num)
 453 {
 454         return IB_LINK_LAYER_ETHERNET;
 455 }
 456
 457 #define BNXT_RE_FENCE_PBL_SIZE  DIV_ROUND_UP(BNXT_RE_FENCE_BYTES, PAGE_SIZE)
 458
 459 static void bnxt_re_create_fence_wqe(struct bnxt_re_pd *pd)
 460 {
 461         struct bnxt_re_fence_data *fence = &pd->fence;
 462         struct ib_mr *ib_mr = &fence->mr->ib_mr;
 463         struct bnxt_qplib_swqe *wqe = &fence->bind_wqe;
 464
 465         memset(wqe, 0, sizeof(*wqe));
 466         wqe->type = BNXT_QPLIB_SWQE_TYPE_BIND_MW;
 467         wqe->wr_id = BNXT_QPLIB_FENCE_WRID;
 468         wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
 469         wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
 470         wqe->bind.zero_based = false;
 471         wqe->bind.parent_l_key = ib_mr->lkey;
 472         wqe->bind.va = (u64)(unsigned long)fence->va;
 473         wqe->bind.length = fence->size;
 474         wqe->bind.access_cntl = __from_ib_access_flags(IB_ACCESS_REMOTE_READ);
 475         wqe->bind.mw_type = SQ_BIND_MW_TYPE_TYPE1;
 476
 477         /* Save the initial rkey in fence structure for now;
 478          * wqe->bind.r_key will be set at (re)bind time.
 479          */
 480         fence->bind_rkey = ib_inc_rkey(fence->mw->rkey);
 481 }
 482
 483 static int bnxt_re_bind_fence_mw(struct bnxt_qplib_qp *qplib_qp)
 484 {
 485         struct bnxt_re_qp *qp = container_of(qplib_qp, struct bnxt_re_qp,
 486                                              qplib_qp);
 487         struct ib_pd *ib_pd = qp->ib_qp.pd;
 488         struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
 489         struct bnxt_re_fence_data *fence = &pd->fence;
 490         struct bnxt_qplib_swqe *fence_wqe = &fence->bind_wqe;
 491         struct bnxt_qplib_swqe wqe;
 492         int rc;
 493
 494         memcpy(&wqe, fence_wqe, sizeof(wqe));
 495         wqe.bind.r_key = fence->bind_rkey;
 496         fence->bind_rkey = ib_inc_rkey(fence->bind_rkey);
 497
 498         dev_dbg(rdev_to_dev(qp->rdev),
 499                 "Posting bind fence-WQE: rkey: %#x QP: %d PD: %p\n",
 500                 wqe.bind.r_key, qp->qplib_qp.id, pd);
 501         rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe);
 502         if (rc) {
 503                 dev_err(rdev_to_dev(qp->rdev), "Failed to bind fence-WQE\n");
 504                 return rc;
 505         }
 506         bnxt_qplib_post_send_db(&qp->qplib_qp);
 507
 508         return rc;
 509 }
 510
 511 static void bnxt_re_destroy_fence_mr(struct bnxt_re_pd *pd)
 512 {
 513         struct bnxt_re_fence_data *fence = &pd->fence;
 514         struct bnxt_re_dev *rdev = pd->rdev;
 515         struct device *dev = &rdev->en_dev->pdev->dev;
 516         struct bnxt_re_mr *mr = fence->mr;
 517
 518         if (fence->mw) {
 519                 bnxt_re_dealloc_mw(fence->mw);
 520                 fence->mw = NULL;
 521         }
 522         if (mr) {
 523                 if (mr->ib_mr.rkey)
 524                         bnxt_qplib_dereg_mrw(&rdev->qplib_res, &mr->qplib_mr,
 525                                              true);
 526                 if (mr->ib_mr.lkey)
 527                         bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
 528                 kfree(mr);
 529                 fence->mr = NULL;
 530         }
 531         if (fence->dma_addr) {
 532                 dma_unmap_single(dev, fence->dma_addr, BNXT_RE_FENCE_BYTES,
 533                                  DMA_BIDIRECTIONAL);
 534                 fence->dma_addr = 0;
 535         }
 536 }
 537
 538 static int bnxt_re_create_fence_mr(struct bnxt_re_pd *pd)
 539 {
 540         int mr_access_flags = IB_ACCESS_LOCAL_WRITE | IB_ACCESS_MW_BIND;
 541         struct bnxt_re_fence_data *fence = &pd->fence;
 542         struct bnxt_re_dev *rdev = pd->rdev;
 543         struct device *dev = &rdev->en_dev->pdev->dev;
 544         struct bnxt_re_mr *mr = NULL;
 545         dma_addr_t dma_addr = 0;
 546         struct ib_mw *mw;
 547         u64 pbl_tbl;
 548         int rc;
 549
 550         dma_addr = dma_map_single(dev, fence->va, BNXT_RE_FENCE_BYTES,
 551                                   DMA_BIDIRECTIONAL);
 552         rc = dma_mapping_error(dev, dma_addr);
 553         if (rc) {
 554                 dev_err(rdev_to_dev(rdev), "Failed to dma-map fence-MR-mem\n");
 555                 rc = -EIO;
 556                 fence->dma_addr = 0;
 557                 goto fail;
 558         }
 559         fence->dma_addr = dma_addr;
 560
 561         /* Allocate a MR */
 562         mr = kzalloc(sizeof(*mr), GFP_KERNEL);
 563         if (!mr) {
 564                 rc = -ENOMEM;
 565                 goto fail;
 566         }
 567         fence->mr = mr;
 568         mr->rdev = rdev;
 569         mr->qplib_mr.pd = &pd->qplib_pd;
 570         mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR;
 571         mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags);
 572         rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
 573         if (rc) {
 574                 dev_err(rdev_to_dev(rdev), "Failed to alloc fence-HW-MR\n");
 575                 goto fail;
 576         }
 577
 578         /* Register MR */
 579         mr->ib_mr.lkey = mr->qplib_mr.lkey;
 580         mr->qplib_mr.va = (u64)(unsigned long)fence->va;
 581         mr->qplib_mr.total_size = BNXT_RE_FENCE_BYTES;
 582         pbl_tbl = dma_addr;
 583         rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, &pbl_tbl,
 584                                BNXT_RE_FENCE_PBL_SIZE, false);
 585         if (rc) {
 586                 dev_err(rdev_to_dev(rdev), "Failed to register fence-MR\n");
 587                 goto fail;
 588         }
 589         mr->ib_mr.rkey = mr->qplib_mr.rkey;
 590
 591         /* Create a fence MW only for kernel consumers */
 592         mw = bnxt_re_alloc_mw(&pd->ib_pd, IB_MW_TYPE_1, NULL);
 593         if (IS_ERR(mw)) {
 594                 dev_err(rdev_to_dev(rdev),
 595                         "Failed to create fence-MW for PD: %p\n", pd);
 596                 rc = PTR_ERR(mw);
 597                 goto fail;
 598         }
 599         fence->mw = mw;
 600
 601         bnxt_re_create_fence_wqe(pd);
 602         return 0;
 603
 604 fail:
 605         bnxt_re_destroy_fence_mr(pd);
 606         return rc;
 607 }
 608
 609 /* Protection Domains */
 610 int bnxt_re_dealloc_pd(struct ib_pd *ib_pd)
 611 {
 612         struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
 613         struct bnxt_re_dev *rdev = pd->rdev;
 614         int rc;
 615
 616         bnxt_re_destroy_fence_mr(pd);
 617
 618         if (pd->qplib_pd.id) {
 619                 rc = bnxt_qplib_dealloc_pd(&rdev->qplib_res,
 620                                            &rdev->qplib_res.pd_tbl,
 621                                            &pd->qplib_pd);
 622                 if (rc)
 623                         dev_err(rdev_to_dev(rdev), "Failed to deallocate HW PD");
 624         }
 625
 626         kfree(pd);
 627         return 0;
 628 }
 629
 630 struct ib_pd *bnxt_re_alloc_pd(struct ib_device *ibdev,
 631                                struct ib_ucontext *ucontext,
 632                                struct ib_udata *udata)
 633 {
 634         struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
 635         struct bnxt_re_ucontext *ucntx = container_of(ucontext,
 636                                                       struct bnxt_re_ucontext,
 637                                                       ib_uctx);
 638         struct bnxt_re_pd *pd;
 639         int rc;
 640
 641         pd = kzalloc(sizeof(*pd), GFP_KERNEL);
 642         if (!pd)
 643                 return ERR_PTR(-ENOMEM);
 644
 645         pd->rdev = rdev;
 646         if (bnxt_qplib_alloc_pd(&rdev->qplib_res.pd_tbl, &pd->qplib_pd)) {
 647                 dev_err(rdev_to_dev(rdev), "Failed to allocate HW PD");
 648                 rc = -ENOMEM;
 649                 goto fail;
 650         }
 651
 652         if (udata) {
 653                 struct bnxt_re_pd_resp resp;
 654
 655                 if (!ucntx->dpi.dbr) {
 656                         /* Allocate DPI in alloc_pd to avoid failing of
 657                          * ibv_devinfo and family of application when DPIs
 658                          * are depleted.
 659                          */
 660                         if (bnxt_qplib_alloc_dpi(&rdev->qplib_res.dpi_tbl,
 661                                                  &ucntx->dpi, ucntx)) {
 662                                 rc = -ENOMEM;
 663                                 goto dbfail;
 664                         }
 665                 }
 666
 667                 resp.pdid = pd->qplib_pd.id;
 668                 /* Still allow mapping this DBR to the new user PD. */
 669                 resp.dpi = ucntx->dpi.dpi;
 670                 resp.dbr = (u64)ucntx->dpi.umdbr;
 671
 672                 rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
 673                 if (rc) {
 674                         dev_err(rdev_to_dev(rdev),
 675                                 "Failed to copy user response\n");
 676                         goto dbfail;
 677                 }
 678         }
 679
 680         if (!udata)
 681                 if (bnxt_re_create_fence_mr(pd))
 682                         dev_warn(rdev_to_dev(rdev),
 683                                  "Failed to create Fence-MR\n");
 684         return &pd->ib_pd;
 685 dbfail:
 686         (void)bnxt_qplib_dealloc_pd(&rdev->qplib_res, &rdev->qplib_res.pd_tbl,
 687                                     &pd->qplib_pd);
 688 fail:
 689         kfree(pd);
 690         return ERR_PTR(rc);
 691 }
 692
 693 /* Address Handles */
 694 int bnxt_re_destroy_ah(struct ib_ah *ib_ah)
 695 {
 696         struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah);
 697         struct bnxt_re_dev *rdev = ah->rdev;
 698         int rc;
 699
 700         rc = bnxt_qplib_destroy_ah(&rdev->qplib_res, &ah->qplib_ah);
 701         if (rc) {
 702                 dev_err(rdev_to_dev(rdev), "Failed to destroy HW AH");
 703                 return rc;
 704         }
 705         kfree(ah);
 706         return 0;
 707 }
 708
 709 struct ib_ah *bnxt_re_create_ah(struct ib_pd *ib_pd,
 710                                 struct rdma_ah_attr *ah_attr,
 711                                 struct ib_udata *udata)
 712 {
 713         struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
 714         struct bnxt_re_dev *rdev = pd->rdev;
 715         struct bnxt_re_ah *ah;
 716         const struct ib_global_route *grh = rdma_ah_read_grh(ah_attr);
 717         int rc;
 718         u16 vlan_tag;
 719         u8 nw_type;
 720
 721         struct ib_gid_attr sgid_attr;
 722
 723         if (!(rdma_ah_get_ah_flags(ah_attr) & IB_AH_GRH)) {
 724                 dev_err(rdev_to_dev(rdev), "Failed to alloc AH: GRH not set");
 725                 return ERR_PTR(-EINVAL);
 726         }
 727         ah = kzalloc(sizeof(*ah), GFP_ATOMIC);
 728         if (!ah)
 729                 return ERR_PTR(-ENOMEM);
 730
 731         ah->rdev = rdev;
 732         ah->qplib_ah.pd = &pd->qplib_pd;
 733
 734         /* Supply the configuration for the HW */
 735         memcpy(ah->qplib_ah.dgid.data, grh->dgid.raw,
 736                sizeof(union ib_gid));
 737         /*
 738          * If RoCE V2 is enabled, stack will have two entries for
 739          * each GID entry. Avoiding this duplicte entry in HW. Dividing
 740          * the GID index by 2 for RoCE V2
 741          */
 742         ah->qplib_ah.sgid_index = grh->sgid_index / 2;
 743         ah->qplib_ah.host_sgid_index = grh->sgid_index;
 744         ah->qplib_ah.traffic_class = grh->traffic_class;
 745         ah->qplib_ah.flow_label = grh->flow_label;
 746         ah->qplib_ah.hop_limit = grh->hop_limit;
 747         ah->qplib_ah.sl = rdma_ah_get_sl(ah_attr);
 748         if (ib_pd->uobject &&
 749             !rdma_is_multicast_addr((struct in6_addr *)
 750                                     grh->dgid.raw) &&
 751             !rdma_link_local_addr((struct in6_addr *)
 752                                   grh->dgid.raw)) {
 753                 union ib_gid sgid;
 754
 755                 rc = ib_get_cached_gid(&rdev->ibdev, 1,
 756                                        grh->sgid_index, &sgid,
 757                                        &sgid_attr);
 758                 if (rc) {
 759                         dev_err(rdev_to_dev(rdev),
 760                                 "Failed to query gid at index %d",
 761                                 grh->sgid_index);
 762                         goto fail;
 763                 }
 764                 if (sgid_attr.ndev) {
 765                         if (is_vlan_dev(sgid_attr.ndev))
 766                                 vlan_tag = vlan_dev_vlan_id(sgid_attr.ndev);
 767                         dev_put(sgid_attr.ndev);
 768                 }
 769                 /* Get network header type for this GID */
 770                 nw_type = ib_gid_to_network_type(sgid_attr.gid_type, &sgid);
 771                 switch (nw_type) {
 772                 case RDMA_NETWORK_IPV4:
 773                         ah->qplib_ah.nw_type = CMDQ_CREATE_AH_TYPE_V2IPV4;
 774                         break;
 775                 case RDMA_NETWORK_IPV6:
 776                         ah->qplib_ah.nw_type = CMDQ_CREATE_AH_TYPE_V2IPV6;
 777                         break;
 778                 default:
 779                         ah->qplib_ah.nw_type = CMDQ_CREATE_AH_TYPE_V1;
 780                         break;
 781                 }
 782                 rc = rdma_addr_find_l2_eth_by_grh(&sgid, &grh->dgid,
 783                                                   ah_attr->roce.dmac, &vlan_tag,
 784                                                   &sgid_attr.ndev->ifindex,
 785                                                   NULL);
 786                 if (rc) {
 787                         dev_err(rdev_to_dev(rdev), "Failed to get dmac\n");
 788                         goto fail;
 789                 }
 790         }
 791
 792         memcpy(ah->qplib_ah.dmac, ah_attr->roce.dmac, ETH_ALEN);
 793         rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah);
 794         if (rc) {
 795                 dev_err(rdev_to_dev(rdev), "Failed to allocate HW AH");
 796                 goto fail;
 797         }
 798
 799         /* Write AVID to shared page. */
 800         if (ib_pd->uobject) {
 801                 struct ib_ucontext *ib_uctx = ib_pd->uobject->context;
 802                 struct bnxt_re_ucontext *uctx;
 803                 unsigned long flag;
 804                 u32 *wrptr;
 805
 806                 uctx = container_of(ib_uctx, struct bnxt_re_ucontext, ib_uctx);
 807                 spin_lock_irqsave(&uctx->sh_lock, flag);
 808                 wrptr = (u32 *)(uctx->shpg + BNXT_RE_AVID_OFFT);
 809                 *wrptr = ah->qplib_ah.id;
 810                 wmb(); /* make sure cache is updated. */
 811                 spin_unlock_irqrestore(&uctx->sh_lock, flag);
 812         }
 813
 814         return &ah->ib_ah;
 815
 816 fail:
 817         kfree(ah);
 818         return ERR_PTR(rc);
 819 }
 820
 821 int bnxt_re_modify_ah(struct ib_ah *ib_ah, struct rdma_ah_attr *ah_attr)
 822 {
 823         return 0;
 824 }
 825
 826 int bnxt_re_query_ah(struct ib_ah *ib_ah, struct rdma_ah_attr *ah_attr)
 827 {
 828         struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah);
 829
 830         ah_attr->type = ib_ah->type;
 831         rdma_ah_set_sl(ah_attr, ah->qplib_ah.sl);
 832         memcpy(ah_attr->roce.dmac, ah->qplib_ah.dmac, ETH_ALEN);
 833         rdma_ah_set_grh(ah_attr, NULL, 0,
 834                         ah->qplib_ah.host_sgid_index,
 835                         0, ah->qplib_ah.traffic_class);
 836         rdma_ah_set_dgid_raw(ah_attr, ah->qplib_ah.dgid.data);
 837         rdma_ah_set_port_num(ah_attr, 1);
 838         rdma_ah_set_static_rate(ah_attr, 0);
 839         return 0;
 840 }
 841
 842 /* Queue Pairs */
 843 int bnxt_re_destroy_qp(struct ib_qp *ib_qp)
 844 {
 845         struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
 846         struct bnxt_re_dev *rdev = qp->rdev;
 847         int rc;
 848
 849         rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp);
 850         if (rc) {
 851                 dev_err(rdev_to_dev(rdev), "Failed to destroy HW QP");
 852                 return rc;
 853         }
 854         if (ib_qp->qp_type == IB_QPT_GSI && rdev->qp1_sqp) {
 855                 rc = bnxt_qplib_destroy_ah(&rdev->qplib_res,
 856                                            &rdev->sqp_ah->qplib_ah);
 857                 if (rc) {
 858                         dev_err(rdev_to_dev(rdev),
 859                                 "Failed to destroy HW AH for shadow QP");
 860                         return rc;
 861                 }
 862
 863                 rc = bnxt_qplib_destroy_qp(&rdev->qplib_res,
 864                                            &rdev->qp1_sqp->qplib_qp);
 865                 if (rc) {
 866                         dev_err(rdev_to_dev(rdev),
 867                                 "Failed to destroy Shadow QP");
 868                         return rc;
 869                 }
 870                 mutex_lock(&rdev->qp_lock);
 871                 list_del(&rdev->qp1_sqp->list);
 872                 atomic_dec(&rdev->qp_count);
 873                 mutex_unlock(&rdev->qp_lock);
 874
 875                 kfree(rdev->sqp_ah);
 876                 kfree(rdev->qp1_sqp);
 877         }
 878
 879         if (!IS_ERR_OR_NULL(qp->rumem))
 880                 ib_umem_release(qp->rumem);
 881         if (!IS_ERR_OR_NULL(qp->sumem))
 882                 ib_umem_release(qp->sumem);
 883
 884         mutex_lock(&rdev->qp_lock);
 885         list_del(&qp->list);
 886         atomic_dec(&rdev->qp_count);
 887         mutex_unlock(&rdev->qp_lock);
 888         kfree(qp);
 889         return 0;
 890 }
 891
 892 static u8 __from_ib_qp_type(enum ib_qp_type type)
 893 {
 894         switch (type) {
 895         case IB_QPT_GSI:
 896                 return CMDQ_CREATE_QP1_TYPE_GSI;
 897         case IB_QPT_RC:
 898                 return CMDQ_CREATE_QP_TYPE_RC;
 899         case IB_QPT_UD:
 900                 return CMDQ_CREATE_QP_TYPE_UD;
 901         default:
 902                 return IB_QPT_MAX;
 903         }
 904 }
 905
 906 static int bnxt_re_init_user_qp(struct bnxt_re_dev *rdev, struct bnxt_re_pd *pd,
 907                                 struct bnxt_re_qp *qp, struct ib_udata *udata)
 908 {
 909         struct bnxt_re_qp_req ureq;
 910         struct bnxt_qplib_qp *qplib_qp = &qp->qplib_qp;
 911         struct ib_umem *umem;
 912         int bytes = 0;
 913         struct ib_ucontext *context = pd->ib_pd.uobject->context;
 914         struct bnxt_re_ucontext *cntx = container_of(context,
 915                                                      struct bnxt_re_ucontext,
 916                                                      ib_uctx);
 917         if (ib_copy_from_udata(&ureq, udata, sizeof(ureq)))
 918                 return -EFAULT;
 919
 920         bytes = (qplib_qp->sq.max_wqe * BNXT_QPLIB_MAX_SQE_ENTRY_SIZE);
 921         /* Consider mapping PSN search memory only for RC QPs. */
 922         if (qplib_qp->type == CMDQ_CREATE_QP_TYPE_RC)
 923                 bytes += (qplib_qp->sq.max_wqe * sizeof(struct sq_psn_search));
 924         bytes = PAGE_ALIGN(bytes);
 925         umem = ib_umem_get(context, ureq.qpsva, bytes,
 926                            IB_ACCESS_LOCAL_WRITE, 1);
 927         if (IS_ERR(umem))
 928                 return PTR_ERR(umem);
 929
 930         qp->sumem = umem;
 931         qplib_qp->sq.sglist = umem->sg_head.sgl;
 932         qplib_qp->sq.nmap = umem->nmap;
 933         qplib_qp->qp_handle = ureq.qp_handle;
 934
 935         if (!qp->qplib_qp.srq) {
 936                 bytes = (qplib_qp->rq.max_wqe * BNXT_QPLIB_MAX_RQE_ENTRY_SIZE);
 937                 bytes = PAGE_ALIGN(bytes);
 938                 umem = ib_umem_get(context, ureq.qprva, bytes,
 939                                    IB_ACCESS_LOCAL_WRITE, 1);
 940                 if (IS_ERR(umem))
 941                         goto rqfail;
 942                 qp->rumem = umem;
 943                 qplib_qp->rq.sglist = umem->sg_head.sgl;
 944                 qplib_qp->rq.nmap = umem->nmap;
 945         }
 946
 947         qplib_qp->dpi = &cntx->dpi;
 948         return 0;
 949 rqfail:
 950         ib_umem_release(qp->sumem);
 951         qp->sumem = NULL;
 952         qplib_qp->sq.sglist = NULL;
 953         qplib_qp->sq.nmap = 0;
 954
 955         return PTR_ERR(umem);
 956 }
 957
 958 static struct bnxt_re_ah *bnxt_re_create_shadow_qp_ah
 959                                 (struct bnxt_re_pd *pd,
 960                                  struct bnxt_qplib_res *qp1_res,
 961                                  struct bnxt_qplib_qp *qp1_qp)
 962 {
 963         struct bnxt_re_dev *rdev = pd->rdev;
 964         struct bnxt_re_ah *ah;
 965         union ib_gid sgid;
 966         int rc;
 967
 968         ah = kzalloc(sizeof(*ah), GFP_KERNEL);
 969         if (!ah)
 970                 return NULL;
 971
 972         memset(ah, 0, sizeof(*ah));
 973         ah->rdev = rdev;
 974         ah->qplib_ah.pd = &pd->qplib_pd;
 975
 976         rc = bnxt_re_query_gid(&rdev->ibdev, 1, 0, &sgid);
 977         if (rc)
 978                 goto fail;
 979
 980         /* supply the dgid data same as sgid */
 981         memcpy(ah->qplib_ah.dgid.data, &sgid.raw,
 982                sizeof(union ib_gid));
 983         ah->qplib_ah.sgid_index = 0;
 984
 985         ah->qplib_ah.traffic_class = 0;
 986         ah->qplib_ah.flow_label = 0;
 987         ah->qplib_ah.hop_limit = 1;
 988         ah->qplib_ah.sl = 0;
 989         /* Have DMAC same as SMAC */
 990         ether_addr_copy(ah->qplib_ah.dmac, rdev->netdev->dev_addr);
 991
 992         rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah);
 993         if (rc) {
 994                 dev_err(rdev_to_dev(rdev),
 995                         "Failed to allocate HW AH for Shadow QP");
 996                 goto fail;
 997         }
 998
 999         return ah;
1000
1001 fail:
1002         kfree(ah);
1003         return NULL;
1004 }
1005
1006 static struct bnxt_re_qp *bnxt_re_create_shadow_qp
1007                                 (struct bnxt_re_pd *pd,
1008                                  struct bnxt_qplib_res *qp1_res,
1009                                  struct bnxt_qplib_qp *qp1_qp)
1010 {
1011         struct bnxt_re_dev *rdev = pd->rdev;
1012         struct bnxt_re_qp *qp;
1013         int rc;
1014
1015         qp = kzalloc(sizeof(*qp), GFP_KERNEL);
1016         if (!qp)
1017                 return NULL;
1018
1019         memset(qp, 0, sizeof(*qp));
1020         qp->rdev = rdev;
1021
1022         /* Initialize the shadow QP structure from the QP1 values */
1023         ether_addr_copy(qp->qplib_qp.smac, rdev->netdev->dev_addr);
1024
1025         qp->qplib_qp.pd = &pd->qplib_pd;
1026         qp->qplib_qp.qp_handle = (u64)(unsigned long)(&qp->qplib_qp);
1027         qp->qplib_qp.type = IB_QPT_UD;
1028
1029         qp->qplib_qp.max_inline_data = 0;
1030         qp->qplib_qp.sig_type = true;
1031
1032         /* Shadow QP SQ depth should be same as QP1 RQ depth */
1033         qp->qplib_qp.sq.max_wqe = qp1_qp->rq.max_wqe;
1034         qp->qplib_qp.sq.max_sge = 2;
1035         /* Q full delta can be 1 since it is internal QP */
1036         qp->qplib_qp.sq.q_full_delta = 1;
1037
1038         qp->qplib_qp.scq = qp1_qp->scq;
1039         qp->qplib_qp.rcq = qp1_qp->rcq;
1040
1041         qp->qplib_qp.rq.max_wqe = qp1_qp->rq.max_wqe;
1042         qp->qplib_qp.rq.max_sge = qp1_qp->rq.max_sge;
1043         /* Q full delta can be 1 since it is internal QP */
1044         qp->qplib_qp.rq.q_full_delta = 1;
1045
1046         qp->qplib_qp.mtu = qp1_qp->mtu;
1047
1048         qp->qplib_qp.sq_hdr_buf_size = 0;
1049         qp->qplib_qp.rq_hdr_buf_size = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6;
1050         qp->qplib_qp.dpi = &rdev->dpi_privileged;
1051
1052         rc = bnxt_qplib_create_qp(qp1_res, &qp->qplib_qp);
1053         if (rc)
1054                 goto fail;
1055
1056         rdev->sqp_id = qp->qplib_qp.id;
1057
1058         spin_lock_init(&qp->sq_lock);
1059         INIT_LIST_HEAD(&qp->list);
1060         mutex_lock(&rdev->qp_lock);
1061         list_add_tail(&qp->list, &rdev->qp_list);
1062         atomic_inc(&rdev->qp_count);
1063         mutex_unlock(&rdev->qp_lock);
1064         return qp;
1065 fail:
1066         kfree(qp);
1067         return NULL;
1068 }
1069
1070 struct ib_qp *bnxt_re_create_qp(struct ib_pd *ib_pd,
1071                                 struct ib_qp_init_attr *qp_init_attr,
1072                                 struct ib_udata *udata)
1073 {
1074         struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
1075         struct bnxt_re_dev *rdev = pd->rdev;
1076         struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
1077         struct bnxt_re_qp *qp;
1078         struct bnxt_re_cq *cq;
1079         int rc, entries;
1080
1081         if ((qp_init_attr->cap.max_send_wr > dev_attr->max_qp_wqes) ||
1082             (qp_init_attr->cap.max_recv_wr > dev_attr->max_qp_wqes) ||
1083             (qp_init_attr->cap.max_send_sge > dev_attr->max_qp_sges) ||
1084             (qp_init_attr->cap.max_recv_sge > dev_attr->max_qp_sges) ||
1085             (qp_init_attr->cap.max_inline_data > dev_attr->max_inline_data))
1086                 return ERR_PTR(-EINVAL);
1087
1088         qp = kzalloc(sizeof(*qp), GFP_KERNEL);
1089         if (!qp)
1090                 return ERR_PTR(-ENOMEM);
1091
1092         qp->rdev = rdev;
1093         ether_addr_copy(qp->qplib_qp.smac, rdev->netdev->dev_addr);
1094         qp->qplib_qp.pd = &pd->qplib_pd;
1095         qp->qplib_qp.qp_handle = (u64)(unsigned long)(&qp->qplib_qp);
1096         qp->qplib_qp.type = __from_ib_qp_type(qp_init_attr->qp_type);
1097         if (qp->qplib_qp.type == IB_QPT_MAX) {
1098                 dev_err(rdev_to_dev(rdev), "QP type 0x%x not supported",
1099                         qp->qplib_qp.type);
1100                 rc = -EINVAL;
1101                 goto fail;
1102         }
1103         qp->qplib_qp.max_inline_data = qp_init_attr->cap.max_inline_data;
1104         qp->qplib_qp.sig_type = ((qp_init_attr->sq_sig_type ==
1105                                   IB_SIGNAL_ALL_WR) ? true : false);
1106
1107         qp->qplib_qp.sq.max_sge = qp_init_attr->cap.max_send_sge;
1108         if (qp->qplib_qp.sq.max_sge > dev_attr->max_qp_sges)
1109                 qp->qplib_qp.sq.max_sge = dev_attr->max_qp_sges;
1110
1111         if (qp_init_attr->send_cq) {
1112                 cq = container_of(qp_init_attr->send_cq, struct bnxt_re_cq,
1113                                   ib_cq);
1114                 if (!cq) {
1115                         dev_err(rdev_to_dev(rdev), "Send CQ not found");
1116                         rc = -EINVAL;
1117                         goto fail;
1118                 }
1119                 qp->qplib_qp.scq = &cq->qplib_cq;
1120         }
1121
1122         if (qp_init_attr->recv_cq) {
1123                 cq = container_of(qp_init_attr->recv_cq, struct bnxt_re_cq,
1124                                   ib_cq);
1125                 if (!cq) {
1126                         dev_err(rdev_to_dev(rdev), "Receive CQ not found");
1127                         rc = -EINVAL;
1128                         goto fail;
1129                 }
1130                 qp->qplib_qp.rcq = &cq->qplib_cq;
1131         }
1132
1133         if (qp_init_attr->srq) {
1134                 dev_err(rdev_to_dev(rdev), "SRQ not supported");
1135                 rc = -ENOTSUPP;
1136                 goto fail;
1137         } else {
1138                 /* Allocate 1 more than what's provided so posting max doesn't
1139                  * mean empty
1140                  */
1141                 entries = roundup_pow_of_two(qp_init_attr->cap.max_recv_wr + 1);
1142                 qp->qplib_qp.rq.max_wqe = min_t(u32, entries,
1143                                                 dev_attr->max_qp_wqes + 1);
1144
1145                 qp->qplib_qp.rq.q_full_delta = qp->qplib_qp.rq.max_wqe -
1146                                                 qp_init_attr->cap.max_recv_wr;
1147
1148                 qp->qplib_qp.rq.max_sge = qp_init_attr->cap.max_recv_sge;
1149                 if (qp->qplib_qp.rq.max_sge > dev_attr->max_qp_sges)
1150                         qp->qplib_qp.rq.max_sge = dev_attr->max_qp_sges;
1151         }
1152
1153         qp->qplib_qp.mtu = ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu));
1154
1155         if (qp_init_attr->qp_type == IB_QPT_GSI) {
1156                 /* Allocate 1 more than what's provided */
1157                 entries = roundup_pow_of_two(qp_init_attr->cap.max_send_wr + 1);
1158                 qp->qplib_qp.sq.max_wqe = min_t(u32, entries,
1159                                                 dev_attr->max_qp_wqes + 1);
1160                 qp->qplib_qp.sq.q_full_delta = qp->qplib_qp.sq.max_wqe -
1161                                                 qp_init_attr->cap.max_send_wr;
1162                 qp->qplib_qp.rq.max_sge = dev_attr->max_qp_sges;
1163                 if (qp->qplib_qp.rq.max_sge > dev_attr->max_qp_sges)
1164                         qp->qplib_qp.rq.max_sge = dev_attr->max_qp_sges;
1165                 qp->qplib_qp.sq.max_sge++;
1166                 if (qp->qplib_qp.sq.max_sge > dev_attr->max_qp_sges)
1167                         qp->qplib_qp.sq.max_sge = dev_attr->max_qp_sges;
1168
1169                 qp->qplib_qp.rq_hdr_buf_size =
1170                                         BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2;
1171
1172                 qp->qplib_qp.sq_hdr_buf_size =
1173                                         BNXT_QPLIB_MAX_QP1_SQ_HDR_SIZE_V2;
1174                 qp->qplib_qp.dpi = &rdev->dpi_privileged;
1175                 rc = bnxt_qplib_create_qp1(&rdev->qplib_res, &qp->qplib_qp);
1176                 if (rc) {
1177                         dev_err(rdev_to_dev(rdev), "Failed to create HW QP1");
1178                         goto fail;
1179                 }
1180                 /* Create a shadow QP to handle the QP1 traffic */
1181                 rdev->qp1_sqp = bnxt_re_create_shadow_qp(pd, &rdev->qplib_res,
1182                                                          &qp->qplib_qp);
1183                 if (!rdev->qp1_sqp) {
1184                         rc = -EINVAL;
1185                         dev_err(rdev_to_dev(rdev),
1186                                 "Failed to create Shadow QP for QP1");
1187                         goto qp_destroy;
1188                 }
1189                 rdev->sqp_ah = bnxt_re_create_shadow_qp_ah(pd, &rdev->qplib_res,
1190                                                            &qp->qplib_qp);
1191                 if (!rdev->sqp_ah) {
1192                         bnxt_qplib_destroy_qp(&rdev->qplib_res,
1193                                               &rdev->qp1_sqp->qplib_qp);
1194                         rc = -EINVAL;
1195                         dev_err(rdev_to_dev(rdev),
1196                                 "Failed to create AH entry for ShadowQP");
1197                         goto qp_destroy;
1198                 }
1199
1200         } else {
1201                 /* Allocate 128 + 1 more than what's provided */
1202                 entries = roundup_pow_of_two(qp_init_attr->cap.max_send_wr +
1203                                              BNXT_QPLIB_RESERVED_QP_WRS + 1);
1204                 qp->qplib_qp.sq.max_wqe = min_t(u32, entries,
1205                                                 dev_attr->max_qp_wqes +
1206                                                 BNXT_QPLIB_RESERVED_QP_WRS + 1);
1207                 qp->qplib_qp.sq.q_full_delta = BNXT_QPLIB_RESERVED_QP_WRS + 1;
1208
1209                 /*
1210                  * Reserving one slot for Phantom WQE. Application can
1211                  * post one extra entry in this case. But allowing this to avoid
1212                  * unexpected Queue full condition
1213                  */
1214
1215                 qp->qplib_qp.sq.q_full_delta -= 1;
1216
1217                 qp->qplib_qp.max_rd_atomic = dev_attr->max_qp_rd_atom;
1218                 qp->qplib_qp.max_dest_rd_atomic = dev_attr->max_qp_init_rd_atom;
1219                 if (udata) {
1220                         rc = bnxt_re_init_user_qp(rdev, pd, qp, udata);
1221                         if (rc)
1222                                 goto fail;
1223                 } else {
1224                         qp->qplib_qp.dpi = &rdev->dpi_privileged;
1225                 }
1226
1227                 rc = bnxt_qplib_create_qp(&rdev->qplib_res, &qp->qplib_qp);
1228                 if (rc) {
1229                         dev_err(rdev_to_dev(rdev), "Failed to create HW QP");
1230                         goto fail;
1231                 }
1232         }
1233
1234         qp->ib_qp.qp_num = qp->qplib_qp.id;
1235         spin_lock_init(&qp->sq_lock);
1236         spin_lock_init(&qp->rq_lock);
1237
1238         if (udata) {
1239                 struct bnxt_re_qp_resp resp;
1240
1241                 resp.qpid = qp->ib_qp.qp_num;
1242                 resp.rsvd = 0;
1243                 rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
1244                 if (rc) {
1245                         dev_err(rdev_to_dev(rdev), "Failed to copy QP udata");
1246                         goto qp_destroy;
1247                 }
1248         }
1249         INIT_LIST_HEAD(&qp->list);
1250         mutex_lock(&rdev->qp_lock);
1251         list_add_tail(&qp->list, &rdev->qp_list);
1252         atomic_inc(&rdev->qp_count);
1253         mutex_unlock(&rdev->qp_lock);
1254
1255         return &qp->ib_qp;
1256 qp_destroy:
1257         bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp);
1258 fail:
1259         kfree(qp);
1260         return ERR_PTR(rc);
1261 }
1262
1263 static u8 __from_ib_qp_state(enum ib_qp_state state)
1264 {
1265         switch (state) {
1266         case IB_QPS_RESET:
1267                 return CMDQ_MODIFY_QP_NEW_STATE_RESET;
1268         case IB_QPS_INIT:
1269                 return CMDQ_MODIFY_QP_NEW_STATE_INIT;
1270         case IB_QPS_RTR:
1271                 return CMDQ_MODIFY_QP_NEW_STATE_RTR;
1272         case IB_QPS_RTS:
1273                 return CMDQ_MODIFY_QP_NEW_STATE_RTS;
1274         case IB_QPS_SQD:
1275                 return CMDQ_MODIFY_QP_NEW_STATE_SQD;
1276         case IB_QPS_SQE:
1277                 return CMDQ_MODIFY_QP_NEW_STATE_SQE;
1278         case IB_QPS_ERR:
1279         default:
1280                 return CMDQ_MODIFY_QP_NEW_STATE_ERR;
1281         }
1282 }
1283
1284 static enum ib_qp_state __to_ib_qp_state(u8 state)
1285 {
1286         switch (state) {
1287         case CMDQ_MODIFY_QP_NEW_STATE_RESET:
1288                 return IB_QPS_RESET;
1289         case CMDQ_MODIFY_QP_NEW_STATE_INIT:
1290                 return IB_QPS_INIT;
1291         case CMDQ_MODIFY_QP_NEW_STATE_RTR:
1292                 return IB_QPS_RTR;
1293         case CMDQ_MODIFY_QP_NEW_STATE_RTS:
1294                 return IB_QPS_RTS;
1295         case CMDQ_MODIFY_QP_NEW_STATE_SQD:
1296                 return IB_QPS_SQD;
1297         case CMDQ_MODIFY_QP_NEW_STATE_SQE:
1298                 return IB_QPS_SQE;
1299         case CMDQ_MODIFY_QP_NEW_STATE_ERR:
1300         default:
1301                 return IB_QPS_ERR;
1302         }
1303 }
1304
1305 static u32 __from_ib_mtu(enum ib_mtu mtu)
1306 {
1307         switch (mtu) {
1308         case IB_MTU_256:
1309                 return CMDQ_MODIFY_QP_PATH_MTU_MTU_256;
1310         case IB_MTU_512:
1311                 return CMDQ_MODIFY_QP_PATH_MTU_MTU_512;
1312         case IB_MTU_1024:
1313                 return CMDQ_MODIFY_QP_PATH_MTU_MTU_1024;
1314         case IB_MTU_2048:
1315                 return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048;
1316         case IB_MTU_4096:
1317                 return CMDQ_MODIFY_QP_PATH_MTU_MTU_4096;
1318         default:
1319                 return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048;
1320         }
1321 }
1322
1323 static enum ib_mtu __to_ib_mtu(u32 mtu)
1324 {
1325         switch (mtu & CREQ_QUERY_QP_RESP_SB_PATH_MTU_MASK) {
1326         case CMDQ_MODIFY_QP_PATH_MTU_MTU_256:
1327                 return IB_MTU_256;
1328         case CMDQ_MODIFY_QP_PATH_MTU_MTU_512:
1329                 return IB_MTU_512;
1330         case CMDQ_MODIFY_QP_PATH_MTU_MTU_1024:
1331                 return IB_MTU_1024;
1332         case CMDQ_MODIFY_QP_PATH_MTU_MTU_2048:
1333                 return IB_MTU_2048;
1334         case CMDQ_MODIFY_QP_PATH_MTU_MTU_4096:
1335                 return IB_MTU_4096;
1336         default:
1337                 return IB_MTU_2048;
1338         }
1339 }
1340
1341 static int bnxt_re_modify_shadow_qp(struct bnxt_re_dev *rdev,
1342                                     struct bnxt_re_qp *qp1_qp,
1343                                     int qp_attr_mask)
1344 {
1345         struct bnxt_re_qp *qp = rdev->qp1_sqp;
1346         int rc = 0;
1347
1348         if (qp_attr_mask & IB_QP_STATE) {
1349                 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE;
1350                 qp->qplib_qp.state = qp1_qp->qplib_qp.state;
1351         }
1352         if (qp_attr_mask & IB_QP_PKEY_INDEX) {
1353                 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY;
1354                 qp->qplib_qp.pkey_index = qp1_qp->qplib_qp.pkey_index;
1355         }
1356
1357         if (qp_attr_mask & IB_QP_QKEY) {
1358                 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY;
1359                 /* Using a Random  QKEY */
1360                 qp->qplib_qp.qkey = 0x81818181;
1361         }
1362         if (qp_attr_mask & IB_QP_SQ_PSN) {
1363                 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN;
1364                 qp->qplib_qp.sq.psn = qp1_qp->qplib_qp.sq.psn;
1365         }
1366
1367         rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp);
1368         if (rc)
1369                 dev_err(rdev_to_dev(rdev),
1370                         "Failed to modify Shadow QP for QP1");
1371         return rc;
1372 }
1373
1374 int bnxt_re_modify_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr,
1375                       int qp_attr_mask, struct ib_udata *udata)
1376 {
1377         struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
1378         struct bnxt_re_dev *rdev = qp->rdev;
1379         struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
1380         enum ib_qp_state curr_qp_state, new_qp_state;
1381         int rc, entries;
1382         int status;
1383         union ib_gid sgid;
1384         struct ib_gid_attr sgid_attr;
1385         u8 nw_type;
1386
1387         qp->qplib_qp.modify_flags = 0;
1388         if (qp_attr_mask & IB_QP_STATE) {
1389                 curr_qp_state = __to_ib_qp_state(qp->qplib_qp.cur_qp_state);
1390                 new_qp_state = qp_attr->qp_state;
1391                 if (!ib_modify_qp_is_ok(curr_qp_state, new_qp_state,
1392                                         ib_qp->qp_type, qp_attr_mask,
1393                                         IB_LINK_LAYER_ETHERNET)) {
1394                         dev_err(rdev_to_dev(rdev),
1395                                 "Invalid attribute mask: %#x specified ",
1396                                 qp_attr_mask);
1397                         dev_err(rdev_to_dev(rdev),
1398                                 "for qpn: %#x type: %#x",
1399                                 ib_qp->qp_num, ib_qp->qp_type);
1400                         dev_err(rdev_to_dev(rdev),
1401                                 "curr_qp_state=0x%x, new_qp_state=0x%x\n",
1402                                 curr_qp_state, new_qp_state);
1403                         return -EINVAL;
1404                 }
1405                 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE;
1406                 qp->qplib_qp.state = __from_ib_qp_state(qp_attr->qp_state);
1407         }
1408         if (qp_attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) {
1409                 qp->qplib_qp.modify_flags |=
1410                                 CMDQ_MODIFY_QP_MODIFY_MASK_EN_SQD_ASYNC_NOTIFY;
1411                 qp->qplib_qp.en_sqd_async_notify = true;
1412         }
1413         if (qp_attr_mask & IB_QP_ACCESS_FLAGS) {
1414                 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_ACCESS;
1415                 qp->qplib_qp.access =
1416                         __from_ib_access_flags(qp_attr->qp_access_flags);
1417                 /* LOCAL_WRITE access must be set to allow RC receive */
1418                 qp->qplib_qp.access |= BNXT_QPLIB_ACCESS_LOCAL_WRITE;
1419         }
1420         if (qp_attr_mask & IB_QP_PKEY_INDEX) {
1421                 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY;
1422                 qp->qplib_qp.pkey_index = qp_attr->pkey_index;
1423         }
1424         if (qp_attr_mask & IB_QP_QKEY) {
1425                 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY;
1426                 qp->qplib_qp.qkey = qp_attr->qkey;
1427         }
1428         if (qp_attr_mask & IB_QP_AV) {
1429                 const struct ib_global_route *grh =
1430                         rdma_ah_read_grh(&qp_attr->ah_attr);
1431
1432                 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_DGID |
1433                                      CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL |
1434                                      CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX |
1435                                      CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT |
1436                                      CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS |
1437                                      CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC |
1438                                      CMDQ_MODIFY_QP_MODIFY_MASK_VLAN_ID;
1439                 memcpy(qp->qplib_qp.ah.dgid.data, grh->dgid.raw,
1440                        sizeof(qp->qplib_qp.ah.dgid.data));
1441                 qp->qplib_qp.ah.flow_label = grh->flow_label;
1442                 /* If RoCE V2 is enabled, stack will have two entries for
1443                  * each GID entry. Avoiding this duplicte entry in HW. Dividing
1444                  * the GID index by 2 for RoCE V2
1445                  */
1446                 qp->qplib_qp.ah.sgid_index = grh->sgid_index / 2;
1447                 qp->qplib_qp.ah.host_sgid_index = grh->sgid_index;
1448                 qp->qplib_qp.ah.hop_limit = grh->hop_limit;
1449                 qp->qplib_qp.ah.traffic_class = grh->traffic_class;
1450                 qp->qplib_qp.ah.sl = rdma_ah_get_sl(&qp_attr->ah_attr);
1451                 ether_addr_copy(qp->qplib_qp.ah.dmac,
1452                                 qp_attr->ah_attr.roce.dmac);
1453
1454                 status = ib_get_cached_gid(&rdev->ibdev, 1,
1455                                            grh->sgid_index,
1456                                            &sgid, &sgid_attr);
1457                 if (!status && sgid_attr.ndev) {
1458                         memcpy(qp->qplib_qp.smac, sgid_attr.ndev->dev_addr,
1459                                ETH_ALEN);
1460                         dev_put(sgid_attr.ndev);
1461                         nw_type = ib_gid_to_network_type(sgid_attr.gid_type,
1462                                                          &sgid);
1463                         switch (nw_type) {
1464                         case RDMA_NETWORK_IPV4:
1465                                 qp->qplib_qp.nw_type =
1466                                         CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV4;
1467                                 break;
1468                         case RDMA_NETWORK_IPV6:
1469                                 qp->qplib_qp.nw_type =
1470                                         CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6;
1471                                 break;
1472                         default:
1473                                 qp->qplib_qp.nw_type =
1474                                         CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV1;
1475                                 break;
1476                         }
1477                 }
1478         }
1479
1480         if (qp_attr_mask & IB_QP_PATH_MTU) {
1481                 qp->qplib_qp.modify_flags |=
1482                                 CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU;
1483                 qp->qplib_qp.path_mtu = __from_ib_mtu(qp_attr->path_mtu);
1484         } else if (qp_attr->qp_state == IB_QPS_RTR) {
1485                 qp->qplib_qp.modify_flags |=
1486                         CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU;
1487                 qp->qplib_qp.path_mtu =
1488                         __from_ib_mtu(iboe_get_mtu(rdev->netdev->mtu));
1489         }
1490
1491         if (qp_attr_mask & IB_QP_TIMEOUT) {
1492                 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_TIMEOUT;
1493                 qp->qplib_qp.timeout = qp_attr->timeout;
1494         }
1495         if (qp_attr_mask & IB_QP_RETRY_CNT) {
1496                 qp->qplib_qp.modify_flags |=
1497                                 CMDQ_MODIFY_QP_MODIFY_MASK_RETRY_CNT;
1498                 qp->qplib_qp.retry_cnt = qp_attr->retry_cnt;
1499         }
1500         if (qp_attr_mask & IB_QP_RNR_RETRY) {
1501                 qp->qplib_qp.modify_flags |=
1502                                 CMDQ_MODIFY_QP_MODIFY_MASK_RNR_RETRY;
1503                 qp->qplib_qp.rnr_retry = qp_attr->rnr_retry;
1504         }
1505         if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) {
1506                 qp->qplib_qp.modify_flags |=
1507                                 CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER;
1508                 qp->qplib_qp.min_rnr_timer = qp_attr->min_rnr_timer;
1509         }
1510         if (qp_attr_mask & IB_QP_RQ_PSN) {
1511                 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN;
1512                 qp->qplib_qp.rq.psn = qp_attr->rq_psn;
1513         }
1514         if (qp_attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1515                 qp->qplib_qp.modify_flags |=
1516                                 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_RD_ATOMIC;
1517                 qp->qplib_qp.max_rd_atomic = qp_attr->max_rd_atomic;
1518         }
1519         if (qp_attr_mask & IB_QP_SQ_PSN) {
1520                 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN;
1521                 qp->qplib_qp.sq.psn = qp_attr->sq_psn;
1522         }
1523         if (qp_attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1524                 qp->qplib_qp.modify_flags |=
1525                                 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC;
1526                 qp->qplib_qp.max_dest_rd_atomic = qp_attr->max_dest_rd_atomic;
1527         }
1528         if (qp_attr_mask & IB_QP_CAP) {
1529                 qp->qplib_qp.modify_flags |=
1530                                 CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SIZE |
1531                                 CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SIZE |
1532                                 CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SGE |
1533                                 CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SGE |
1534                                 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_INLINE_DATA;
1535                 if ((qp_attr->cap.max_send_wr >= dev_attr->max_qp_wqes) ||
1536                     (qp_attr->cap.max_recv_wr >= dev_attr->max_qp_wqes) ||
1537                     (qp_attr->cap.max_send_sge >= dev_attr->max_qp_sges) ||
1538                     (qp_attr->cap.max_recv_sge >= dev_attr->max_qp_sges) ||
1539                     (qp_attr->cap.max_inline_data >=
1540                                                 dev_attr->max_inline_data)) {
1541                         dev_err(rdev_to_dev(rdev),
1542                                 "Create QP failed - max exceeded");
1543                         return -EINVAL;
1544                 }
1545                 entries = roundup_pow_of_two(qp_attr->cap.max_send_wr);
1546                 qp->qplib_qp.sq.max_wqe = min_t(u32, entries,
1547                                                 dev_attr->max_qp_wqes + 1);
1548                 qp->qplib_qp.sq.q_full_delta = qp->qplib_qp.sq.max_wqe -
1549                                                 qp_attr->cap.max_send_wr;
1550                 /*
1551                  * Reserving one slot for Phantom WQE. Some application can
1552                  * post one extra entry in this case. Allowing this to avoid
1553                  * unexpected Queue full condition
1554                  */
1555                 qp->qplib_qp.sq.q_full_delta -= 1;
1556                 qp->qplib_qp.sq.max_sge = qp_attr->cap.max_send_sge;
1557                 if (qp->qplib_qp.rq.max_wqe) {
1558                         entries = roundup_pow_of_two(qp_attr->cap.max_recv_wr);
1559                         qp->qplib_qp.rq.max_wqe =
1560                                 min_t(u32, entries, dev_attr->max_qp_wqes + 1);
1561                         qp->qplib_qp.rq.q_full_delta = qp->qplib_qp.rq.max_wqe -
1562                                                        qp_attr->cap.max_recv_wr;
1563                         qp->qplib_qp.rq.max_sge = qp_attr->cap.max_recv_sge;
1564                 } else {
1565                         /* SRQ was used prior, just ignore the RQ caps */
1566                 }
1567         }
1568         if (qp_attr_mask & IB_QP_DEST_QPN) {
1569                 qp->qplib_qp.modify_flags |=
1570                                 CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID;
1571                 qp->qplib_qp.dest_qpn = qp_attr->dest_qp_num;
1572         }
1573         rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp);
1574         if (rc) {
1575                 dev_err(rdev_to_dev(rdev), "Failed to modify HW QP");
1576                 return rc;
1577         }
1578         if (ib_qp->qp_type == IB_QPT_GSI && rdev->qp1_sqp)
1579                 rc = bnxt_re_modify_shadow_qp(rdev, qp, qp_attr_mask);
1580         return rc;
1581 }
1582
1583 int bnxt_re_query_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr,
1584                      int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
1585 {
1586         struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
1587         struct bnxt_re_dev *rdev = qp->rdev;
1588         struct bnxt_qplib_qp qplib_qp;
1589         int rc;
1590
1591         memset(&qplib_qp, 0, sizeof(struct bnxt_qplib_qp));
1592         qplib_qp.id = qp->qplib_qp.id;
1593         qplib_qp.ah.host_sgid_index = qp->qplib_qp.ah.host_sgid_index;
1594
1595         rc = bnxt_qplib_query_qp(&rdev->qplib_res, &qplib_qp);
1596         if (rc) {
1597                 dev_err(rdev_to_dev(rdev), "Failed to query HW QP");
1598                 return rc;
1599         }
1600         qp_attr->qp_state = __to_ib_qp_state(qplib_qp.state);
1601         qp_attr->en_sqd_async_notify = qplib_qp.en_sqd_async_notify ? 1 : 0;
1602         qp_attr->qp_access_flags = __to_ib_access_flags(qplib_qp.access);
1603         qp_attr->pkey_index = qplib_qp.pkey_index;
1604         qp_attr->qkey = qplib_qp.qkey;
1605         qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
1606         rdma_ah_set_grh(&qp_attr->ah_attr, NULL, qplib_qp.ah.flow_label,
1607                         qplib_qp.ah.host_sgid_index,
1608                         qplib_qp.ah.hop_limit,
1609                         qplib_qp.ah.traffic_class);
1610         rdma_ah_set_dgid_raw(&qp_attr->ah_attr, qplib_qp.ah.dgid.data);
1611         rdma_ah_set_sl(&qp_attr->ah_attr, qplib_qp.ah.sl);
1612         ether_addr_copy(qp_attr->ah_attr.roce.dmac, qplib_qp.ah.dmac);
1613         qp_attr->path_mtu = __to_ib_mtu(qplib_qp.path_mtu);
1614         qp_attr->timeout = qplib_qp.timeout;
1615         qp_attr->retry_cnt = qplib_qp.retry_cnt;
1616         qp_attr->rnr_retry = qplib_qp.rnr_retry;
1617         qp_attr->min_rnr_timer = qplib_qp.min_rnr_timer;
1618         qp_attr->rq_psn = qplib_qp.rq.psn;
1619         qp_attr->max_rd_atomic = qplib_qp.max_rd_atomic;
1620         qp_attr->sq_psn = qplib_qp.sq.psn;
1621         qp_attr->max_dest_rd_atomic = qplib_qp.max_dest_rd_atomic;
1622         qp_init_attr->sq_sig_type = qplib_qp.sig_type ? IB_SIGNAL_ALL_WR :
1623                                                         IB_SIGNAL_REQ_WR;
1624         qp_attr->dest_qp_num = qplib_qp.dest_qpn;
1625
1626         qp_attr->cap.max_send_wr = qp->qplib_qp.sq.max_wqe;
1627         qp_attr->cap.max_send_sge = qp->qplib_qp.sq.max_sge;
1628         qp_attr->cap.max_recv_wr = qp->qplib_qp.rq.max_wqe;
1629         qp_attr->cap.max_recv_sge = qp->qplib_qp.rq.max_sge;
1630         qp_attr->cap.max_inline_data = qp->qplib_qp.max_inline_data;
1631         qp_init_attr->cap = qp_attr->cap;
1632
1633         return 0;
1634 }
1635
1636 /* Routine for sending QP1 packets for RoCE V1 an V2
1637  */
1638 static int bnxt_re_build_qp1_send_v2(struct bnxt_re_qp *qp,
1639                                      struct ib_send_wr *wr,
1640                                      struct bnxt_qplib_swqe *wqe,
1641                                      int payload_size)
1642 {
1643         struct ib_device *ibdev = &qp->rdev->ibdev;
1644         struct bnxt_re_ah *ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah,
1645                                              ib_ah);
1646         struct bnxt_qplib_ah *qplib_ah = &ah->qplib_ah;
1647         struct bnxt_qplib_sge sge;
1648         union ib_gid sgid;
1649         u8 nw_type;
1650         u16 ether_type;
1651         struct ib_gid_attr sgid_attr;
1652         union ib_gid dgid;
1653         bool is_eth = false;
1654         bool is_vlan = false;
1655         bool is_grh = false;
1656         bool is_udp = false;
1657         u8 ip_version = 0;
1658         u16 vlan_id = 0xFFFF;
1659         void *buf;
1660         int i, rc = 0, size;
1661
1662         memset(&qp->qp1_hdr, 0, sizeof(qp->qp1_hdr));
1663
1664         rc = ib_get_cached_gid(ibdev, 1,
1665                                qplib_ah->host_sgid_index, &sgid,
1666                                &sgid_attr);
1667         if (rc) {
1668                 dev_err(rdev_to_dev(qp->rdev),
1669                         "Failed to query gid at index %d",
1670                         qplib_ah->host_sgid_index);
1671                 return rc;
1672         }
1673         if (sgid_attr.ndev) {
1674                 if (is_vlan_dev(sgid_attr.ndev))
1675                         vlan_id = vlan_dev_vlan_id(sgid_attr.ndev);
1676                 dev_put(sgid_attr.ndev);
1677         }
1678         /* Get network header type for this GID */
1679         nw_type = ib_gid_to_network_type(sgid_attr.gid_type, &sgid);
1680         switch (nw_type) {
1681         case RDMA_NETWORK_IPV4:
1682                 nw_type = BNXT_RE_ROCEV2_IPV4_PACKET;
1683                 break;
1684         case RDMA_NETWORK_IPV6:
1685                 nw_type = BNXT_RE_ROCEV2_IPV6_PACKET;
1686                 break;
1687         default:
1688                 nw_type = BNXT_RE_ROCE_V1_PACKET;
1689                 break;
1690         }
1691         memcpy(&dgid.raw, &qplib_ah->dgid, 16);
1692         is_udp = sgid_attr.gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP;
1693         if (is_udp) {
1694                 if (ipv6_addr_v4mapped((struct in6_addr *)&sgid)) {
1695                         ip_version = 4;
1696                         ether_type = ETH_P_IP;
1697                 } else {
1698                         ip_version = 6;
1699                         ether_type = ETH_P_IPV6;
1700                 }
1701                 is_grh = false;
1702         } else {
1703                 ether_type = ETH_P_IBOE;
1704                 is_grh = true;
1705         }
1706
1707         is_eth = true;
1708         is_vlan = (vlan_id && (vlan_id < 0x1000)) ? true : false;
1709
1710         ib_ud_header_init(payload_size, !is_eth, is_eth, is_vlan, is_grh,
1711                           ip_version, is_udp, 0, &qp->qp1_hdr);
1712
1713         /* ETH */
1714         ether_addr_copy(qp->qp1_hdr.eth.dmac_h, ah->qplib_ah.dmac);
1715         ether_addr_copy(qp->qp1_hdr.eth.smac_h, qp->qplib_qp.smac);
1716
1717         /* For vlan, check the sgid for vlan existence */
1718
1719         if (!is_vlan) {
1720                 qp->qp1_hdr.eth.type = cpu_to_be16(ether_type);
1721         } else {
1722                 qp->qp1_hdr.vlan.type = cpu_to_be16(ether_type);
1723                 qp->qp1_hdr.vlan.tag = cpu_to_be16(vlan_id);
1724         }
1725
1726         if (is_grh || (ip_version == 6)) {
1727                 memcpy(qp->qp1_hdr.grh.source_gid.raw, sgid.raw, sizeof(sgid));
1728                 memcpy(qp->qp1_hdr.grh.destination_gid.raw, qplib_ah->dgid.data,
1729                        sizeof(sgid));
1730                 qp->qp1_hdr.grh.hop_limit     = qplib_ah->hop_limit;
1731         }
1732
1733         if (ip_version == 4) {
1734                 qp->qp1_hdr.ip4.tos = 0;
1735                 qp->qp1_hdr.ip4.id = 0;
1736                 qp->qp1_hdr.ip4.frag_off = htons(IP_DF);
1737                 qp->qp1_hdr.ip4.ttl = qplib_ah->hop_limit;
1738
1739                 memcpy(&qp->qp1_hdr.ip4.saddr, sgid.raw + 12, 4);
1740                 memcpy(&qp->qp1_hdr.ip4.daddr, qplib_ah->dgid.data + 12, 4);
1741                 qp->qp1_hdr.ip4.check = ib_ud_ip4_csum(&qp->qp1_hdr);
1742         }
1743
1744         if (is_udp) {
1745                 qp->qp1_hdr.udp.dport = htons(ROCE_V2_UDP_DPORT);
1746                 qp->qp1_hdr.udp.sport = htons(0x8CD1);
1747                 qp->qp1_hdr.udp.csum = 0;
1748         }
1749
1750         /* BTH */
1751         if (wr->opcode == IB_WR_SEND_WITH_IMM) {
1752                 qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1753                 qp->qp1_hdr.immediate_present = 1;
1754         } else {
1755                 qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
1756         }
1757         if (wr->send_flags & IB_SEND_SOLICITED)
1758                 qp->qp1_hdr.bth.solicited_event = 1;
1759         /* pad_count */
1760         qp->qp1_hdr.bth.pad_count = (4 - payload_size) & 3;
1761
1762         /* P_key for QP1 is for all members */
1763         qp->qp1_hdr.bth.pkey = cpu_to_be16(0xFFFF);
1764         qp->qp1_hdr.bth.destination_qpn = IB_QP1;
1765         qp->qp1_hdr.bth.ack_req = 0;
1766         qp->send_psn++;
1767         qp->send_psn &= BTH_PSN_MASK;
1768         qp->qp1_hdr.bth.psn = cpu_to_be32(qp->send_psn);
1769         /* DETH */
1770         /* Use the priviledged Q_Key for QP1 */
1771         qp->qp1_hdr.deth.qkey = cpu_to_be32(IB_QP1_QKEY);
1772         qp->qp1_hdr.deth.source_qpn = IB_QP1;
1773
1774         /* Pack the QP1 to the transmit buffer */
1775         buf = bnxt_qplib_get_qp1_sq_buf(&qp->qplib_qp, &sge);
1776         if (buf) {
1777                 size = ib_ud_header_pack(&qp->qp1_hdr, buf);
1778                 for (i = wqe->num_sge; i; i--) {
1779                         wqe->sg_list[i].addr = wqe->sg_list[i - 1].addr;
1780                         wqe->sg_list[i].lkey = wqe->sg_list[i - 1].lkey;
1781                         wqe->sg_list[i].size = wqe->sg_list[i - 1].size;
1782                 }
1783
1784                 /*
1785                  * Max Header buf size for IPV6 RoCE V2 is 86,
1786                  * which is same as the QP1 SQ header buffer.
1787                  * Header buf size for IPV4 RoCE V2 can be 66.
1788                  * ETH(14) + VLAN(4)+ IP(20) + UDP (8) + BTH(20).
1789                  * Subtract 20 bytes from QP1 SQ header buf size
1790                  */
1791                 if (is_udp && ip_version == 4)
1792                         sge.size -= 20;
1793                 /*
1794                  * Max Header buf size for RoCE V1 is 78.
1795                  * ETH(14) + VLAN(4) + GRH(40) + BTH(20).
1796                  * Subtract 8 bytes from QP1 SQ header buf size
1797                  */
1798                 if (!is_udp)
1799                         sge.size -= 8;
1800
1801                 /* Subtract 4 bytes for non vlan packets */
1802                 if (!is_vlan)
1803                         sge.size -= 4;
1804
1805                 wqe->sg_list[0].addr = sge.addr;
1806                 wqe->sg_list[0].lkey = sge.lkey;
1807                 wqe->sg_list[0].size = sge.size;
1808                 wqe->num_sge++;
1809
1810         } else {
1811                 dev_err(rdev_to_dev(qp->rdev), "QP1 buffer is empty!");
1812                 rc = -ENOMEM;
1813         }
1814         return rc;
1815 }
1816
1817 /* For the MAD layer, it only provides the recv SGE the size of
1818  * ib_grh + MAD datagram.  No Ethernet headers, Ethertype, BTH, DETH,
1819  * nor RoCE iCRC.  The Cu+ solution must provide buffer for the entire
1820  * receive packet (334 bytes) with no VLAN and then copy the GRH
1821  * and the MAD datagram out to the provided SGE.
1822  */
1823 static int bnxt_re_build_qp1_shadow_qp_recv(struct bnxt_re_qp *qp,
1824                                             struct ib_recv_wr *wr,
1825                                             struct bnxt_qplib_swqe *wqe,
1826                                             int payload_size)
1827 {
1828         struct bnxt_qplib_sge ref, sge;
1829         u32 rq_prod_index;
1830         struct bnxt_re_sqp_entries *sqp_entry;
1831
1832         rq_prod_index = bnxt_qplib_get_rq_prod_index(&qp->qplib_qp);
1833
1834         if (!bnxt_qplib_get_qp1_rq_buf(&qp->qplib_qp, &sge))
1835                 return -ENOMEM;
1836
1837         /* Create 1 SGE to receive the entire
1838          * ethernet packet
1839          */
1840         /* Save the reference from ULP */
1841         ref.addr = wqe->sg_list[0].addr;
1842         ref.lkey = wqe->sg_list[0].lkey;
1843         ref.size = wqe->sg_list[0].size;
1844
1845         sqp_entry = &qp->rdev->sqp_tbl[rq_prod_index];
1846
1847         /* SGE 1 */
1848         wqe->sg_list[0].addr = sge.addr;
1849         wqe->sg_list[0].lkey = sge.lkey;
1850         wqe->sg_list[0].size = BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2;
1851         sge.size -= wqe->sg_list[0].size;
1852
1853         sqp_entry->sge.addr = ref.addr;
1854         sqp_entry->sge.lkey = ref.lkey;
1855         sqp_entry->sge.size = ref.size;
1856         /* Store the wrid for reporting completion */
1857         sqp_entry->wrid = wqe->wr_id;
1858         /* change the wqe->wrid to table index */
1859         wqe->wr_id = rq_prod_index;
1860         return 0;
1861 }
1862
1863 static int is_ud_qp(struct bnxt_re_qp *qp)
1864 {
1865         return qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_UD;
1866 }
1867
1868 static int bnxt_re_build_send_wqe(struct bnxt_re_qp *qp,
1869                                   struct ib_send_wr *wr,
1870                                   struct bnxt_qplib_swqe *wqe)
1871 {
1872         struct bnxt_re_ah *ah = NULL;
1873
1874         if (is_ud_qp(qp)) {
1875                 ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah, ib_ah);
1876                 wqe->send.q_key = ud_wr(wr)->remote_qkey;
1877                 wqe->send.dst_qp = ud_wr(wr)->remote_qpn;
1878                 wqe->send.avid = ah->qplib_ah.id;
1879         }
1880         switch (wr->opcode) {
1881         case IB_WR_SEND:
1882                 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND;
1883                 break;
1884         case IB_WR_SEND_WITH_IMM:
1885                 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM;
1886                 wqe->send.imm_data = wr->ex.imm_data;
1887                 break;
1888         case IB_WR_SEND_WITH_INV:
1889                 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV;
1890                 wqe->send.inv_key = wr->ex.invalidate_rkey;
1891                 break;
1892         default:
1893                 return -EINVAL;
1894         }
1895         if (wr->send_flags & IB_SEND_SIGNALED)
1896                 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
1897         if (wr->send_flags & IB_SEND_FENCE)
1898                 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
1899         if (wr->send_flags & IB_SEND_SOLICITED)
1900                 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
1901         if (wr->send_flags & IB_SEND_INLINE)
1902                 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE;
1903
1904         return 0;
1905 }
1906
1907 static int bnxt_re_build_rdma_wqe(struct ib_send_wr *wr,
1908                                   struct bnxt_qplib_swqe *wqe)
1909 {
1910         switch (wr->opcode) {
1911         case IB_WR_RDMA_WRITE:
1912                 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE;
1913                 break;
1914         case IB_WR_RDMA_WRITE_WITH_IMM:
1915                 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM;
1916                 wqe->rdma.imm_data = wr->ex.imm_data;
1917                 break;
1918         case IB_WR_RDMA_READ:
1919                 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_READ;
1920                 wqe->rdma.inv_key = wr->ex.invalidate_rkey;
1921                 break;
1922         default:
1923                 return -EINVAL;
1924         }
1925         wqe->rdma.remote_va = rdma_wr(wr)->remote_addr;
1926         wqe->rdma.r_key = rdma_wr(wr)->rkey;
1927         if (wr->send_flags & IB_SEND_SIGNALED)
1928                 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
1929         if (wr->send_flags & IB_SEND_FENCE)
1930                 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
1931         if (wr->send_flags & IB_SEND_SOLICITED)
1932                 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
1933         if (wr->send_flags & IB_SEND_INLINE)
1934                 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE;
1935
1936         return 0;
1937 }
1938
1939 static int bnxt_re_build_atomic_wqe(struct ib_send_wr *wr,
1940                                     struct bnxt_qplib_swqe *wqe)
1941 {
1942         switch (wr->opcode) {
1943         case IB_WR_ATOMIC_CMP_AND_SWP:
1944                 wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP;
1945                 wqe->atomic.swap_data = atomic_wr(wr)->swap;
1946                 break;
1947         case IB_WR_ATOMIC_FETCH_AND_ADD:
1948                 wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD;
1949                 wqe->atomic.cmp_data = atomic_wr(wr)->compare_add;
1950                 break;
1951         default:
1952                 return -EINVAL;
1953         }
1954         wqe->atomic.remote_va = atomic_wr(wr)->remote_addr;
1955         wqe->atomic.r_key = atomic_wr(wr)->rkey;
1956         if (wr->send_flags & IB_SEND_SIGNALED)
1957                 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
1958         if (wr->send_flags & IB_SEND_FENCE)
1959                 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
1960         if (wr->send_flags & IB_SEND_SOLICITED)
1961                 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
1962         return 0;
1963 }
1964
1965 static int bnxt_re_build_inv_wqe(struct ib_send_wr *wr,
1966                                  struct bnxt_qplib_swqe *wqe)
1967 {
1968         wqe->type = BNXT_QPLIB_SWQE_TYPE_LOCAL_INV;
1969         wqe->local_inv.inv_l_key = wr->ex.invalidate_rkey;
1970
1971         if (wr->send_flags & IB_SEND_SIGNALED)
1972                 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
1973         if (wr->send_flags & IB_SEND_FENCE)
1974                 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
1975         if (wr->send_flags & IB_SEND_SOLICITED)
1976                 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
1977
1978         return 0;
1979 }
1980
1981 static int bnxt_re_build_reg_wqe(struct ib_reg_wr *wr,
1982                                  struct bnxt_qplib_swqe *wqe)
1983 {
1984         struct bnxt_re_mr *mr = container_of(wr->mr, struct bnxt_re_mr, ib_mr);
1985         struct bnxt_qplib_frpl *qplib_frpl = &mr->qplib_frpl;
1986         int access = wr->access;
1987
1988         wqe->frmr.pbl_ptr = (__le64 *)qplib_frpl->hwq.pbl_ptr[0];
1989         wqe->frmr.pbl_dma_ptr = qplib_frpl->hwq.pbl_dma_ptr[0];
1990         wqe->frmr.page_list = mr->pages;
1991         wqe->frmr.page_list_len = mr->npages;
1992         wqe->frmr.levels = qplib_frpl->hwq.level + 1;
1993         wqe->type = BNXT_QPLIB_SWQE_TYPE_REG_MR;
1994
1995         if (wr->wr.send_flags & IB_SEND_FENCE)
1996                 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
1997         if (wr->wr.send_flags & IB_SEND_SIGNALED)
1998                 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
1999
2000         if (access & IB_ACCESS_LOCAL_WRITE)
2001                 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_LOCAL_WRITE;
2002         if (access & IB_ACCESS_REMOTE_READ)
2003                 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_READ;
2004         if (access & IB_ACCESS_REMOTE_WRITE)
2005                 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_WRITE;
2006         if (access & IB_ACCESS_REMOTE_ATOMIC)
2007                 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_ATOMIC;
2008         if (access & IB_ACCESS_MW_BIND)
2009                 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_WINDOW_BIND;
2010
2011         wqe->frmr.l_key = wr->key;
2012         wqe->frmr.length = wr->mr->length;
2013         wqe->frmr.pbl_pg_sz_log = (wr->mr->page_size >> PAGE_SHIFT_4K) - 1;
2014         wqe->frmr.va = wr->mr->iova;
2015         return 0;
2016 }
2017
2018 static int bnxt_re_copy_inline_data(struct bnxt_re_dev *rdev,
2019                                     struct ib_send_wr *wr,
2020                                     struct bnxt_qplib_swqe *wqe)
2021 {
2022         /*  Copy the inline data to the data  field */
2023         u8 *in_data;
2024         u32 i, sge_len;
2025         void *sge_addr;
2026
2027         in_data = wqe->inline_data;
2028         for (i = 0; i < wr->num_sge; i++) {
2029                 sge_addr = (void *)(unsigned long)
2030                                 wr->sg_list[i].addr;
2031                 sge_len = wr->sg_list[i].length;
2032
2033                 if ((sge_len + wqe->inline_len) >
2034                     BNXT_QPLIB_SWQE_MAX_INLINE_LENGTH) {
2035                         dev_err(rdev_to_dev(rdev),
2036                                 "Inline data size requested > supported value");
2037                         return -EINVAL;
2038                 }
2039                 sge_len = wr->sg_list[i].length;
2040
2041                 memcpy(in_data, sge_addr, sge_len);
2042                 in_data += wr->sg_list[i].length;
2043                 wqe->inline_len += wr->sg_list[i].length;
2044         }
2045         return wqe->inline_len;
2046 }
2047
2048 static int bnxt_re_copy_wr_payload(struct bnxt_re_dev *rdev,
2049                                    struct ib_send_wr *wr,
2050                                    struct bnxt_qplib_swqe *wqe)
2051 {
2052         int payload_sz = 0;
2053
2054         if (wr->send_flags & IB_SEND_INLINE)
2055                 payload_sz = bnxt_re_copy_inline_data(rdev, wr, wqe);
2056         else
2057                 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe->sg_list,
2058                                                wqe->num_sge);
2059
2060         return payload_sz;
2061 }
2062
2063 static void bnxt_ud_qp_hw_stall_workaround(struct bnxt_re_qp *qp)
2064 {
2065         if ((qp->ib_qp.qp_type == IB_QPT_UD ||
2066              qp->ib_qp.qp_type == IB_QPT_GSI ||
2067              qp->ib_qp.qp_type == IB_QPT_RAW_ETHERTYPE) &&
2068              qp->qplib_qp.wqe_cnt == BNXT_RE_UD_QP_HW_STALL) {
2069                 int qp_attr_mask;
2070                 struct ib_qp_attr qp_attr;
2071
2072                 qp_attr_mask = IB_QP_STATE;
2073                 qp_attr.qp_state = IB_QPS_RTS;
2074                 bnxt_re_modify_qp(&qp->ib_qp, &qp_attr, qp_attr_mask, NULL);
2075                 qp->qplib_qp.wqe_cnt = 0;
2076         }
2077 }
2078
2079 static int bnxt_re_post_send_shadow_qp(struct bnxt_re_dev *rdev,
2080                                        struct bnxt_re_qp *qp,
2081                                 struct ib_send_wr *wr)
2082 {
2083         struct bnxt_qplib_swqe wqe;
2084         int rc = 0, payload_sz = 0;
2085         unsigned long flags;
2086
2087         spin_lock_irqsave(&qp->sq_lock, flags);
2088         memset(&wqe, 0, sizeof(wqe));
2089         while (wr) {
2090                 /* House keeping */
2091                 memset(&wqe, 0, sizeof(wqe));
2092
2093                 /* Common */
2094                 wqe.num_sge = wr->num_sge;
2095                 if (wr->num_sge > qp->qplib_qp.sq.max_sge) {
2096                         dev_err(rdev_to_dev(rdev),
2097                                 "Limit exceeded for Send SGEs");
2098                         rc = -EINVAL;
2099                         goto bad;
2100                 }
2101
2102                 payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe);
2103                 if (payload_sz < 0) {
2104                         rc = -EINVAL;
2105                         goto bad;
2106                 }
2107                 wqe.wr_id = wr->wr_id;
2108
2109                 wqe.type = BNXT_QPLIB_SWQE_TYPE_SEND;
2110
2111                 rc = bnxt_re_build_send_wqe(qp, wr, &wqe);
2112                 if (!rc)
2113                         rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe);
2114 bad:
2115                 if (rc) {
2116                         dev_err(rdev_to_dev(rdev),
2117                                 "Post send failed opcode = %#x rc = %d",
2118                                 wr->opcode, rc);
2119                         break;
2120                 }
2121                 wr = wr->next;
2122         }
2123         bnxt_qplib_post_send_db(&qp->qplib_qp);
2124         bnxt_ud_qp_hw_stall_workaround(qp);
2125         spin_unlock_irqrestore(&qp->sq_lock, flags);
2126         return rc;
2127 }
2128
2129 int bnxt_re_post_send(struct ib_qp *ib_qp, struct ib_send_wr *wr,
2130                       struct ib_send_wr **bad_wr)
2131 {
2132         struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
2133         struct bnxt_qplib_swqe wqe;
2134         int rc = 0, payload_sz = 0;
2135         unsigned long flags;
2136
2137         spin_lock_irqsave(&qp->sq_lock, flags);
2138         while (wr) {
2139                 /* House keeping */
2140                 memset(&wqe, 0, sizeof(wqe));
2141
2142                 /* Common */
2143                 wqe.num_sge = wr->num_sge;
2144                 if (wr->num_sge > qp->qplib_qp.sq.max_sge) {
2145                         dev_err(rdev_to_dev(qp->rdev),
2146                                 "Limit exceeded for Send SGEs");
2147                         rc = -EINVAL;
2148                         goto bad;
2149                 }
2150
2151                 payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe);
2152                 if (payload_sz < 0) {
2153                         rc = -EINVAL;
2154                         goto bad;
2155                 }
2156                 wqe.wr_id = wr->wr_id;
2157
2158                 switch (wr->opcode) {
2159                 case IB_WR_SEND:
2160                 case IB_WR_SEND_WITH_IMM:
2161                         if (ib_qp->qp_type == IB_QPT_GSI) {
2162                                 rc = bnxt_re_build_qp1_send_v2(qp, wr, &wqe,
2163                                                                payload_sz);
2164                                 if (rc)
2165                                         goto bad;
2166                                 wqe.rawqp1.lflags |=
2167                                         SQ_SEND_RAWETH_QP1_LFLAGS_ROCE_CRC;
2168                         }
2169                         switch (wr->send_flags) {
2170                         case IB_SEND_IP_CSUM:
2171                                 wqe.rawqp1.lflags |=
2172                                         SQ_SEND_RAWETH_QP1_LFLAGS_IP_CHKSUM;
2173                                 break;
2174                         default:
2175                                 break;
2176                         }
2177                         /* Fall thru to build the wqe */
2178                 case IB_WR_SEND_WITH_INV:
2179                         rc = bnxt_re_build_send_wqe(qp, wr, &wqe);
2180                         break;
2181                 case IB_WR_RDMA_WRITE:
2182                 case IB_WR_RDMA_WRITE_WITH_IMM:
2183                 case IB_WR_RDMA_READ:
2184                         rc = bnxt_re_build_rdma_wqe(wr, &wqe);
2185                         break;
2186                 case IB_WR_ATOMIC_CMP_AND_SWP:
2187                 case IB_WR_ATOMIC_FETCH_AND_ADD:
2188                         rc = bnxt_re_build_atomic_wqe(wr, &wqe);
2189                         break;
2190                 case IB_WR_RDMA_READ_WITH_INV:
2191                         dev_err(rdev_to_dev(qp->rdev),
2192                                 "RDMA Read with Invalidate is not supported");
2193                         rc = -EINVAL;
2194                         goto bad;
2195                 case IB_WR_LOCAL_INV:
2196                         rc = bnxt_re_build_inv_wqe(wr, &wqe);
2197                         break;
2198                 case IB_WR_REG_MR:
2199                         rc = bnxt_re_build_reg_wqe(reg_wr(wr), &wqe);
2200                         break;
2201                 default:
2202                         /* Unsupported WRs */
2203                         dev_err(rdev_to_dev(qp->rdev),
2204                                 "WR (%#x) is not supported", wr->opcode);
2205                         rc = -EINVAL;
2206                         goto bad;
2207                 }
2208                 if (!rc)
2209                         rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe);
2210 bad:
2211                 if (rc) {
2212                         dev_err(rdev_to_dev(qp->rdev),
2213                                 "post_send failed op:%#x qps = %#x rc = %d\n",
2214                                 wr->opcode, qp->qplib_qp.state, rc);
2215                         *bad_wr = wr;
2216                         break;
2217                 }
2218                 wr = wr->next;
2219         }
2220         bnxt_qplib_post_send_db(&qp->qplib_qp);
2221         bnxt_ud_qp_hw_stall_workaround(qp);
2222         spin_unlock_irqrestore(&qp->sq_lock, flags);
2223
2224         return rc;
2225 }
2226
2227 static int bnxt_re_post_recv_shadow_qp(struct bnxt_re_dev *rdev,
2228                                        struct bnxt_re_qp *qp,
2229                                        struct ib_recv_wr *wr)
2230 {
2231         struct bnxt_qplib_swqe wqe;
2232         int rc = 0, payload_sz = 0;
2233
2234         memset(&wqe, 0, sizeof(wqe));
2235         while (wr) {
2236                 /* House keeping */
2237                 memset(&wqe, 0, sizeof(wqe));
2238
2239                 /* Common */
2240                 wqe.num_sge = wr->num_sge;
2241                 if (wr->num_sge > qp->qplib_qp.rq.max_sge) {
2242                         dev_err(rdev_to_dev(rdev),
2243                                 "Limit exceeded for Receive SGEs");
2244                         rc = -EINVAL;
2245                         break;
2246                 }
2247                 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe.sg_list,
2248                                                wr->num_sge);
2249                 wqe.wr_id = wr->wr_id;
2250                 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV;
2251
2252                 rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe);
2253                 if (rc)
2254                         break;
2255
2256                 wr = wr->next;
2257         }
2258         if (!rc)
2259                 bnxt_qplib_post_recv_db(&qp->qplib_qp);
2260         return rc;
2261 }
2262
2263 int bnxt_re_post_recv(struct ib_qp *ib_qp, struct ib_recv_wr *wr,
2264                       struct ib_recv_wr **bad_wr)
2265 {
2266         struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
2267         struct bnxt_qplib_swqe wqe;
2268         int rc = 0, payload_sz = 0;
2269         unsigned long flags;
2270         u32 count = 0;
2271
2272         spin_lock_irqsave(&qp->rq_lock, flags);
2273         while (wr) {
2274                 /* House keeping */
2275                 memset(&wqe, 0, sizeof(wqe));
2276
2277                 /* Common */
2278                 wqe.num_sge = wr->num_sge;
2279                 if (wr->num_sge > qp->qplib_qp.rq.max_sge) {
2280                         dev_err(rdev_to_dev(qp->rdev),
2281                                 "Limit exceeded for Receive SGEs");
2282                         rc = -EINVAL;
2283                         *bad_wr = wr;
2284                         break;
2285                 }
2286
2287                 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe.sg_list,
2288                                                wr->num_sge);
2289                 wqe.wr_id = wr->wr_id;
2290                 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV;
2291
2292                 if (ib_qp->qp_type == IB_QPT_GSI)
2293                         rc = bnxt_re_build_qp1_shadow_qp_recv(qp, wr, &wqe,
2294                                                               payload_sz);
2295                 if (!rc)
2296                         rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe);
2297                 if (rc) {
2298                         *bad_wr = wr;
2299                         break;
2300                 }
2301
2302                 /* Ring DB if the RQEs posted reaches a threshold value */
2303                 if (++count >= BNXT_RE_RQ_WQE_THRESHOLD) {
2304                         bnxt_qplib_post_recv_db(&qp->qplib_qp);
2305                         count = 0;
2306                 }
2307
2308                 wr = wr->next;
2309         }
2310
2311         if (count)
2312                 bnxt_qplib_post_recv_db(&qp->qplib_qp);
2313
2314         spin_unlock_irqrestore(&qp->rq_lock, flags);
2315
2316         return rc;
2317 }
2318
2319 /* Completion Queues */
2320 int bnxt_re_destroy_cq(struct ib_cq *ib_cq)
2321 {
2322         struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
2323         struct bnxt_re_dev *rdev = cq->rdev;
2324         int rc;
2325
2326         rc = bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq);
2327         if (rc) {
2328                 dev_err(rdev_to_dev(rdev), "Failed to destroy HW CQ");
2329                 return rc;
2330         }
2331         if (!IS_ERR_OR_NULL(cq->umem))
2332                 ib_umem_release(cq->umem);
2333
2334         if (cq) {
2335                 kfree(cq->cql);
2336                 kfree(cq);
2337         }
2338         atomic_dec(&rdev->cq_count);
2339         rdev->nq.budget--;
2340         return 0;
2341 }
2342
2343 struct ib_cq *bnxt_re_create_cq(struct ib_device *ibdev,
2344                                 const struct ib_cq_init_attr *attr,
2345                                 struct ib_ucontext *context,
2346                                 struct ib_udata *udata)
2347 {
2348         struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
2349         struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
2350         struct bnxt_re_cq *cq = NULL;
2351         int rc, entries;
2352         int cqe = attr->cqe;
2353
2354         /* Validate CQ fields */
2355         if (cqe < 1 || cqe > dev_attr->max_cq_wqes) {
2356                 dev_err(rdev_to_dev(rdev), "Failed to create CQ -max exceeded");
2357                 return ERR_PTR(-EINVAL);
2358         }
2359         cq = kzalloc(sizeof(*cq), GFP_KERNEL);
2360         if (!cq)
2361                 return ERR_PTR(-ENOMEM);
2362
2363         cq->rdev = rdev;
2364         cq->qplib_cq.cq_handle = (u64)(unsigned long)(&cq->qplib_cq);
2365
2366         entries = roundup_pow_of_two(cqe + 1);
2367         if (entries > dev_attr->max_cq_wqes + 1)
2368                 entries = dev_attr->max_cq_wqes + 1;
2369
2370         if (context) {
2371                 struct bnxt_re_cq_req req;
2372                 struct bnxt_re_ucontext *uctx = container_of
2373                                                 (context,
2374                                                  struct bnxt_re_ucontext,
2375                                                  ib_uctx);
2376                 if (ib_copy_from_udata(&req, udata, sizeof(req))) {
2377                         rc = -EFAULT;
2378                         goto fail;
2379                 }
2380
2381                 cq->umem = ib_umem_get(context, req.cq_va,
2382                                        entries * sizeof(struct cq_base),
2383                                        IB_ACCESS_LOCAL_WRITE, 1);
2384                 if (IS_ERR(cq->umem)) {
2385                         rc = PTR_ERR(cq->umem);
2386                         goto fail;
2387                 }
2388                 cq->qplib_cq.sghead = cq->umem->sg_head.sgl;
2389                 cq->qplib_cq.nmap = cq->umem->nmap;
2390                 cq->qplib_cq.dpi = &uctx->dpi;
2391         } else {
2392                 cq->max_cql = min_t(u32, entries, MAX_CQL_PER_POLL);
2393                 cq->cql = kcalloc(cq->max_cql, sizeof(struct bnxt_qplib_cqe),
2394                                   GFP_KERNEL);
2395                 if (!cq->cql) {
2396                         rc = -ENOMEM;
2397                         goto fail;
2398                 }
2399
2400                 cq->qplib_cq.dpi = &rdev->dpi_privileged;
2401                 cq->qplib_cq.sghead = NULL;
2402                 cq->qplib_cq.nmap = 0;
2403         }
2404         cq->qplib_cq.max_wqe = entries;
2405         cq->qplib_cq.cnq_hw_ring_id = rdev->nq.ring_id;
2406
2407         rc = bnxt_qplib_create_cq(&rdev->qplib_res, &cq->qplib_cq);
2408         if (rc) {
2409                 dev_err(rdev_to_dev(rdev), "Failed to create HW CQ");
2410                 goto fail;
2411         }
2412
2413         cq->ib_cq.cqe = entries;
2414         cq->cq_period = cq->qplib_cq.period;
2415         rdev->nq.budget++;
2416
2417         atomic_inc(&rdev->cq_count);
2418
2419         if (context) {
2420                 struct bnxt_re_cq_resp resp;
2421
2422                 resp.cqid = cq->qplib_cq.id;
2423                 resp.tail = cq->qplib_cq.hwq.cons;
2424                 resp.phase = cq->qplib_cq.period;
2425                 resp.rsvd = 0;
2426                 rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
2427                 if (rc) {
2428                         dev_err(rdev_to_dev(rdev), "Failed to copy CQ udata");
2429                         bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq);
2430                         goto c2fail;
2431                 }
2432         }
2433
2434         return &cq->ib_cq;
2435
2436 c2fail:
2437         if (context)
2438                 ib_umem_release(cq->umem);
2439 fail:
2440         kfree(cq->cql);
2441         kfree(cq);
2442         return ERR_PTR(rc);
2443 }
2444
2445 static u8 __req_to_ib_wc_status(u8 qstatus)
2446 {
2447         switch (qstatus) {
2448         case CQ_REQ_STATUS_OK:
2449                 return IB_WC_SUCCESS;
2450         case CQ_REQ_STATUS_BAD_RESPONSE_ERR:
2451                 return IB_WC_BAD_RESP_ERR;
2452         case CQ_REQ_STATUS_LOCAL_LENGTH_ERR:
2453                 return IB_WC_LOC_LEN_ERR;
2454         case CQ_REQ_STATUS_LOCAL_QP_OPERATION_ERR:
2455                 return IB_WC_LOC_QP_OP_ERR;
2456         case CQ_REQ_STATUS_LOCAL_PROTECTION_ERR:
2457                 return IB_WC_LOC_PROT_ERR;
2458         case CQ_REQ_STATUS_MEMORY_MGT_OPERATION_ERR:
2459                 return IB_WC_GENERAL_ERR;
2460         case CQ_REQ_STATUS_REMOTE_INVALID_REQUEST_ERR:
2461                 return IB_WC_REM_INV_REQ_ERR;
2462         case CQ_REQ_STATUS_REMOTE_ACCESS_ERR:
2463                 return IB_WC_REM_ACCESS_ERR;
2464         case CQ_REQ_STATUS_REMOTE_OPERATION_ERR:
2465                 return IB_WC_REM_OP_ERR;
2466         case CQ_REQ_STATUS_RNR_NAK_RETRY_CNT_ERR:
2467                 return IB_WC_RNR_RETRY_EXC_ERR;
2468         case CQ_REQ_STATUS_TRANSPORT_RETRY_CNT_ERR:
2469                 return IB_WC_RETRY_EXC_ERR;
2470         case CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR:
2471                 return IB_WC_WR_FLUSH_ERR;
2472         default:
2473                 return IB_WC_GENERAL_ERR;
2474         }
2475         return 0;
2476 }
2477
2478 static u8 __rawqp1_to_ib_wc_status(u8 qstatus)
2479 {
2480         switch (qstatus) {
2481         case CQ_RES_RAWETH_QP1_STATUS_OK:
2482                 return IB_WC_SUCCESS;
2483         case CQ_RES_RAWETH_QP1_STATUS_LOCAL_ACCESS_ERROR:
2484                 return IB_WC_LOC_ACCESS_ERR;
2485         case CQ_RES_RAWETH_QP1_STATUS_HW_LOCAL_LENGTH_ERR:
2486                 return IB_WC_LOC_LEN_ERR;
2487         case CQ_RES_RAWETH_QP1_STATUS_LOCAL_PROTECTION_ERR:
2488                 return IB_WC_LOC_PROT_ERR;
2489         case CQ_RES_RAWETH_QP1_STATUS_LOCAL_QP_OPERATION_ERR:
2490                 return IB_WC_LOC_QP_OP_ERR;
2491         case CQ_RES_RAWETH_QP1_STATUS_MEMORY_MGT_OPERATION_ERR:
2492                 return IB_WC_GENERAL_ERR;
2493         case CQ_RES_RAWETH_QP1_STATUS_WORK_REQUEST_FLUSHED_ERR:
2494                 return IB_WC_WR_FLUSH_ERR;
2495         case CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR:
2496                 return IB_WC_WR_FLUSH_ERR;
2497         default:
2498                 return IB_WC_GENERAL_ERR;
2499         }
2500 }
2501
2502 static u8 __rc_to_ib_wc_status(u8 qstatus)
2503 {
2504         switch (qstatus) {
2505         case CQ_RES_RC_STATUS_OK:
2506                 return IB_WC_SUCCESS;
2507         case CQ_RES_RC_STATUS_LOCAL_ACCESS_ERROR:
2508                 return IB_WC_LOC_ACCESS_ERR;
2509         case CQ_RES_RC_STATUS_LOCAL_LENGTH_ERR:
2510                 return IB_WC_LOC_LEN_ERR;
2511         case CQ_RES_RC_STATUS_LOCAL_PROTECTION_ERR:
2512                 return IB_WC_LOC_PROT_ERR;
2513         case CQ_RES_RC_STATUS_LOCAL_QP_OPERATION_ERR:
2514                 return IB_WC_LOC_QP_OP_ERR;
2515         case CQ_RES_RC_STATUS_MEMORY_MGT_OPERATION_ERR:
2516                 return IB_WC_GENERAL_ERR;
2517         case CQ_RES_RC_STATUS_REMOTE_INVALID_REQUEST_ERR:
2518                 return IB_WC_REM_INV_REQ_ERR;
2519         case CQ_RES_RC_STATUS_WORK_REQUEST_FLUSHED_ERR:
2520                 return IB_WC_WR_FLUSH_ERR;
2521         case CQ_RES_RC_STATUS_HW_FLUSH_ERR:
2522                 return IB_WC_WR_FLUSH_ERR;
2523         default:
2524                 return IB_WC_GENERAL_ERR;
2525         }
2526 }
2527
2528 static void bnxt_re_process_req_wc(struct ib_wc *wc, struct bnxt_qplib_cqe *cqe)
2529 {
2530         switch (cqe->type) {
2531         case BNXT_QPLIB_SWQE_TYPE_SEND:
2532                 wc->opcode = IB_WC_SEND;
2533                 break;
2534         case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM:
2535                 wc->opcode = IB_WC_SEND;
2536                 wc->wc_flags |= IB_WC_WITH_IMM;
2537                 break;
2538         case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV:
2539                 wc->opcode = IB_WC_SEND;
2540                 wc->wc_flags |= IB_WC_WITH_INVALIDATE;
2541                 break;
2542         case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE:
2543                 wc->opcode = IB_WC_RDMA_WRITE;
2544                 break;
2545         case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM:
2546                 wc->opcode = IB_WC_RDMA_WRITE;
2547                 wc->wc_flags |= IB_WC_WITH_IMM;
2548                 break;
2549         case BNXT_QPLIB_SWQE_TYPE_RDMA_READ:
2550                 wc->opcode = IB_WC_RDMA_READ;
2551                 break;
2552         case BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP:
2553                 wc->opcode = IB_WC_COMP_SWAP;
2554                 break;
2555         case BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD:
2556                 wc->opcode = IB_WC_FETCH_ADD;
2557                 break;
2558         case BNXT_QPLIB_SWQE_TYPE_LOCAL_INV:
2559                 wc->opcode = IB_WC_LOCAL_INV;
2560                 break;
2561         case BNXT_QPLIB_SWQE_TYPE_REG_MR:
2562                 wc->opcode = IB_WC_REG_MR;
2563                 break;
2564         default:
2565                 wc->opcode = IB_WC_SEND;
2566                 break;
2567         }
2568
2569         wc->status = __req_to_ib_wc_status(cqe->status);
2570 }
2571
2572 static int bnxt_re_check_packet_type(u16 raweth_qp1_flags,
2573                                      u16 raweth_qp1_flags2)
2574 {
2575         bool is_udp = false, is_ipv6 = false, is_ipv4 = false;
2576
2577         /* raweth_qp1_flags Bit 9-6 indicates itype */
2578         if ((raweth_qp1_flags & CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE)
2579             != CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE)
2580                 return -1;
2581
2582         if (raweth_qp1_flags2 &
2583             CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_CS_CALC &&
2584             raweth_qp1_flags2 &
2585             CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_L4_CS_CALC) {
2586                 is_udp = true;
2587                 /* raweth_qp1_flags2 Bit 8 indicates ip_type. 0-v4 1 - v6 */
2588                 (raweth_qp1_flags2 &
2589                  CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_TYPE) ?
2590                         (is_ipv6 = true) : (is_ipv4 = true);
2591                 return ((is_ipv6) ?
2592                          BNXT_RE_ROCEV2_IPV6_PACKET :
2593                          BNXT_RE_ROCEV2_IPV4_PACKET);
2594         } else {
2595                 return BNXT_RE_ROCE_V1_PACKET;
2596         }
2597 }
2598
2599 static int bnxt_re_to_ib_nw_type(int nw_type)
2600 {
2601         u8 nw_hdr_type = 0xFF;
2602
2603         switch (nw_type) {
2604         case BNXT_RE_ROCE_V1_PACKET:
2605                 nw_hdr_type = RDMA_NETWORK_ROCE_V1;
2606                 break;
2607         case BNXT_RE_ROCEV2_IPV4_PACKET:
2608                 nw_hdr_type = RDMA_NETWORK_IPV4;
2609                 break;
2610         case BNXT_RE_ROCEV2_IPV6_PACKET:
2611                 nw_hdr_type = RDMA_NETWORK_IPV6;
2612                 break;
2613         }
2614         return nw_hdr_type;
2615 }
2616
2617 static bool bnxt_re_is_loopback_packet(struct bnxt_re_dev *rdev,
2618                                        void *rq_hdr_buf)
2619 {
2620         u8 *tmp_buf = NULL;
2621         struct ethhdr *eth_hdr;
2622         u16 eth_type;
2623         bool rc = false;
2624
2625         tmp_buf = (u8 *)rq_hdr_buf;
2626         /*
2627          * If dest mac is not same as I/F mac, this could be a
2628          * loopback address or multicast address, check whether
2629          * it is a loopback packet
2630          */
2631         if (!ether_addr_equal(tmp_buf, rdev->netdev->dev_addr)) {
2632                 tmp_buf += 4;
2633                 /* Check the  ether type */
2634                 eth_hdr = (struct ethhdr *)tmp_buf;
2635                 eth_type = ntohs(eth_hdr->h_proto);
2636                 switch (eth_type) {
2637                 case ETH_P_IBOE:
2638                         rc = true;
2639                         break;
2640                 case ETH_P_IP:
2641                 case ETH_P_IPV6: {
2642                         u32 len;
2643                         struct udphdr *udp_hdr;
2644
2645                         len = (eth_type == ETH_P_IP ? sizeof(struct iphdr) :
2646                                                       sizeof(struct ipv6hdr));
2647                         tmp_buf += sizeof(struct ethhdr) + len;
2648                         udp_hdr = (struct udphdr *)tmp_buf;
2649                         if (ntohs(udp_hdr->dest) ==
2650                                     ROCE_V2_UDP_DPORT)
2651                                 rc = true;
2652                         break;
2653                         }
2654                 default:
2655                         break;
2656                 }
2657         }
2658
2659         return rc;
2660 }
2661
2662 static int bnxt_re_process_raw_qp_pkt_rx(struct bnxt_re_qp *qp1_qp,
2663                                          struct bnxt_qplib_cqe *cqe)
2664 {
2665         struct bnxt_re_dev *rdev = qp1_qp->rdev;
2666         struct bnxt_re_sqp_entries *sqp_entry = NULL;
2667         struct bnxt_re_qp *qp = rdev->qp1_sqp;
2668         struct ib_send_wr *swr;
2669         struct ib_ud_wr udwr;
2670         struct ib_recv_wr rwr;
2671         int pkt_type = 0;
2672         u32 tbl_idx;
2673         void *rq_hdr_buf;
2674         dma_addr_t rq_hdr_buf_map;
2675         dma_addr_t shrq_hdr_buf_map;
2676         u32 offset = 0;
2677         u32 skip_bytes = 0;
2678         struct ib_sge s_sge[2];
2679         struct ib_sge r_sge[2];
2680         int rc;
2681
2682         memset(&udwr, 0, sizeof(udwr));
2683         memset(&rwr, 0, sizeof(rwr));
2684         memset(&s_sge, 0, sizeof(s_sge));
2685         memset(&r_sge, 0, sizeof(r_sge));
2686
2687         swr = &udwr.wr;
2688         tbl_idx = cqe->wr_id;
2689
2690         rq_hdr_buf = qp1_qp->qplib_qp.rq_hdr_buf +
2691                         (tbl_idx * qp1_qp->qplib_qp.rq_hdr_buf_size);
2692         rq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&qp1_qp->qplib_qp,
2693                                                           tbl_idx);
2694
2695         /* Shadow QP header buffer */
2696         shrq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&qp->qplib_qp,
2697                                                             tbl_idx);
2698         sqp_entry = &rdev->sqp_tbl[tbl_idx];
2699
2700         /* Store this cqe */
2701         memcpy(&sqp_entry->cqe, cqe, sizeof(struct bnxt_qplib_cqe));
2702         sqp_entry->qp1_qp = qp1_qp;
2703
2704         /* Find packet type from the cqe */
2705
2706         pkt_type = bnxt_re_check_packet_type(cqe->raweth_qp1_flags,
2707                                              cqe->raweth_qp1_flags2);
2708         if (pkt_type < 0) {
2709                 dev_err(rdev_to_dev(rdev), "Invalid packet\n");
2710                 return -EINVAL;
2711         }
2712
2713         /* Adjust the offset for the user buffer and post in the rq */
2714
2715         if (pkt_type == BNXT_RE_ROCEV2_IPV4_PACKET)
2716                 offset = 20;
2717
2718         /*
2719          * QP1 loopback packet has 4 bytes of internal header before
2720          * ether header. Skip these four bytes.
2721          */
2722         if (bnxt_re_is_loopback_packet(rdev, rq_hdr_buf))
2723                 skip_bytes = 4;
2724
2725         /* First send SGE . Skip the ether header*/
2726         s_sge[0].addr = rq_hdr_buf_map + BNXT_QPLIB_MAX_QP1_RQ_ETH_HDR_SIZE
2727                         + skip_bytes;
2728         s_sge[0].lkey = 0xFFFFFFFF;
2729         s_sge[0].length = offset ? BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV4 :
2730                                 BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6;
2731
2732         /* Second Send SGE */
2733         s_sge[1].addr = s_sge[0].addr + s_sge[0].length +
2734                         BNXT_QPLIB_MAX_QP1_RQ_BDETH_HDR_SIZE;
2735         if (pkt_type != BNXT_RE_ROCE_V1_PACKET)
2736                 s_sge[1].addr += 8;
2737         s_sge[1].lkey = 0xFFFFFFFF;
2738         s_sge[1].length = 256;
2739
2740         /* First recv SGE */
2741
2742         r_sge[0].addr = shrq_hdr_buf_map;
2743         r_sge[0].lkey = 0xFFFFFFFF;
2744         r_sge[0].length = 40;
2745
2746         r_sge[1].addr = sqp_entry->sge.addr + offset;
2747         r_sge[1].lkey = sqp_entry->sge.lkey;
2748         r_sge[1].length = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6 + 256 - offset;
2749
2750         /* Create receive work request */
2751         rwr.num_sge = 2;
2752         rwr.sg_list = r_sge;
2753         rwr.wr_id = tbl_idx;
2754         rwr.next = NULL;
2755
2756         rc = bnxt_re_post_recv_shadow_qp(rdev, qp, &rwr);
2757         if (rc) {
2758                 dev_err(rdev_to_dev(rdev),
2759                         "Failed to post Rx buffers to shadow QP");
2760                 return -ENOMEM;
2761         }
2762
2763         swr->num_sge = 2;
2764         swr->sg_list = s_sge;
2765         swr->wr_id = tbl_idx;
2766         swr->opcode = IB_WR_SEND;
2767         swr->next = NULL;
2768
2769         udwr.ah = &rdev->sqp_ah->ib_ah;
2770         udwr.remote_qpn = rdev->qp1_sqp->qplib_qp.id;
2771         udwr.remote_qkey = rdev->qp1_sqp->qplib_qp.qkey;
2772
2773         /* post data received  in the send queue */
2774         rc = bnxt_re_post_send_shadow_qp(rdev, qp, swr);
2775
2776         return 0;
2777 }
2778
2779 static void bnxt_re_process_res_rawqp1_wc(struct ib_wc *wc,
2780                                           struct bnxt_qplib_cqe *cqe)
2781 {
2782         wc->opcode = IB_WC_RECV;
2783         wc->status = __rawqp1_to_ib_wc_status(cqe->status);
2784         wc->wc_flags |= IB_WC_GRH;
2785 }
2786
2787 static void bnxt_re_process_res_rc_wc(struct ib_wc *wc,
2788                                       struct bnxt_qplib_cqe *cqe)
2789 {
2790         wc->opcode = IB_WC_RECV;
2791         wc->status = __rc_to_ib_wc_status(cqe->status);
2792
2793         if (cqe->flags & CQ_RES_RC_FLAGS_IMM)
2794                 wc->wc_flags |= IB_WC_WITH_IMM;
2795         if (cqe->flags & CQ_RES_RC_FLAGS_INV)
2796                 wc->wc_flags |= IB_WC_WITH_INVALIDATE;
2797         if ((cqe->flags & (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) ==
2798             (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM))
2799                 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
2800 }
2801
2802 static void bnxt_re_process_res_shadow_qp_wc(struct bnxt_re_qp *qp,
2803                                              struct ib_wc *wc,
2804                                              struct bnxt_qplib_cqe *cqe)
2805 {
2806         u32 tbl_idx;
2807         struct bnxt_re_dev *rdev = qp->rdev;
2808         struct bnxt_re_qp *qp1_qp = NULL;
2809         struct bnxt_qplib_cqe *orig_cqe = NULL;
2810         struct bnxt_re_sqp_entries *sqp_entry = NULL;
2811         int nw_type;
2812
2813         tbl_idx = cqe->wr_id;
2814
2815         sqp_entry = &rdev->sqp_tbl[tbl_idx];
2816         qp1_qp = sqp_entry->qp1_qp;
2817         orig_cqe = &sqp_entry->cqe;
2818
2819         wc->wr_id = sqp_entry->wrid;
2820         wc->byte_len = orig_cqe->length;
2821         wc->qp = &qp1_qp->ib_qp;
2822
2823         wc->ex.imm_data = orig_cqe->immdata;
2824         wc->src_qp = orig_cqe->src_qp;
2825         memcpy(wc->smac, orig_cqe->smac, ETH_ALEN);
2826         wc->port_num = 1;
2827         wc->vendor_err = orig_cqe->status;
2828
2829         wc->opcode = IB_WC_RECV;
2830         wc->status = __rawqp1_to_ib_wc_status(orig_cqe->status);
2831         wc->wc_flags |= IB_WC_GRH;
2832
2833         nw_type = bnxt_re_check_packet_type(orig_cqe->raweth_qp1_flags,
2834                                             orig_cqe->raweth_qp1_flags2);
2835         if (nw_type >= 0) {
2836                 wc->network_hdr_type = bnxt_re_to_ib_nw_type(nw_type);
2837                 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE;
2838         }
2839 }
2840
2841 static void bnxt_re_process_res_ud_wc(struct ib_wc *wc,
2842                                       struct bnxt_qplib_cqe *cqe)
2843 {
2844         wc->opcode = IB_WC_RECV;
2845         wc->status = __rc_to_ib_wc_status(cqe->status);
2846
2847         if (cqe->flags & CQ_RES_RC_FLAGS_IMM)
2848                 wc->wc_flags |= IB_WC_WITH_IMM;
2849         if (cqe->flags & CQ_RES_RC_FLAGS_INV)
2850                 wc->wc_flags |= IB_WC_WITH_INVALIDATE;
2851         if ((cqe->flags & (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) ==
2852             (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM))
2853                 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
2854 }
2855
2856 static int send_phantom_wqe(struct bnxt_re_qp *qp)
2857 {
2858         struct bnxt_qplib_qp *lib_qp = &qp->qplib_qp;
2859         unsigned long flags;
2860         int rc = 0;
2861
2862         spin_lock_irqsave(&qp->sq_lock, flags);
2863
2864         rc = bnxt_re_bind_fence_mw(lib_qp);
2865         if (!rc) {
2866                 lib_qp->sq.phantom_wqe_cnt++;
2867                 dev_dbg(&lib_qp->sq.hwq.pdev->dev,
2868                         "qp %#x sq->prod %#x sw_prod %#x phantom_wqe_cnt %d\n",
2869                         lib_qp->id, lib_qp->sq.hwq.prod,
2870                         HWQ_CMP(lib_qp->sq.hwq.prod, &lib_qp->sq.hwq),
2871                         lib_qp->sq.phantom_wqe_cnt);
2872         }
2873
2874         spin_unlock_irqrestore(&qp->sq_lock, flags);
2875         return rc;
2876 }
2877
2878 int bnxt_re_poll_cq(struct ib_cq *ib_cq, int num_entries, struct ib_wc *wc)
2879 {
2880         struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
2881         struct bnxt_re_qp *qp;
2882         struct bnxt_qplib_cqe *cqe;
2883         int i, ncqe, budget;
2884         struct bnxt_qplib_q *sq;
2885         struct bnxt_qplib_qp *lib_qp;
2886         u32 tbl_idx;
2887         struct bnxt_re_sqp_entries *sqp_entry = NULL;
2888         unsigned long flags;
2889
2890         spin_lock_irqsave(&cq->cq_lock, flags);
2891         budget = min_t(u32, num_entries, cq->max_cql);
2892         if (!cq->cql) {
2893                 dev_err(rdev_to_dev(cq->rdev), "POLL CQ : no CQL to use");
2894                 goto exit;
2895         }
2896         cqe = &cq->cql[0];
2897         while (budget) {
2898                 lib_qp = NULL;
2899                 ncqe = bnxt_qplib_poll_cq(&cq->qplib_cq, cqe, budget, &lib_qp);
2900                 if (lib_qp) {
2901                         sq = &lib_qp->sq;
2902                         if (sq->send_phantom) {
2903                                 qp = container_of(lib_qp,
2904                                                   struct bnxt_re_qp, qplib_qp);
2905                                 if (send_phantom_wqe(qp) == -ENOMEM)
2906                                         dev_err(rdev_to_dev(cq->rdev),
2907                                                 "Phantom failed! Scheduled to send again\n");
2908                                 else
2909                                         sq->send_phantom = false;
2910                         }
2911                 }
2912
2913                 if (!ncqe)
2914                         break;
2915
2916                 for (i = 0; i < ncqe; i++, cqe++) {
2917                         /* Transcribe each qplib_wqe back to ib_wc */
2918                         memset(wc, 0, sizeof(*wc));
2919
2920                         wc->wr_id = cqe->wr_id;
2921                         wc->byte_len = cqe->length;
2922                         qp = container_of
2923                                 ((struct bnxt_qplib_qp *)
2924                                  (unsigned long)(cqe->qp_handle),
2925                                  struct bnxt_re_qp, qplib_qp);
2926                         if (!qp) {
2927                                 dev_err(rdev_to_dev(cq->rdev),
2928                                         "POLL CQ : bad QP handle");
2929                                 continue;
2930                         }
2931                         wc->qp = &qp->ib_qp;
2932                         wc->ex.imm_data = cqe->immdata;
2933                         wc->src_qp = cqe->src_qp;
2934                         memcpy(wc->smac, cqe->smac, ETH_ALEN);
2935                         wc->port_num = 1;
2936                         wc->vendor_err = cqe->status;
2937
2938                         switch (cqe->opcode) {
2939                         case CQ_BASE_CQE_TYPE_REQ:
2940                                 if (qp->qplib_qp.id ==
2941                                     qp->rdev->qp1_sqp->qplib_qp.id) {
2942                                         /* Handle this completion with
2943                                          * the stored completion
2944                                          */
2945                                         memset(wc, 0, sizeof(*wc));
2946                                         continue;
2947                                 }
2948                                 bnxt_re_process_req_wc(wc, cqe);
2949                                 break;
2950                         case CQ_BASE_CQE_TYPE_RES_RAWETH_QP1:
2951                                 if (!cqe->status) {
2952                                         int rc = 0;
2953
2954                                         rc = bnxt_re_process_raw_qp_pkt_rx
2955                                                                 (qp, cqe);
2956                                         if (!rc) {
2957                                                 memset(wc, 0, sizeof(*wc));
2958                                                 continue;
2959                                         }
2960                                         cqe->status = -1;
2961                                 }
2962                                 /* Errors need not be looped back.
2963                                  * But change the wr_id to the one
2964                                  * stored in the table
2965                                  */
2966                                 tbl_idx = cqe->wr_id;
2967                                 sqp_entry = &cq->rdev->sqp_tbl[tbl_idx];
2968                                 wc->wr_id = sqp_entry->wrid;
2969                                 bnxt_re_process_res_rawqp1_wc(wc, cqe);
2970                                 break;
2971                         case CQ_BASE_CQE_TYPE_RES_RC:
2972                                 bnxt_re_process_res_rc_wc(wc, cqe);
2973                                 break;
2974                         case CQ_BASE_CQE_TYPE_RES_UD:
2975                                 if (qp->qplib_qp.id ==
2976                                     qp->rdev->qp1_sqp->qplib_qp.id) {
2977                                         /* Handle this completion with
2978                                          * the stored completion
2979                                          */
2980                                         if (cqe->status) {
2981                                                 continue;
2982                                         } else {
2983                                                 bnxt_re_process_res_shadow_qp_wc
2984                                                                 (qp, wc, cqe);
2985                                                 break;
2986                                         }
2987                                 }
2988                                 bnxt_re_process_res_ud_wc(wc, cqe);
2989                                 break;
2990                         default:
2991                                 dev_err(rdev_to_dev(cq->rdev),
2992                                         "POLL CQ : type 0x%x not handled",
2993                                         cqe->opcode);
2994                                 continue;
2995                         }
2996                         wc++;
2997                         budget--;
2998                 }
2999         }
3000 exit:
3001         spin_unlock_irqrestore(&cq->cq_lock, flags);
3002         return num_entries - budget;
3003 }
3004
3005 int bnxt_re_req_notify_cq(struct ib_cq *ib_cq,
3006                           enum ib_cq_notify_flags ib_cqn_flags)
3007 {
3008         struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
3009         int type = 0;
3010
3011         /* Trigger on the very next completion */
3012         if (ib_cqn_flags & IB_CQ_NEXT_COMP)
3013                 type = DBR_DBR_TYPE_CQ_ARMALL;
3014         /* Trigger on the next solicited completion */
3015         else if (ib_cqn_flags & IB_CQ_SOLICITED)
3016                 type = DBR_DBR_TYPE_CQ_ARMSE;
3017
3018         bnxt_qplib_req_notify_cq(&cq->qplib_cq, type);
3019
3020         return 0;
3021 }
3022
3023 /* Memory Regions */
3024 struct ib_mr *bnxt_re_get_dma_mr(struct ib_pd *ib_pd, int mr_access_flags)
3025 {
3026         struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
3027         struct bnxt_re_dev *rdev = pd->rdev;
3028         struct bnxt_re_mr *mr;
3029         u64 pbl = 0;
3030         int rc;
3031
3032         mr = kzalloc(sizeof(*mr), GFP_KERNEL);
3033         if (!mr)
3034                 return ERR_PTR(-ENOMEM);
3035
3036         mr->rdev = rdev;
3037         mr->qplib_mr.pd = &pd->qplib_pd;
3038         mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags);
3039         mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR;
3040
3041         /* Allocate and register 0 as the address */
3042         rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
3043         if (rc)
3044                 goto fail;
3045
3046         mr->qplib_mr.hwq.level = PBL_LVL_MAX;
3047         mr->qplib_mr.total_size = -1; /* Infinte length */
3048         rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, &pbl, 0, false);
3049         if (rc)
3050                 goto fail_mr;
3051
3052         mr->ib_mr.lkey = mr->qplib_mr.lkey;
3053         if (mr_access_flags & (IB_ACCESS_REMOTE_WRITE | IB_ACCESS_REMOTE_READ |
3054                                IB_ACCESS_REMOTE_ATOMIC))
3055                 mr->ib_mr.rkey = mr->ib_mr.lkey;
3056         atomic_inc(&rdev->mr_count);
3057
3058         return &mr->ib_mr;
3059
3060 fail_mr:
3061         bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
3062 fail:
3063         kfree(mr);
3064         return ERR_PTR(rc);
3065 }
3066
3067 int bnxt_re_dereg_mr(struct ib_mr *ib_mr)
3068 {
3069         struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
3070         struct bnxt_re_dev *rdev = mr->rdev;
3071         int rc;
3072
3073         rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
3074         if (rc) {
3075                 dev_err(rdev_to_dev(rdev), "Dereg MR failed: %#x\n", rc);
3076                 return rc;
3077         }
3078
3079         if (mr->npages && mr->pages) {
3080                 rc = bnxt_qplib_free_fast_reg_page_list(&rdev->qplib_res,
3081                                                         &mr->qplib_frpl);
3082                 kfree(mr->pages);
3083                 mr->npages = 0;
3084                 mr->pages = NULL;
3085         }
3086         if (!IS_ERR_OR_NULL(mr->ib_umem))
3087                 ib_umem_release(mr->ib_umem);
3088
3089         kfree(mr);
3090         atomic_dec(&rdev->mr_count);
3091         return rc;
3092 }
3093
3094 static int bnxt_re_set_page(struct ib_mr *ib_mr, u64 addr)
3095 {
3096         struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
3097
3098         if (unlikely(mr->npages == mr->qplib_frpl.max_pg_ptrs))
3099                 return -ENOMEM;
3100
3101         mr->pages[mr->npages++] = addr;
3102         return 0;
3103 }
3104
3105 int bnxt_re_map_mr_sg(struct ib_mr *ib_mr, struct scatterlist *sg, int sg_nents,
3106                       unsigned int *sg_offset)
3107 {
3108         struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
3109
3110         mr->npages = 0;
3111         return ib_sg_to_pages(ib_mr, sg, sg_nents, sg_offset, bnxt_re_set_page);
3112 }
3113
3114 struct ib_mr *bnxt_re_alloc_mr(struct ib_pd *ib_pd, enum ib_mr_type type,
3115                                u32 max_num_sg)
3116 {
3117         struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
3118         struct bnxt_re_dev *rdev = pd->rdev;
3119         struct bnxt_re_mr *mr = NULL;
3120         int rc;
3121
3122         if (type != IB_MR_TYPE_MEM_REG) {
3123                 dev_dbg(rdev_to_dev(rdev), "MR type 0x%x not supported", type);
3124                 return ERR_PTR(-EINVAL);
3125         }
3126         if (max_num_sg > MAX_PBL_LVL_1_PGS)
3127                 return ERR_PTR(-EINVAL);
3128
3129         mr = kzalloc(sizeof(*mr), GFP_KERNEL);
3130         if (!mr)
3131                 return ERR_PTR(-ENOMEM);
3132
3133         mr->rdev = rdev;
3134         mr->qplib_mr.pd = &pd->qplib_pd;
3135         mr->qplib_mr.flags = BNXT_QPLIB_FR_PMR;
3136         mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR;
3137
3138         rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
3139         if (rc)
3140                 goto fail;
3141
3142         mr->ib_mr.lkey = mr->qplib_mr.lkey;
3143         mr->ib_mr.rkey = mr->ib_mr.lkey;
3144
3145         mr->pages = kcalloc(max_num_sg, sizeof(u64), GFP_KERNEL);
3146         if (!mr->pages) {
3147                 rc = -ENOMEM;
3148                 goto fail;
3149         }
3150         rc = bnxt_qplib_alloc_fast_reg_page_list(&rdev->qplib_res,
3151                                                  &mr->qplib_frpl, max_num_sg);
3152         if (rc) {
3153                 dev_err(rdev_to_dev(rdev),
3154                         "Failed to allocate HW FR page list");
3155                 goto fail_mr;
3156         }
3157
3158         atomic_inc(&rdev->mr_count);
3159         return &mr->ib_mr;
3160
3161 fail_mr:
3162         bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
3163 fail:
3164         kfree(mr->pages);
3165         kfree(mr);
3166         return ERR_PTR(rc);
3167 }
3168
3169 struct ib_mw *bnxt_re_alloc_mw(struct ib_pd *ib_pd, enum ib_mw_type type,
3170                                struct ib_udata *udata)
3171 {
3172         struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
3173         struct bnxt_re_dev *rdev = pd->rdev;
3174         struct bnxt_re_mw *mw;
3175         int rc;
3176
3177         mw = kzalloc(sizeof(*mw), GFP_KERNEL);
3178         if (!mw)
3179                 return ERR_PTR(-ENOMEM);
3180         mw->rdev = rdev;
3181         mw->qplib_mw.pd = &pd->qplib_pd;
3182
3183         mw->qplib_mw.type = (type == IB_MW_TYPE_1 ?
3184                                CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1 :
3185                                CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B);
3186         rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mw->qplib_mw);
3187         if (rc) {
3188                 dev_err(rdev_to_dev(rdev), "Allocate MW failed!");
3189                 goto fail;
3190         }
3191         mw->ib_mw.rkey = mw->qplib_mw.rkey;
3192
3193         atomic_inc(&rdev->mw_count);
3194         return &mw->ib_mw;
3195
3196 fail:
3197         kfree(mw);
3198         return ERR_PTR(rc);
3199 }
3200
3201 int bnxt_re_dealloc_mw(struct ib_mw *ib_mw)
3202 {
3203         struct bnxt_re_mw *mw = container_of(ib_mw, struct bnxt_re_mw, ib_mw);
3204         struct bnxt_re_dev *rdev = mw->rdev;
3205         int rc;
3206
3207         rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mw->qplib_mw);
3208         if (rc) {
3209                 dev_err(rdev_to_dev(rdev), "Free MW failed: %#x\n", rc);
3210                 return rc;
3211         }
3212
3213         kfree(mw);
3214         atomic_dec(&rdev->mw_count);
3215         return rc;
3216 }
3217
3218 /* uverbs */
3219 struct ib_mr *bnxt_re_reg_user_mr(struct ib_pd *ib_pd, u64 start, u64 length,
3220                                   u64 virt_addr, int mr_access_flags,
3221                                   struct ib_udata *udata)
3222 {
3223         struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
3224         struct bnxt_re_dev *rdev = pd->rdev;
3225         struct bnxt_re_mr *mr;
3226         struct ib_umem *umem;
3227         u64 *pbl_tbl, *pbl_tbl_orig;
3228         int i, umem_pgs, pages, rc;
3229         struct scatterlist *sg;
3230         int entry;
3231
3232         mr = kzalloc(sizeof(*mr), GFP_KERNEL);
3233         if (!mr)
3234                 return ERR_PTR(-ENOMEM);
3235
3236         mr->rdev = rdev;
3237         mr->qplib_mr.pd = &pd->qplib_pd;
3238         mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags);
3239         mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_MR;
3240
3241         umem = ib_umem_get(ib_pd->uobject->context, start, length,
3242                            mr_access_flags, 0);
3243         if (IS_ERR(umem)) {
3244                 dev_err(rdev_to_dev(rdev), "Failed to get umem");
3245                 rc = -EFAULT;
3246                 goto free_mr;
3247         }
3248         mr->ib_umem = umem;
3249
3250         rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
3251         if (rc) {
3252                 dev_err(rdev_to_dev(rdev), "Failed to allocate MR");
3253                 goto release_umem;
3254         }
3255         /* The fixed portion of the rkey is the same as the lkey */
3256         mr->ib_mr.rkey = mr->qplib_mr.rkey;
3257
3258         mr->qplib_mr.va = virt_addr;
3259         umem_pgs = ib_umem_page_count(umem);
3260         if (!umem_pgs) {
3261                 dev_err(rdev_to_dev(rdev), "umem is invalid!");
3262                 rc = -EINVAL;
3263                 goto free_mrw;
3264         }
3265         mr->qplib_mr.total_size = length;
3266
3267         pbl_tbl = kcalloc(umem_pgs, sizeof(u64 *), GFP_KERNEL);
3268         if (!pbl_tbl) {
3269                 rc = -EINVAL;
3270                 goto free_mrw;
3271         }
3272         pbl_tbl_orig = pbl_tbl;
3273
3274         if (umem->hugetlb) {
3275                 dev_err(rdev_to_dev(rdev), "umem hugetlb not supported!");
3276                 rc = -EFAULT;
3277                 goto fail;
3278         }
3279
3280         if (umem->page_shift != PAGE_SHIFT) {
3281                 dev_err(rdev_to_dev(rdev), "umem page shift unsupported!");
3282                 rc = -EFAULT;
3283                 goto fail;
3284         }
3285         /* Map umem buf ptrs to the PBL */
3286         for_each_sg(umem->sg_head.sgl, sg, umem->nmap, entry) {
3287                 pages = sg_dma_len(sg) >> umem->page_shift;
3288                 for (i = 0; i < pages; i++, pbl_tbl++)
3289                         *pbl_tbl = sg_dma_address(sg) + (i << umem->page_shift);
3290         }
3291         rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, pbl_tbl_orig,
3292                                umem_pgs, false);
3293         if (rc) {
3294                 dev_err(rdev_to_dev(rdev), "Failed to register user MR");
3295                 goto fail;
3296         }
3297
3298         kfree(pbl_tbl_orig);
3299
3300         mr->ib_mr.lkey = mr->qplib_mr.lkey;
3301         mr->ib_mr.rkey = mr->qplib_mr.lkey;
3302         atomic_inc(&rdev->mr_count);
3303
3304         return &mr->ib_mr;
3305 fail:
3306         kfree(pbl_tbl_orig);
3307 free_mrw:
3308         bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
3309 release_umem:
3310         ib_umem_release(umem);
3311 free_mr:
3312         kfree(mr);
3313         return ERR_PTR(rc);
3314 }
3315
3316 struct ib_ucontext *bnxt_re_alloc_ucontext(struct ib_device *ibdev,
3317                                            struct ib_udata *udata)
3318 {
3319         struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
3320         struct bnxt_re_uctx_resp resp;
3321         struct bnxt_re_ucontext *uctx;
3322         struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
3323         int rc;
3324
3325         dev_dbg(rdev_to_dev(rdev), "ABI version requested %d",
3326                 ibdev->uverbs_abi_ver);
3327
3328         if (ibdev->uverbs_abi_ver != BNXT_RE_ABI_VERSION) {
3329                 dev_dbg(rdev_to_dev(rdev), " is different from the device %d ",
3330                         BNXT_RE_ABI_VERSION);
3331                 return ERR_PTR(-EPERM);
3332         }
3333
3334         uctx = kzalloc(sizeof(*uctx), GFP_KERNEL);
3335         if (!uctx)
3336                 return ERR_PTR(-ENOMEM);
3337
3338         uctx->rdev = rdev;
3339
3340         uctx->shpg = (void *)__get_free_page(GFP_KERNEL);
3341         if (!uctx->shpg) {
3342                 rc = -ENOMEM;
3343                 goto fail;
3344         }
3345         spin_lock_init(&uctx->sh_lock);
3346
3347         resp.dev_id = rdev->en_dev->pdev->devfn; /*Temp, Use idr_alloc instead*/
3348         resp.max_qp = rdev->qplib_ctx.qpc_count;
3349         resp.pg_size = PAGE_SIZE;
3350         resp.cqe_sz = sizeof(struct cq_base);
3351         resp.max_cqd = dev_attr->max_cq_wqes;
3352         resp.rsvd    = 0;
3353
3354         rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
3355         if (rc) {
3356                 dev_err(rdev_to_dev(rdev), "Failed to copy user context");
3357                 rc = -EFAULT;
3358                 goto cfail;
3359         }
3360
3361         return &uctx->ib_uctx;
3362 cfail:
3363         free_page((unsigned long)uctx->shpg);
3364         uctx->shpg = NULL;
3365 fail:
3366         kfree(uctx);
3367         return ERR_PTR(rc);
3368 }
3369
3370 int bnxt_re_dealloc_ucontext(struct ib_ucontext *ib_uctx)
3371 {
3372         struct bnxt_re_ucontext *uctx = container_of(ib_uctx,
3373                                                    struct bnxt_re_ucontext,
3374                                                    ib_uctx);
3375
3376         struct bnxt_re_dev *rdev = uctx->rdev;
3377         int rc = 0;
3378
3379         if (uctx->shpg)
3380                 free_page((unsigned long)uctx->shpg);
3381
3382         if (uctx->dpi.dbr) {
3383                 /* Free DPI only if this is the first PD allocated by the
3384                  * application and mark the context dpi as NULL
3385                  */
3386                 rc = bnxt_qplib_dealloc_dpi(&rdev->qplib_res,
3387                                             &rdev->qplib_res.dpi_tbl,
3388                                             &uctx->dpi);
3389                 if (rc)
3390                         dev_err(rdev_to_dev(rdev), "Deallocte HW DPI failed!");
3391                         /* Don't fail, continue*/
3392                 uctx->dpi.dbr = NULL;
3393         }
3394
3395         kfree(uctx);
3396         return 0;
3397 }
3398
3399 /* Helper function to mmap the virtual memory from user app */
3400 int bnxt_re_mmap(struct ib_ucontext *ib_uctx, struct vm_area_struct *vma)
3401 {
3402         struct bnxt_re_ucontext *uctx = container_of(ib_uctx,
3403                                                    struct bnxt_re_ucontext,
3404                                                    ib_uctx);
3405         struct bnxt_re_dev *rdev = uctx->rdev;
3406         u64 pfn;
3407
3408         if (vma->vm_end - vma->vm_start != PAGE_SIZE)
3409                 return -EINVAL;
3410
3411         if (vma->vm_pgoff) {
3412                 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
3413                 if (io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
3414                                        PAGE_SIZE, vma->vm_page_prot)) {
3415                         dev_err(rdev_to_dev(rdev), "Failed to map DPI");
3416                         return -EAGAIN;
3417                 }
3418         } else {
3419                 pfn = virt_to_phys(uctx->shpg) >> PAGE_SHIFT;
3420                 if (remap_pfn_range(vma, vma->vm_start,
3421                                     pfn, PAGE_SIZE, vma->vm_page_prot)) {
3422                         dev_err(rdev_to_dev(rdev),
3423                                 "Failed to map shared page");
3424                         return -EAGAIN;
3425                 }
3426         }
3427
3428         return 0;
3429 }