2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
12 * Yaniv Kamay <yaniv@qumranet.com>
13 * Avi Kivity <avi@qumranet.com>
15 * This work is licensed under the terms of the GNU GPL, version 2. See
16 * the COPYING file in the top-level directory.
21 * We need the mmu code to access both 32-bit and 64-bit guest ptes,
22 * so the code in this file is compiled twice, once per pte size.
26 #define pt_element_t u64
27 #define guest_walker guest_walker64
28 #define FNAME(name) paging##64_##name
29 #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
30 #define PT_DIR_BASE_ADDR_MASK PT64_DIR_BASE_ADDR_MASK
31 #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
32 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
33 #define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level)
34 #define PT_LEVEL_BITS PT64_LEVEL_BITS
36 #define PT_MAX_FULL_LEVELS 4
37 #define CMPXCHG cmpxchg
39 #define CMPXCHG cmpxchg64
40 #define PT_MAX_FULL_LEVELS 2
43 #define pt_element_t u32
44 #define guest_walker guest_walker32
45 #define FNAME(name) paging##32_##name
46 #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
47 #define PT_DIR_BASE_ADDR_MASK PT32_DIR_BASE_ADDR_MASK
48 #define PT_INDEX(addr, level) PT32_INDEX(addr, level)
49 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
50 #define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level)
51 #define PT_LEVEL_BITS PT32_LEVEL_BITS
52 #define PT_MAX_FULL_LEVELS 2
53 #define CMPXCHG cmpxchg
55 #error Invalid PTTYPE value
58 #define gpte_to_gfn FNAME(gpte_to_gfn)
59 #define gpte_to_gfn_pde FNAME(gpte_to_gfn_pde)
62 * The guest_walker structure emulates the behavior of the hardware page
67 gfn_t table_gfn[PT_MAX_FULL_LEVELS];
75 static gfn_t gpte_to_gfn(pt_element_t gpte)
77 return (gpte & PT_BASE_ADDR_MASK) >> PAGE_SHIFT;
80 static gfn_t gpte_to_gfn_pde(pt_element_t gpte)
82 return (gpte & PT_DIR_BASE_ADDR_MASK) >> PAGE_SHIFT;
85 static bool FNAME(cmpxchg_gpte)(struct kvm *kvm,
86 gfn_t table_gfn, unsigned index,
87 pt_element_t orig_pte, pt_element_t new_pte)
93 page = gfn_to_page(kvm, table_gfn);
94 table = kmap_atomic(page, KM_USER0);
96 ret = CMPXCHG(&table[index], orig_pte, new_pte);
98 kunmap_atomic(table, KM_USER0);
100 kvm_release_page_dirty(page);
102 return (ret != orig_pte);
106 * Fetch a guest pte for a guest virtual address
108 static int FNAME(walk_addr)(struct guest_walker *walker,
109 struct kvm_vcpu *vcpu, gva_t addr,
110 int write_fault, int user_fault, int fetch_fault)
114 unsigned index, pt_access, pte_access;
117 pgprintk("%s: addr %lx\n", __FUNCTION__, addr);
119 walker->level = vcpu->mmu.root_level;
122 if (!is_long_mode(vcpu)) {
123 pte = vcpu->pdptrs[(addr >> 30) & 3];
124 if (!is_present_pte(pte))
129 ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) ||
130 (vcpu->cr3 & CR3_NONPAE_RESERVED_BITS) == 0);
135 index = PT_INDEX(addr, walker->level);
137 table_gfn = gpte_to_gfn(pte);
138 pte_gpa = gfn_to_gpa(table_gfn);
139 pte_gpa += index * sizeof(pt_element_t);
140 walker->table_gfn[walker->level - 1] = table_gfn;
141 pgprintk("%s: table_gfn[%d] %lx\n", __FUNCTION__,
142 walker->level - 1, table_gfn);
144 kvm_read_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte));
146 if (!is_present_pte(pte))
149 if (write_fault && !is_writeble_pte(pte))
150 if (user_fault || is_write_protection(vcpu))
153 if (user_fault && !(pte & PT_USER_MASK))
157 if (fetch_fault && is_nx(vcpu) && (pte & PT64_NX_MASK))
161 if (!(pte & PT_ACCESSED_MASK)) {
162 mark_page_dirty(vcpu->kvm, table_gfn);
163 if (FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn,
164 index, pte, pte|PT_ACCESSED_MASK))
166 pte |= PT_ACCESSED_MASK;
169 pte_access = pte & (PT_WRITABLE_MASK | PT_USER_MASK);
170 pte_access |= ACC_EXEC_MASK;
173 pte_access &= ~(pte >> PT64_NX_SHIFT);
175 pte_access &= pt_access;
177 if (walker->level == PT_PAGE_TABLE_LEVEL) {
178 walker->gfn = gpte_to_gfn(pte);
182 if (walker->level == PT_DIRECTORY_LEVEL
183 && (pte & PT_PAGE_SIZE_MASK)
184 && (PTTYPE == 64 || is_pse(vcpu))) {
185 walker->gfn = gpte_to_gfn_pde(pte);
186 walker->gfn += PT_INDEX(addr, PT_PAGE_TABLE_LEVEL);
187 if (PTTYPE == 32 && is_cpuid_PSE36())
188 walker->gfn += pse36_gfn_delta(pte);
192 pt_access = pte_access;
196 if (write_fault && !is_dirty_pte(pte)) {
199 mark_page_dirty(vcpu->kvm, table_gfn);
200 ret = FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn, index, pte,
204 pte |= PT_DIRTY_MASK;
205 kvm_mmu_pte_write(vcpu, pte_gpa, (u8 *)&pte, sizeof(pte));
209 walker->pt_access = pt_access;
210 walker->pte_access = pte_access;
211 pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
212 __FUNCTION__, (u64)pte, pt_access, pte_access);
216 walker->error_code = 0;
220 walker->error_code = PFERR_PRESENT_MASK;
224 walker->error_code |= PFERR_WRITE_MASK;
226 walker->error_code |= PFERR_USER_MASK;
228 walker->error_code |= PFERR_FETCH_MASK;
232 static void FNAME(set_pte)(struct kvm_vcpu *vcpu, pt_element_t gpte,
233 u64 *shadow_pte, unsigned pt_access,
235 int user_fault, int write_fault,
236 int *ptwrite, struct guest_walker *walker,
239 int dirty = gpte & PT_DIRTY_MASK;
241 int was_rmapped = is_rmap_pte(*shadow_pte);
244 pgprintk("%s: spte %llx gpte %llx access %x write_fault %d"
245 " user_fault %d gfn %lx\n",
246 __FUNCTION__, *shadow_pte, (u64)gpte, pt_access,
247 write_fault, user_fault, gfn);
250 * We don't set the accessed bit, since we sometimes want to see
251 * whether the guest actually used the pte (in order to detect
254 spte = PT_PRESENT_MASK | PT_DIRTY_MASK;
255 spte |= gpte & PT64_NX_MASK;
257 pte_access &= ~ACC_WRITE_MASK;
259 page = gfn_to_page(vcpu->kvm, gfn);
261 spte |= PT_PRESENT_MASK;
262 if (pte_access & ACC_USER_MASK)
263 spte |= PT_USER_MASK;
265 if (is_error_page(page)) {
266 set_shadow_pte(shadow_pte,
267 shadow_trap_nonpresent_pte | PT_SHADOW_IO_MARK);
268 kvm_release_page_clean(page);
272 spte |= page_to_phys(page);
274 if ((pte_access & ACC_WRITE_MASK)
275 || (write_fault && !is_write_protection(vcpu) && !user_fault)) {
276 struct kvm_mmu_page *shadow;
278 spte |= PT_WRITABLE_MASK;
280 mmu_unshadow(vcpu->kvm, gfn);
284 shadow = kvm_mmu_lookup_page(vcpu->kvm, gfn);
286 pgprintk("%s: found shadow page for %lx, marking ro\n",
288 pte_access &= ~ACC_WRITE_MASK;
289 if (is_writeble_pte(spte)) {
290 spte &= ~PT_WRITABLE_MASK;
291 kvm_x86_ops->tlb_flush(vcpu);
300 if (pte_access & ACC_WRITE_MASK)
301 mark_page_dirty(vcpu->kvm, gfn);
303 pgprintk("%s: setting spte %llx\n", __FUNCTION__, spte);
304 set_shadow_pte(shadow_pte, spte);
305 page_header_update_slot(vcpu->kvm, shadow_pte, gfn);
307 rmap_add(vcpu, shadow_pte, gfn);
308 if (!is_rmap_pte(*shadow_pte))
309 kvm_release_page_clean(page);
312 kvm_release_page_clean(page);
313 if (!ptwrite || !*ptwrite)
314 vcpu->last_pte_updated = shadow_pte;
317 static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *page,
318 u64 *spte, const void *pte, int bytes,
323 gpte = *(const pt_element_t *)pte;
324 if (~gpte & (PT_PRESENT_MASK | PT_ACCESSED_MASK)) {
325 if (!offset_in_pte && !is_present_pte(gpte))
326 set_shadow_pte(spte, shadow_notrap_nonpresent_pte);
329 if (bytes < sizeof(pt_element_t))
331 pgprintk("%s: gpte %llx spte %p\n", __FUNCTION__, (u64)gpte, spte);
332 FNAME(set_pte)(vcpu, gpte, spte, ACC_ALL, ACC_ALL,
333 0, 0, NULL, NULL, gpte_to_gfn(gpte));
337 * Fetch a shadow pte for a specific level in the paging hierarchy.
339 static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
340 struct guest_walker *walker,
341 int user_fault, int write_fault, int *ptwrite)
346 unsigned access = walker->pt_access;
348 if (!is_present_pte(walker->pte))
351 shadow_addr = vcpu->mmu.root_hpa;
352 level = vcpu->mmu.shadow_root_level;
353 if (level == PT32E_ROOT_LEVEL) {
354 shadow_addr = vcpu->mmu.pae_root[(addr >> 30) & 3];
355 shadow_addr &= PT64_BASE_ADDR_MASK;
360 u32 index = SHADOW_PT_INDEX(addr, level);
361 struct kvm_mmu_page *shadow_page;
366 shadow_ent = ((u64 *)__va(shadow_addr)) + index;
367 if (is_shadow_present_pte(*shadow_ent)) {
368 if (level == PT_PAGE_TABLE_LEVEL)
370 shadow_addr = *shadow_ent & PT64_BASE_ADDR_MASK;
374 if (level == PT_PAGE_TABLE_LEVEL)
377 if (level - 1 == PT_PAGE_TABLE_LEVEL
378 && walker->level == PT_DIRECTORY_LEVEL) {
380 if (!is_dirty_pte(walker->pte))
381 access &= ~ACC_WRITE_MASK;
382 table_gfn = gpte_to_gfn(walker->pte);
385 table_gfn = walker->table_gfn[level - 2];
387 shadow_page = kvm_mmu_get_page(vcpu, table_gfn, addr, level-1,
388 metaphysical, access,
390 shadow_addr = __pa(shadow_page->spt);
391 shadow_pte = shadow_addr | PT_PRESENT_MASK | PT_ACCESSED_MASK
392 | PT_WRITABLE_MASK | PT_USER_MASK;
393 *shadow_ent = shadow_pte;
396 FNAME(set_pte)(vcpu, walker->pte, shadow_ent,
397 access, walker->pte_access & access,
398 user_fault, write_fault,
399 ptwrite, walker, walker->gfn);
405 * Page fault handler. There are several causes for a page fault:
406 * - there is no shadow pte for the guest pte
407 * - write access through a shadow pte marked read only so that we can set
409 * - write access to a shadow pte marked read only so we can update the page
410 * dirty bitmap, when userspace requests it
411 * - mmio access; in this case we will never install a present shadow pte
412 * - normal guest page fault due to the guest pte marked not present, not
413 * writable, or not executable
415 * Returns: 1 if we need to emulate the instruction, 0 otherwise, or
416 * a negative value on error.
418 static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
421 int write_fault = error_code & PFERR_WRITE_MASK;
422 int user_fault = error_code & PFERR_USER_MASK;
423 int fetch_fault = error_code & PFERR_FETCH_MASK;
424 struct guest_walker walker;
429 pgprintk("%s: addr %lx err %x\n", __FUNCTION__, addr, error_code);
430 kvm_mmu_audit(vcpu, "pre page fault");
432 r = mmu_topup_memory_caches(vcpu);
437 * Look up the shadow pte for the faulting address.
439 r = FNAME(walk_addr)(&walker, vcpu, addr, write_fault, user_fault,
443 * The page is not mapped by the guest. Let the guest handle it.
446 pgprintk("%s: guest page fault\n", __FUNCTION__);
447 inject_page_fault(vcpu, addr, walker.error_code);
448 vcpu->last_pt_write_count = 0; /* reset fork detector */
452 shadow_pte = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
454 pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __FUNCTION__,
455 shadow_pte, *shadow_pte, write_pt);
458 vcpu->last_pt_write_count = 0; /* reset fork detector */
461 * mmio: emulate if accessible, otherwise its a guest fault.
463 if (is_io_pte(*shadow_pte))
466 ++vcpu->stat.pf_fixed;
467 kvm_mmu_audit(vcpu, "post page fault (fixed)");
472 static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr)
474 struct guest_walker walker;
475 gpa_t gpa = UNMAPPED_GVA;
478 r = FNAME(walk_addr)(&walker, vcpu, vaddr, 0, 0, 0);
481 gpa = gfn_to_gpa(walker.gfn);
482 gpa |= vaddr & ~PAGE_MASK;
488 static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu,
489 struct kvm_mmu_page *sp)
495 if (sp->role.metaphysical
496 || (PTTYPE == 32 && sp->role.level > PT_PAGE_TABLE_LEVEL)) {
497 nonpaging_prefetch_page(vcpu, sp);
502 offset = sp->role.quadrant << PT64_LEVEL_BITS;
503 page = gfn_to_page(vcpu->kvm, sp->gfn);
504 gpt = kmap_atomic(page, KM_USER0);
505 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
506 if (is_present_pte(gpt[offset + i]))
507 sp->spt[i] = shadow_trap_nonpresent_pte;
509 sp->spt[i] = shadow_notrap_nonpresent_pte;
510 kunmap_atomic(gpt, KM_USER0);
511 kvm_release_page_clean(page);
517 #undef PT_BASE_ADDR_MASK
519 #undef SHADOW_PT_INDEX
521 #undef PT_DIR_BASE_ADDR_MASK
523 #undef PT_MAX_FULL_LEVELS
525 #undef gpte_to_gfn_pde