drivers/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  *
   9  * Authors:
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *   Yaniv Kamay  <yaniv@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17
  18 #include "kvm.h"
  19 #include "x86.h"
  20 #include "x86_emulate.h"
  21 #include "irq.h"
  22 #include "vmx.h"
  23 #include "segment_descriptor.h"
  24
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/mm.h>
  28 #include <linux/highmem.h>
  29 #include <linux/sched.h>
  30 #include <linux/moduleparam.h>
  31
  32 #include <asm/io.h>
  33 #include <asm/desc.h>
  34
  35 MODULE_AUTHOR("Qumranet");
  36 MODULE_LICENSE("GPL");
  37
  38 static int bypass_guest_pf = 1;
  39 module_param(bypass_guest_pf, bool, 0);
  40
  41 struct vmcs {
  42         u32 revision_id;
  43         u32 abort;
  44         char data[0];
  45 };
  46
  47 struct vcpu_vmx {
  48         struct kvm_vcpu       vcpu;
  49         int                   launched;
  50         u8                    fail;
  51         u32                   idt_vectoring_info;
  52         struct kvm_msr_entry *guest_msrs;
  53         struct kvm_msr_entry *host_msrs;
  54         int                   nmsrs;
  55         int                   save_nmsrs;
  56         int                   msr_offset_efer;
  57 #ifdef CONFIG_X86_64
  58         int                   msr_offset_kernel_gs_base;
  59 #endif
  60         struct vmcs          *vmcs;
  61         struct {
  62                 int           loaded;
  63                 u16           fs_sel, gs_sel, ldt_sel;
  64                 int           gs_ldt_reload_needed;
  65                 int           fs_reload_needed;
  66                 int           guest_efer_loaded;
  67         } host_state;
  68         struct {
  69                 struct {
  70                         bool pending;
  71                         u8 vector;
  72                         unsigned rip;
  73                 } irq;
  74         } rmode;
  75 };
  76
  77 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
  78 {
  79         return container_of(vcpu, struct vcpu_vmx, vcpu);
  80 }
  81
  82 static int init_rmode_tss(struct kvm *kvm);
  83
  84 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
  85 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
  86
  87 static struct page *vmx_io_bitmap_a;
  88 static struct page *vmx_io_bitmap_b;
  89
  90 static struct vmcs_config {
  91         int size;
  92         int order;
  93         u32 revision_id;
  94         u32 pin_based_exec_ctrl;
  95         u32 cpu_based_exec_ctrl;
  96         u32 cpu_based_2nd_exec_ctrl;
  97         u32 vmexit_ctrl;
  98         u32 vmentry_ctrl;
  99 } vmcs_config;
 100
 101 #define VMX_SEGMENT_FIELD(seg)                                  \
 102         [VCPU_SREG_##seg] = {                                   \
 103                 .selector = GUEST_##seg##_SELECTOR,             \
 104                 .base = GUEST_##seg##_BASE,                     \
 105                 .limit = GUEST_##seg##_LIMIT,                   \
 106                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 107         }
 108
 109 static struct kvm_vmx_segment_field {
 110         unsigned selector;
 111         unsigned base;
 112         unsigned limit;
 113         unsigned ar_bytes;
 114 } kvm_vmx_segment_fields[] = {
 115         VMX_SEGMENT_FIELD(CS),
 116         VMX_SEGMENT_FIELD(DS),
 117         VMX_SEGMENT_FIELD(ES),
 118         VMX_SEGMENT_FIELD(FS),
 119         VMX_SEGMENT_FIELD(GS),
 120         VMX_SEGMENT_FIELD(SS),
 121         VMX_SEGMENT_FIELD(TR),
 122         VMX_SEGMENT_FIELD(LDTR),
 123 };
 124
 125 /*
 126  * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
 127  * away by decrementing the array size.
 128  */
 129 static const u32 vmx_msr_index[] = {
 130 #ifdef CONFIG_X86_64
 131         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
 132 #endif
 133         MSR_EFER, MSR_K6_STAR,
 134 };
 135 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 136
 137 static void load_msrs(struct kvm_msr_entry *e, int n)
 138 {
 139         int i;
 140
 141         for (i = 0; i < n; ++i)
 142                 wrmsrl(e[i].index, e[i].data);
 143 }
 144
 145 static void save_msrs(struct kvm_msr_entry *e, int n)
 146 {
 147         int i;
 148
 149         for (i = 0; i < n; ++i)
 150                 rdmsrl(e[i].index, e[i].data);
 151 }
 152
 153 static inline int is_page_fault(u32 intr_info)
 154 {
 155         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 156                              INTR_INFO_VALID_MASK)) ==
 157                 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 158 }
 159
 160 static inline int is_no_device(u32 intr_info)
 161 {
 162         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 163                              INTR_INFO_VALID_MASK)) ==
 164                 (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 165 }
 166
 167 static inline int is_invalid_opcode(u32 intr_info)
 168 {
 169         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 170                              INTR_INFO_VALID_MASK)) ==
 171                 (INTR_TYPE_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 172 }
 173
 174 static inline int is_external_interrupt(u32 intr_info)
 175 {
 176         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 177                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 178 }
 179
 180 static inline int cpu_has_vmx_tpr_shadow(void)
 181 {
 182         return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW);
 183 }
 184
 185 static inline int vm_need_tpr_shadow(struct kvm *kvm)
 186 {
 187         return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)));
 188 }
 189
 190 static inline int cpu_has_secondary_exec_ctrls(void)
 191 {
 192         return (vmcs_config.cpu_based_exec_ctrl &
 193                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS);
 194 }
 195
 196 static inline int cpu_has_vmx_virtualize_apic_accesses(void)
 197 {
 198         return (vmcs_config.cpu_based_2nd_exec_ctrl &
 199                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
 200 }
 201
 202 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
 203 {
 204         return ((cpu_has_vmx_virtualize_apic_accesses()) &&
 205                 (irqchip_in_kernel(kvm)));
 206 }
 207
 208 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 209 {
 210         int i;
 211
 212         for (i = 0; i < vmx->nmsrs; ++i)
 213                 if (vmx->guest_msrs[i].index == msr)
 214                         return i;
 215         return -1;
 216 }
 217
 218 static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 219 {
 220         int i;
 221
 222         i = __find_msr_index(vmx, msr);
 223         if (i >= 0)
 224                 return &vmx->guest_msrs[i];
 225         return NULL;
 226 }
 227
 228 static void vmcs_clear(struct vmcs *vmcs)
 229 {
 230         u64 phys_addr = __pa(vmcs);
 231         u8 error;
 232
 233         asm volatile (ASM_VMX_VMCLEAR_RAX "; setna %0"
 234                       : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 235                       : "cc", "memory");
 236         if (error)
 237                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 238                        vmcs, phys_addr);
 239 }
 240
 241 static void __vcpu_clear(void *arg)
 242 {
 243         struct vcpu_vmx *vmx = arg;
 244         int cpu = raw_smp_processor_id();
 245
 246         if (vmx->vcpu.cpu == cpu)
 247                 vmcs_clear(vmx->vmcs);
 248         if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
 249                 per_cpu(current_vmcs, cpu) = NULL;
 250         rdtscll(vmx->vcpu.host_tsc);
 251 }
 252
 253 static void vcpu_clear(struct vcpu_vmx *vmx)
 254 {
 255         if (vmx->vcpu.cpu == -1)
 256                 return;
 257         smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 0, 1);
 258         vmx->launched = 0;
 259 }
 260
 261 static unsigned long vmcs_readl(unsigned long field)
 262 {
 263         unsigned long value;
 264
 265         asm volatile (ASM_VMX_VMREAD_RDX_RAX
 266                       : "=a"(value) : "d"(field) : "cc");
 267         return value;
 268 }
 269
 270 static u16 vmcs_read16(unsigned long field)
 271 {
 272         return vmcs_readl(field);
 273 }
 274
 275 static u32 vmcs_read32(unsigned long field)
 276 {
 277         return vmcs_readl(field);
 278 }
 279
 280 static u64 vmcs_read64(unsigned long field)
 281 {
 282 #ifdef CONFIG_X86_64
 283         return vmcs_readl(field);
 284 #else
 285         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
 286 #endif
 287 }
 288
 289 static noinline void vmwrite_error(unsigned long field, unsigned long value)
 290 {
 291         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
 292                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 293         dump_stack();
 294 }
 295
 296 static void vmcs_writel(unsigned long field, unsigned long value)
 297 {
 298         u8 error;
 299
 300         asm volatile (ASM_VMX_VMWRITE_RAX_RDX "; setna %0"
 301                        : "=q"(error) : "a"(value), "d"(field) : "cc");
 302         if (unlikely(error))
 303                 vmwrite_error(field, value);
 304 }
 305
 306 static void vmcs_write16(unsigned long field, u16 value)
 307 {
 308         vmcs_writel(field, value);
 309 }
 310
 311 static void vmcs_write32(unsigned long field, u32 value)
 312 {
 313         vmcs_writel(field, value);
 314 }
 315
 316 static void vmcs_write64(unsigned long field, u64 value)
 317 {
 318 #ifdef CONFIG_X86_64
 319         vmcs_writel(field, value);
 320 #else
 321         vmcs_writel(field, value);
 322         asm volatile ("");
 323         vmcs_writel(field+1, value >> 32);
 324 #endif
 325 }
 326
 327 static void vmcs_clear_bits(unsigned long field, u32 mask)
 328 {
 329         vmcs_writel(field, vmcs_readl(field) & ~mask);
 330 }
 331
 332 static void vmcs_set_bits(unsigned long field, u32 mask)
 333 {
 334         vmcs_writel(field, vmcs_readl(field) | mask);
 335 }
 336
 337 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
 338 {
 339         u32 eb;
 340
 341         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR);
 342         if (!vcpu->fpu_active)
 343                 eb |= 1u << NM_VECTOR;
 344         if (vcpu->guest_debug.enabled)
 345                 eb |= 1u << 1;
 346         if (vcpu->rmode.active)
 347                 eb = ~0;
 348         vmcs_write32(EXCEPTION_BITMAP, eb);
 349 }
 350
 351 static void reload_tss(void)
 352 {
 353 #ifndef CONFIG_X86_64
 354
 355         /*
 356          * VT restores TR but not its size.  Useless.
 357          */
 358         struct descriptor_table gdt;
 359         struct segment_descriptor *descs;
 360
 361         get_gdt(&gdt);
 362         descs = (void *)gdt.base;
 363         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
 364         load_TR_desc();
 365 #endif
 366 }
 367
 368 static void load_transition_efer(struct vcpu_vmx *vmx)
 369 {
 370         int efer_offset = vmx->msr_offset_efer;
 371         u64 host_efer = vmx->host_msrs[efer_offset].data;
 372         u64 guest_efer = vmx->guest_msrs[efer_offset].data;
 373         u64 ignore_bits;
 374
 375         if (efer_offset < 0)
 376                 return;
 377         /*
 378          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
 379          * outside long mode
 380          */
 381         ignore_bits = EFER_NX | EFER_SCE;
 382 #ifdef CONFIG_X86_64
 383         ignore_bits |= EFER_LMA | EFER_LME;
 384         /* SCE is meaningful only in long mode on Intel */
 385         if (guest_efer & EFER_LMA)
 386                 ignore_bits &= ~(u64)EFER_SCE;
 387 #endif
 388         if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
 389                 return;
 390
 391         vmx->host_state.guest_efer_loaded = 1;
 392         guest_efer &= ~ignore_bits;
 393         guest_efer |= host_efer & ignore_bits;
 394         wrmsrl(MSR_EFER, guest_efer);
 395         vmx->vcpu.stat.efer_reload++;
 396 }
 397
 398 static void reload_host_efer(struct vcpu_vmx *vmx)
 399 {
 400         if (vmx->host_state.guest_efer_loaded) {
 401                 vmx->host_state.guest_efer_loaded = 0;
 402                 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
 403         }
 404 }
 405
 406 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
 407 {
 408         struct vcpu_vmx *vmx = to_vmx(vcpu);
 409
 410         if (vmx->host_state.loaded)
 411                 return;
 412
 413         vmx->host_state.loaded = 1;
 414         /*
 415          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
 416          * allow segment selectors with cpl > 0 or ti == 1.
 417          */
 418         vmx->host_state.ldt_sel = read_ldt();
 419         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
 420         vmx->host_state.fs_sel = read_fs();
 421         if (!(vmx->host_state.fs_sel & 7)) {
 422                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
 423                 vmx->host_state.fs_reload_needed = 0;
 424         } else {
 425                 vmcs_write16(HOST_FS_SELECTOR, 0);
 426                 vmx->host_state.fs_reload_needed = 1;
 427         }
 428         vmx->host_state.gs_sel = read_gs();
 429         if (!(vmx->host_state.gs_sel & 7))
 430                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
 431         else {
 432                 vmcs_write16(HOST_GS_SELECTOR, 0);
 433                 vmx->host_state.gs_ldt_reload_needed = 1;
 434         }
 435
 436 #ifdef CONFIG_X86_64
 437         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
 438         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
 439 #else
 440         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
 441         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
 442 #endif
 443
 444 #ifdef CONFIG_X86_64
 445         if (is_long_mode(&vmx->vcpu))
 446                 save_msrs(vmx->host_msrs +
 447                           vmx->msr_offset_kernel_gs_base, 1);
 448
 449 #endif
 450         load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 451         load_transition_efer(vmx);
 452 }
 453
 454 static void vmx_load_host_state(struct vcpu_vmx *vmx)
 455 {
 456         unsigned long flags;
 457
 458         if (!vmx->host_state.loaded)
 459                 return;
 460
 461         ++vmx->vcpu.stat.host_state_reload;
 462         vmx->host_state.loaded = 0;
 463         if (vmx->host_state.fs_reload_needed)
 464                 load_fs(vmx->host_state.fs_sel);
 465         if (vmx->host_state.gs_ldt_reload_needed) {
 466                 load_ldt(vmx->host_state.ldt_sel);
 467                 /*
 468                  * If we have to reload gs, we must take care to
 469                  * preserve our gs base.
 470                  */
 471                 local_irq_save(flags);
 472                 load_gs(vmx->host_state.gs_sel);
 473 #ifdef CONFIG_X86_64
 474                 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
 475 #endif
 476                 local_irq_restore(flags);
 477         }
 478         reload_tss();
 479         save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 480         load_msrs(vmx->host_msrs, vmx->save_nmsrs);
 481         reload_host_efer(vmx);
 482 }
 483
 484 /*
 485  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
 486  * vcpu mutex is already taken.
 487  */
 488 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 489 {
 490         struct vcpu_vmx *vmx = to_vmx(vcpu);
 491         u64 phys_addr = __pa(vmx->vmcs);
 492         u64 tsc_this, delta;
 493
 494         if (vcpu->cpu != cpu) {
 495                 vcpu_clear(vmx);
 496                 kvm_migrate_apic_timer(vcpu);
 497         }
 498
 499         if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
 500                 u8 error;
 501
 502                 per_cpu(current_vmcs, cpu) = vmx->vmcs;
 503                 asm volatile (ASM_VMX_VMPTRLD_RAX "; setna %0"
 504                               : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 505                               : "cc");
 506                 if (error)
 507                         printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
 508                                vmx->vmcs, phys_addr);
 509         }
 510
 511         if (vcpu->cpu != cpu) {
 512                 struct descriptor_table dt;
 513                 unsigned long sysenter_esp;
 514
 515                 vcpu->cpu = cpu;
 516                 /*
 517                  * Linux uses per-cpu TSS and GDT, so set these when switching
 518                  * processors.
 519                  */
 520                 vmcs_writel(HOST_TR_BASE, read_tr_base()); /* 22.2.4 */
 521                 get_gdt(&dt);
 522                 vmcs_writel(HOST_GDTR_BASE, dt.base);   /* 22.2.4 */
 523
 524                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
 525                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
 526
 527                 /*
 528                  * Make sure the time stamp counter is monotonous.
 529                  */
 530                 rdtscll(tsc_this);
 531                 delta = vcpu->host_tsc - tsc_this;
 532                 vmcs_write64(TSC_OFFSET, vmcs_read64(TSC_OFFSET) + delta);
 533         }
 534 }
 535
 536 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
 537 {
 538         vmx_load_host_state(to_vmx(vcpu));
 539 }
 540
 541 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
 542 {
 543         if (vcpu->fpu_active)
 544                 return;
 545         vcpu->fpu_active = 1;
 546         vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
 547         if (vcpu->cr0 & X86_CR0_TS)
 548                 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 549         update_exception_bitmap(vcpu);
 550 }
 551
 552 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
 553 {
 554         if (!vcpu->fpu_active)
 555                 return;
 556         vcpu->fpu_active = 0;
 557         vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 558         update_exception_bitmap(vcpu);
 559 }
 560
 561 static void vmx_vcpu_decache(struct kvm_vcpu *vcpu)
 562 {
 563         vcpu_clear(to_vmx(vcpu));
 564 }
 565
 566 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
 567 {
 568         return vmcs_readl(GUEST_RFLAGS);
 569 }
 570
 571 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 572 {
 573         if (vcpu->rmode.active)
 574                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
 575         vmcs_writel(GUEST_RFLAGS, rflags);
 576 }
 577
 578 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 579 {
 580         unsigned long rip;
 581         u32 interruptibility;
 582
 583         rip = vmcs_readl(GUEST_RIP);
 584         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
 585         vmcs_writel(GUEST_RIP, rip);
 586
 587         /*
 588          * We emulated an instruction, so temporary interrupt blocking
 589          * should be removed, if set.
 590          */
 591         interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 592         if (interruptibility & 3)
 593                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
 594                              interruptibility & ~3);
 595         vcpu->interrupt_window_open = 1;
 596 }
 597
 598 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 599                                 bool has_error_code, u32 error_code)
 600 {
 601         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
 602                      nr | INTR_TYPE_EXCEPTION
 603                      | (has_error_code ? INTR_INFO_DELIEVER_CODE_MASK : 0)
 604                      | INTR_INFO_VALID_MASK);
 605         if (has_error_code)
 606                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
 607 }
 608
 609 static bool vmx_exception_injected(struct kvm_vcpu *vcpu)
 610 {
 611         struct vcpu_vmx *vmx = to_vmx(vcpu);
 612
 613         return !(vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
 614 }
 615
 616 /*
 617  * Swap MSR entry in host/guest MSR entry array.
 618  */
 619 #ifdef CONFIG_X86_64
 620 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
 621 {
 622         struct kvm_msr_entry tmp;
 623
 624         tmp = vmx->guest_msrs[to];
 625         vmx->guest_msrs[to] = vmx->guest_msrs[from];
 626         vmx->guest_msrs[from] = tmp;
 627         tmp = vmx->host_msrs[to];
 628         vmx->host_msrs[to] = vmx->host_msrs[from];
 629         vmx->host_msrs[from] = tmp;
 630 }
 631 #endif
 632
 633 /*
 634  * Set up the vmcs to automatically save and restore system
 635  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
 636  * mode, as fiddling with msrs is very expensive.
 637  */
 638 static void setup_msrs(struct vcpu_vmx *vmx)
 639 {
 640         int save_nmsrs;
 641
 642         save_nmsrs = 0;
 643 #ifdef CONFIG_X86_64
 644         if (is_long_mode(&vmx->vcpu)) {
 645                 int index;
 646
 647                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
 648                 if (index >= 0)
 649                         move_msr_up(vmx, index, save_nmsrs++);
 650                 index = __find_msr_index(vmx, MSR_LSTAR);
 651                 if (index >= 0)
 652                         move_msr_up(vmx, index, save_nmsrs++);
 653                 index = __find_msr_index(vmx, MSR_CSTAR);
 654                 if (index >= 0)
 655                         move_msr_up(vmx, index, save_nmsrs++);
 656                 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
 657                 if (index >= 0)
 658                         move_msr_up(vmx, index, save_nmsrs++);
 659                 /*
 660                  * MSR_K6_STAR is only needed on long mode guests, and only
 661                  * if efer.sce is enabled.
 662                  */
 663                 index = __find_msr_index(vmx, MSR_K6_STAR);
 664                 if ((index >= 0) && (vmx->vcpu.shadow_efer & EFER_SCE))
 665                         move_msr_up(vmx, index, save_nmsrs++);
 666         }
 667 #endif
 668         vmx->save_nmsrs = save_nmsrs;
 669
 670 #ifdef CONFIG_X86_64
 671         vmx->msr_offset_kernel_gs_base =
 672                 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
 673 #endif
 674         vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
 675 }
 676
 677 /*
 678  * reads and returns guest's timestamp counter "register"
 679  * guest_tsc = host_tsc + tsc_offset    -- 21.3
 680  */
 681 static u64 guest_read_tsc(void)
 682 {
 683         u64 host_tsc, tsc_offset;
 684
 685         rdtscll(host_tsc);
 686         tsc_offset = vmcs_read64(TSC_OFFSET);
 687         return host_tsc + tsc_offset;
 688 }
 689
 690 /*
 691  * writes 'guest_tsc' into guest's timestamp counter "register"
 692  * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
 693  */
 694 static void guest_write_tsc(u64 guest_tsc)
 695 {
 696         u64 host_tsc;
 697
 698         rdtscll(host_tsc);
 699         vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
 700 }
 701
 702 /*
 703  * Reads an msr value (of 'msr_index') into 'pdata'.
 704  * Returns 0 on success, non-0 otherwise.
 705  * Assumes vcpu_load() was already called.
 706  */
 707 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
 708 {
 709         u64 data;
 710         struct kvm_msr_entry *msr;
 711
 712         if (!pdata) {
 713                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
 714                 return -EINVAL;
 715         }
 716
 717         switch (msr_index) {
 718 #ifdef CONFIG_X86_64
 719         case MSR_FS_BASE:
 720                 data = vmcs_readl(GUEST_FS_BASE);
 721                 break;
 722         case MSR_GS_BASE:
 723                 data = vmcs_readl(GUEST_GS_BASE);
 724                 break;
 725         case MSR_EFER:
 726                 return kvm_get_msr_common(vcpu, msr_index, pdata);
 727 #endif
 728         case MSR_IA32_TIME_STAMP_COUNTER:
 729                 data = guest_read_tsc();
 730                 break;
 731         case MSR_IA32_SYSENTER_CS:
 732                 data = vmcs_read32(GUEST_SYSENTER_CS);
 733                 break;
 734         case MSR_IA32_SYSENTER_EIP:
 735                 data = vmcs_readl(GUEST_SYSENTER_EIP);
 736                 break;
 737         case MSR_IA32_SYSENTER_ESP:
 738                 data = vmcs_readl(GUEST_SYSENTER_ESP);
 739                 break;
 740         default:
 741                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
 742                 if (msr) {
 743                         data = msr->data;
 744                         break;
 745                 }
 746                 return kvm_get_msr_common(vcpu, msr_index, pdata);
 747         }
 748
 749         *pdata = data;
 750         return 0;
 751 }
 752
 753 /*
 754  * Writes msr value into into the appropriate "register".
 755  * Returns 0 on success, non-0 otherwise.
 756  * Assumes vcpu_load() was already called.
 757  */
 758 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
 759 {
 760         struct vcpu_vmx *vmx = to_vmx(vcpu);
 761         struct kvm_msr_entry *msr;
 762         int ret = 0;
 763
 764         switch (msr_index) {
 765 #ifdef CONFIG_X86_64
 766         case MSR_EFER:
 767                 ret = kvm_set_msr_common(vcpu, msr_index, data);
 768                 if (vmx->host_state.loaded) {
 769                         reload_host_efer(vmx);
 770                         load_transition_efer(vmx);
 771                 }
 772                 break;
 773         case MSR_FS_BASE:
 774                 vmcs_writel(GUEST_FS_BASE, data);
 775                 break;
 776         case MSR_GS_BASE:
 777                 vmcs_writel(GUEST_GS_BASE, data);
 778                 break;
 779 #endif
 780         case MSR_IA32_SYSENTER_CS:
 781                 vmcs_write32(GUEST_SYSENTER_CS, data);
 782                 break;
 783         case MSR_IA32_SYSENTER_EIP:
 784                 vmcs_writel(GUEST_SYSENTER_EIP, data);
 785                 break;
 786         case MSR_IA32_SYSENTER_ESP:
 787                 vmcs_writel(GUEST_SYSENTER_ESP, data);
 788                 break;
 789         case MSR_IA32_TIME_STAMP_COUNTER:
 790                 guest_write_tsc(data);
 791                 break;
 792         default:
 793                 msr = find_msr_entry(vmx, msr_index);
 794                 if (msr) {
 795                         msr->data = data;
 796                         if (vmx->host_state.loaded)
 797                                 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 798                         break;
 799                 }
 800                 ret = kvm_set_msr_common(vcpu, msr_index, data);
 801         }
 802
 803         return ret;
 804 }
 805
 806 /*
 807  * Sync the rsp and rip registers into the vcpu structure.  This allows
 808  * registers to be accessed by indexing vcpu->regs.
 809  */
 810 static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu)
 811 {
 812         vcpu->regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
 813         vcpu->rip = vmcs_readl(GUEST_RIP);
 814 }
 815
 816 /*
 817  * Syncs rsp and rip back into the vmcs.  Should be called after possible
 818  * modification.
 819  */
 820 static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu)
 821 {
 822         vmcs_writel(GUEST_RSP, vcpu->regs[VCPU_REGS_RSP]);
 823         vmcs_writel(GUEST_RIP, vcpu->rip);
 824 }
 825
 826 static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
 827 {
 828         unsigned long dr7 = 0x400;
 829         int old_singlestep;
 830
 831         old_singlestep = vcpu->guest_debug.singlestep;
 832
 833         vcpu->guest_debug.enabled = dbg->enabled;
 834         if (vcpu->guest_debug.enabled) {
 835                 int i;
 836
 837                 dr7 |= 0x200;  /* exact */
 838                 for (i = 0; i < 4; ++i) {
 839                         if (!dbg->breakpoints[i].enabled)
 840                                 continue;
 841                         vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
 842                         dr7 |= 2 << (i*2);    /* global enable */
 843                         dr7 |= 0 << (i*4+16); /* execution breakpoint */
 844                 }
 845
 846                 vcpu->guest_debug.singlestep = dbg->singlestep;
 847         } else
 848                 vcpu->guest_debug.singlestep = 0;
 849
 850         if (old_singlestep && !vcpu->guest_debug.singlestep) {
 851                 unsigned long flags;
 852
 853                 flags = vmcs_readl(GUEST_RFLAGS);
 854                 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
 855                 vmcs_writel(GUEST_RFLAGS, flags);
 856         }
 857
 858         update_exception_bitmap(vcpu);
 859         vmcs_writel(GUEST_DR7, dr7);
 860
 861         return 0;
 862 }
 863
 864 static int vmx_get_irq(struct kvm_vcpu *vcpu)
 865 {
 866         struct vcpu_vmx *vmx = to_vmx(vcpu);
 867         u32 idtv_info_field;
 868
 869         idtv_info_field = vmx->idt_vectoring_info;
 870         if (idtv_info_field & INTR_INFO_VALID_MASK) {
 871                 if (is_external_interrupt(idtv_info_field))
 872                         return idtv_info_field & VECTORING_INFO_VECTOR_MASK;
 873                 else
 874                         printk(KERN_DEBUG "pending exception: not handled yet\n");
 875         }
 876         return -1;
 877 }
 878
 879 static __init int cpu_has_kvm_support(void)
 880 {
 881         unsigned long ecx = cpuid_ecx(1);
 882         return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */
 883 }
 884
 885 static __init int vmx_disabled_by_bios(void)
 886 {
 887         u64 msr;
 888
 889         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
 890         return (msr & (MSR_IA32_FEATURE_CONTROL_LOCKED |
 891                        MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
 892             == MSR_IA32_FEATURE_CONTROL_LOCKED;
 893         /* locked but not enabled */
 894 }
 895
 896 static void hardware_enable(void *garbage)
 897 {
 898         int cpu = raw_smp_processor_id();
 899         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
 900         u64 old;
 901
 902         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
 903         if ((old & (MSR_IA32_FEATURE_CONTROL_LOCKED |
 904                     MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
 905             != (MSR_IA32_FEATURE_CONTROL_LOCKED |
 906                 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
 907                 /* enable and lock */
 908                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
 909                        MSR_IA32_FEATURE_CONTROL_LOCKED |
 910                        MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED);
 911         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
 912         asm volatile (ASM_VMX_VMXON_RAX : : "a"(&phys_addr), "m"(phys_addr)
 913                       : "memory", "cc");
 914 }
 915
 916 static void hardware_disable(void *garbage)
 917 {
 918         asm volatile (ASM_VMX_VMXOFF : : : "cc");
 919 }
 920
 921 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
 922                                       u32 msr, u32 *result)
 923 {
 924         u32 vmx_msr_low, vmx_msr_high;
 925         u32 ctl = ctl_min | ctl_opt;
 926
 927         rdmsr(msr, vmx_msr_low, vmx_msr_high);
 928
 929         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
 930         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
 931
 932         /* Ensure minimum (required) set of control bits are supported. */
 933         if (ctl_min & ~ctl)
 934                 return -EIO;
 935
 936         *result = ctl;
 937         return 0;
 938 }
 939
 940 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
 941 {
 942         u32 vmx_msr_low, vmx_msr_high;
 943         u32 min, opt;
 944         u32 _pin_based_exec_control = 0;
 945         u32 _cpu_based_exec_control = 0;
 946         u32 _cpu_based_2nd_exec_control = 0;
 947         u32 _vmexit_control = 0;
 948         u32 _vmentry_control = 0;
 949
 950         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
 951         opt = 0;
 952         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
 953                                 &_pin_based_exec_control) < 0)
 954                 return -EIO;
 955
 956         min = CPU_BASED_HLT_EXITING |
 957 #ifdef CONFIG_X86_64
 958               CPU_BASED_CR8_LOAD_EXITING |
 959               CPU_BASED_CR8_STORE_EXITING |
 960 #endif
 961               CPU_BASED_USE_IO_BITMAPS |
 962               CPU_BASED_MOV_DR_EXITING |
 963               CPU_BASED_USE_TSC_OFFSETING;
 964         opt = CPU_BASED_TPR_SHADOW |
 965               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 966         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
 967                                 &_cpu_based_exec_control) < 0)
 968                 return -EIO;
 969 #ifdef CONFIG_X86_64
 970         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
 971                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
 972                                            ~CPU_BASED_CR8_STORE_EXITING;
 973 #endif
 974         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
 975                 min = 0;
 976                 opt = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
 977                         SECONDARY_EXEC_WBINVD_EXITING;
 978                 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS2,
 979                                         &_cpu_based_2nd_exec_control) < 0)
 980                         return -EIO;
 981         }
 982 #ifndef CONFIG_X86_64
 983         if (!(_cpu_based_2nd_exec_control &
 984                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
 985                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
 986 #endif
 987
 988         min = 0;
 989 #ifdef CONFIG_X86_64
 990         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
 991 #endif
 992         opt = 0;
 993         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
 994                                 &_vmexit_control) < 0)
 995                 return -EIO;
 996
 997         min = opt = 0;
 998         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
 999                                 &_vmentry_control) < 0)
1000                 return -EIO;
1001
1002         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1003
1004         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1005         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1006                 return -EIO;
1007
1008 #ifdef CONFIG_X86_64
1009         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1010         if (vmx_msr_high & (1u<<16))
1011                 return -EIO;
1012 #endif
1013
1014         /* Require Write-Back (WB) memory type for VMCS accesses. */
1015         if (((vmx_msr_high >> 18) & 15) != 6)
1016                 return -EIO;
1017
1018         vmcs_conf->size = vmx_msr_high & 0x1fff;
1019         vmcs_conf->order = get_order(vmcs_config.size);
1020         vmcs_conf->revision_id = vmx_msr_low;
1021
1022         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1023         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1024         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1025         vmcs_conf->vmexit_ctrl         = _vmexit_control;
1026         vmcs_conf->vmentry_ctrl        = _vmentry_control;
1027
1028         return 0;
1029 }
1030
1031 static struct vmcs *alloc_vmcs_cpu(int cpu)
1032 {
1033         int node = cpu_to_node(cpu);
1034         struct page *pages;
1035         struct vmcs *vmcs;
1036
1037         pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
1038         if (!pages)
1039                 return NULL;
1040         vmcs = page_address(pages);
1041         memset(vmcs, 0, vmcs_config.size);
1042         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1043         return vmcs;
1044 }
1045
1046 static struct vmcs *alloc_vmcs(void)
1047 {
1048         return alloc_vmcs_cpu(raw_smp_processor_id());
1049 }
1050
1051 static void free_vmcs(struct vmcs *vmcs)
1052 {
1053         free_pages((unsigned long)vmcs, vmcs_config.order);
1054 }
1055
1056 static void free_kvm_area(void)
1057 {
1058         int cpu;
1059
1060         for_each_online_cpu(cpu)
1061                 free_vmcs(per_cpu(vmxarea, cpu));
1062 }
1063
1064 static __init int alloc_kvm_area(void)
1065 {
1066         int cpu;
1067
1068         for_each_online_cpu(cpu) {
1069                 struct vmcs *vmcs;
1070
1071                 vmcs = alloc_vmcs_cpu(cpu);
1072                 if (!vmcs) {
1073                         free_kvm_area();
1074                         return -ENOMEM;
1075                 }
1076
1077                 per_cpu(vmxarea, cpu) = vmcs;
1078         }
1079         return 0;
1080 }
1081
1082 static __init int hardware_setup(void)
1083 {
1084         if (setup_vmcs_config(&vmcs_config) < 0)
1085                 return -EIO;
1086         return alloc_kvm_area();
1087 }
1088
1089 static __exit void hardware_unsetup(void)
1090 {
1091         free_kvm_area();
1092 }
1093
1094 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1095 {
1096         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1097
1098         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1099                 vmcs_write16(sf->selector, save->selector);
1100                 vmcs_writel(sf->base, save->base);
1101                 vmcs_write32(sf->limit, save->limit);
1102                 vmcs_write32(sf->ar_bytes, save->ar);
1103         } else {
1104                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1105                         << AR_DPL_SHIFT;
1106                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1107         }
1108 }
1109
1110 static void enter_pmode(struct kvm_vcpu *vcpu)
1111 {
1112         unsigned long flags;
1113
1114         vcpu->rmode.active = 0;
1115
1116         vmcs_writel(GUEST_TR_BASE, vcpu->rmode.tr.base);
1117         vmcs_write32(GUEST_TR_LIMIT, vcpu->rmode.tr.limit);
1118         vmcs_write32(GUEST_TR_AR_BYTES, vcpu->rmode.tr.ar);
1119
1120         flags = vmcs_readl(GUEST_RFLAGS);
1121         flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1122         flags |= (vcpu->rmode.save_iopl << IOPL_SHIFT);
1123         vmcs_writel(GUEST_RFLAGS, flags);
1124
1125         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1126                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1127
1128         update_exception_bitmap(vcpu);
1129
1130         fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->rmode.es);
1131         fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->rmode.ds);
1132         fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->rmode.gs);
1133         fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->rmode.fs);
1134
1135         vmcs_write16(GUEST_SS_SELECTOR, 0);
1136         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1137
1138         vmcs_write16(GUEST_CS_SELECTOR,
1139                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1140         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1141 }
1142
1143 static gva_t rmode_tss_base(struct kvm *kvm)
1144 {
1145         if (!kvm->tss_addr) {
1146                 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1147                                  kvm->memslots[0].npages - 3;
1148                 return base_gfn << PAGE_SHIFT;
1149         }
1150         return kvm->tss_addr;
1151 }
1152
1153 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1154 {
1155         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1156
1157         save->selector = vmcs_read16(sf->selector);
1158         save->base = vmcs_readl(sf->base);
1159         save->limit = vmcs_read32(sf->limit);
1160         save->ar = vmcs_read32(sf->ar_bytes);
1161         vmcs_write16(sf->selector, save->base >> 4);
1162         vmcs_write32(sf->base, save->base & 0xfffff);
1163         vmcs_write32(sf->limit, 0xffff);
1164         vmcs_write32(sf->ar_bytes, 0xf3);
1165 }
1166
1167 static void enter_rmode(struct kvm_vcpu *vcpu)
1168 {
1169         unsigned long flags;
1170
1171         vcpu->rmode.active = 1;
1172
1173         vcpu->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1174         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1175
1176         vcpu->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1177         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1178
1179         vcpu->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1180         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1181
1182         flags = vmcs_readl(GUEST_RFLAGS);
1183         vcpu->rmode.save_iopl = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1184
1185         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1186
1187         vmcs_writel(GUEST_RFLAGS, flags);
1188         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1189         update_exception_bitmap(vcpu);
1190
1191         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1192         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1193         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1194
1195         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1196         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1197         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1198                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1199         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1200
1201         fix_rmode_seg(VCPU_SREG_ES, &vcpu->rmode.es);
1202         fix_rmode_seg(VCPU_SREG_DS, &vcpu->rmode.ds);
1203         fix_rmode_seg(VCPU_SREG_GS, &vcpu->rmode.gs);
1204         fix_rmode_seg(VCPU_SREG_FS, &vcpu->rmode.fs);
1205
1206         kvm_mmu_reset_context(vcpu);
1207         init_rmode_tss(vcpu->kvm);
1208 }
1209
1210 #ifdef CONFIG_X86_64
1211
1212 static void enter_lmode(struct kvm_vcpu *vcpu)
1213 {
1214         u32 guest_tr_ar;
1215
1216         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1217         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1218                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1219                        __FUNCTION__);
1220                 vmcs_write32(GUEST_TR_AR_BYTES,
1221                              (guest_tr_ar & ~AR_TYPE_MASK)
1222                              | AR_TYPE_BUSY_64_TSS);
1223         }
1224
1225         vcpu->shadow_efer |= EFER_LMA;
1226
1227         find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME;
1228         vmcs_write32(VM_ENTRY_CONTROLS,
1229                      vmcs_read32(VM_ENTRY_CONTROLS)
1230                      | VM_ENTRY_IA32E_MODE);
1231 }
1232
1233 static void exit_lmode(struct kvm_vcpu *vcpu)
1234 {
1235         vcpu->shadow_efer &= ~EFER_LMA;
1236
1237         vmcs_write32(VM_ENTRY_CONTROLS,
1238                      vmcs_read32(VM_ENTRY_CONTROLS)
1239                      & ~VM_ENTRY_IA32E_MODE);
1240 }
1241
1242 #endif
1243
1244 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1245 {
1246         vcpu->cr4 &= KVM_GUEST_CR4_MASK;
1247         vcpu->cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1248 }
1249
1250 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1251 {
1252         vmx_fpu_deactivate(vcpu);
1253
1254         if (vcpu->rmode.active && (cr0 & X86_CR0_PE))
1255                 enter_pmode(vcpu);
1256
1257         if (!vcpu->rmode.active && !(cr0 & X86_CR0_PE))
1258                 enter_rmode(vcpu);
1259
1260 #ifdef CONFIG_X86_64
1261         if (vcpu->shadow_efer & EFER_LME) {
1262                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1263                         enter_lmode(vcpu);
1264                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1265                         exit_lmode(vcpu);
1266         }
1267 #endif
1268
1269         vmcs_writel(CR0_READ_SHADOW, cr0);
1270         vmcs_writel(GUEST_CR0,
1271                     (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON);
1272         vcpu->cr0 = cr0;
1273
1274         if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1275                 vmx_fpu_activate(vcpu);
1276 }
1277
1278 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1279 {
1280         vmcs_writel(GUEST_CR3, cr3);
1281         if (vcpu->cr0 & X86_CR0_PE)
1282                 vmx_fpu_deactivate(vcpu);
1283 }
1284
1285 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1286 {
1287         vmcs_writel(CR4_READ_SHADOW, cr4);
1288         vmcs_writel(GUEST_CR4, cr4 | (vcpu->rmode.active ?
1289                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON));
1290         vcpu->cr4 = cr4;
1291 }
1292
1293 #ifdef CONFIG_X86_64
1294
1295 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1296 {
1297         struct vcpu_vmx *vmx = to_vmx(vcpu);
1298         struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1299
1300         vcpu->shadow_efer = efer;
1301         if (efer & EFER_LMA) {
1302                 vmcs_write32(VM_ENTRY_CONTROLS,
1303                                      vmcs_read32(VM_ENTRY_CONTROLS) |
1304                                      VM_ENTRY_IA32E_MODE);
1305                 msr->data = efer;
1306
1307         } else {
1308                 vmcs_write32(VM_ENTRY_CONTROLS,
1309                                      vmcs_read32(VM_ENTRY_CONTROLS) &
1310                                      ~VM_ENTRY_IA32E_MODE);
1311
1312                 msr->data = efer & ~EFER_LME;
1313         }
1314         setup_msrs(vmx);
1315 }
1316
1317 #endif
1318
1319 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1320 {
1321         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1322
1323         return vmcs_readl(sf->base);
1324 }
1325
1326 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1327                             struct kvm_segment *var, int seg)
1328 {
1329         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1330         u32 ar;
1331
1332         var->base = vmcs_readl(sf->base);
1333         var->limit = vmcs_read32(sf->limit);
1334         var->selector = vmcs_read16(sf->selector);
1335         ar = vmcs_read32(sf->ar_bytes);
1336         if (ar & AR_UNUSABLE_MASK)
1337                 ar = 0;
1338         var->type = ar & 15;
1339         var->s = (ar >> 4) & 1;
1340         var->dpl = (ar >> 5) & 3;
1341         var->present = (ar >> 7) & 1;
1342         var->avl = (ar >> 12) & 1;
1343         var->l = (ar >> 13) & 1;
1344         var->db = (ar >> 14) & 1;
1345         var->g = (ar >> 15) & 1;
1346         var->unusable = (ar >> 16) & 1;
1347 }
1348
1349 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1350 {
1351         u32 ar;
1352
1353         if (var->unusable)
1354                 ar = 1 << 16;
1355         else {
1356                 ar = var->type & 15;
1357                 ar |= (var->s & 1) << 4;
1358                 ar |= (var->dpl & 3) << 5;
1359                 ar |= (var->present & 1) << 7;
1360                 ar |= (var->avl & 1) << 12;
1361                 ar |= (var->l & 1) << 13;
1362                 ar |= (var->db & 1) << 14;
1363                 ar |= (var->g & 1) << 15;
1364         }
1365         if (ar == 0) /* a 0 value means unusable */
1366                 ar = AR_UNUSABLE_MASK;
1367
1368         return ar;
1369 }
1370
1371 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1372                             struct kvm_segment *var, int seg)
1373 {
1374         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1375         u32 ar;
1376
1377         if (vcpu->rmode.active && seg == VCPU_SREG_TR) {
1378                 vcpu->rmode.tr.selector = var->selector;
1379                 vcpu->rmode.tr.base = var->base;
1380                 vcpu->rmode.tr.limit = var->limit;
1381                 vcpu->rmode.tr.ar = vmx_segment_access_rights(var);
1382                 return;
1383         }
1384         vmcs_writel(sf->base, var->base);
1385         vmcs_write32(sf->limit, var->limit);
1386         vmcs_write16(sf->selector, var->selector);
1387         if (vcpu->rmode.active && var->s) {
1388                 /*
1389                  * Hack real-mode segments into vm86 compatibility.
1390                  */
1391                 if (var->base == 0xffff0000 && var->selector == 0xf000)
1392                         vmcs_writel(sf->base, 0xf0000);
1393                 ar = 0xf3;
1394         } else
1395                 ar = vmx_segment_access_rights(var);
1396         vmcs_write32(sf->ar_bytes, ar);
1397 }
1398
1399 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1400 {
1401         u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1402
1403         *db = (ar >> 14) & 1;
1404         *l = (ar >> 13) & 1;
1405 }
1406
1407 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1408 {
1409         dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1410         dt->base = vmcs_readl(GUEST_IDTR_BASE);
1411 }
1412
1413 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1414 {
1415         vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1416         vmcs_writel(GUEST_IDTR_BASE, dt->base);
1417 }
1418
1419 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1420 {
1421         dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1422         dt->base = vmcs_readl(GUEST_GDTR_BASE);
1423 }
1424
1425 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1426 {
1427         vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1428         vmcs_writel(GUEST_GDTR_BASE, dt->base);
1429 }
1430
1431 static int init_rmode_tss(struct kvm *kvm)
1432 {
1433         gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
1434         u16 data = 0;
1435         int r;
1436
1437         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1438         if (r < 0)
1439                 return 0;
1440         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1441         r = kvm_write_guest_page(kvm, fn++, &data, 0x66, sizeof(u16));
1442         if (r < 0)
1443                 return 0;
1444         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
1445         if (r < 0)
1446                 return 0;
1447         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1448         if (r < 0)
1449                 return 0;
1450         data = ~0;
1451         r = kvm_write_guest_page(kvm, fn, &data, RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
1452                         sizeof(u8));
1453         if (r < 0)
1454                 return 0;
1455         return 1;
1456 }
1457
1458 static void seg_setup(int seg)
1459 {
1460         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1461
1462         vmcs_write16(sf->selector, 0);
1463         vmcs_writel(sf->base, 0);
1464         vmcs_write32(sf->limit, 0xffff);
1465         vmcs_write32(sf->ar_bytes, 0x93);
1466 }
1467
1468 static int alloc_apic_access_page(struct kvm *kvm)
1469 {
1470         struct kvm_userspace_memory_region kvm_userspace_mem;
1471         int r = 0;
1472
1473         mutex_lock(&kvm->lock);
1474         if (kvm->apic_access_page)
1475                 goto out;
1476         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
1477         kvm_userspace_mem.flags = 0;
1478         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
1479         kvm_userspace_mem.memory_size = PAGE_SIZE;
1480         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
1481         if (r)
1482                 goto out;
1483         kvm->apic_access_page = gfn_to_page(kvm, 0xfee00);
1484 out:
1485         mutex_unlock(&kvm->lock);
1486         return r;
1487 }
1488
1489 /*
1490  * Sets up the vmcs for emulated real mode.
1491  */
1492 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
1493 {
1494         u32 host_sysenter_cs;
1495         u32 junk;
1496         unsigned long a;
1497         struct descriptor_table dt;
1498         int i;
1499         unsigned long kvm_vmx_return;
1500         u32 exec_control;
1501
1502         /* I/O */
1503         vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
1504         vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
1505
1506         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
1507
1508         /* Control */
1509         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
1510                 vmcs_config.pin_based_exec_ctrl);
1511
1512         exec_control = vmcs_config.cpu_based_exec_ctrl;
1513         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
1514                 exec_control &= ~CPU_BASED_TPR_SHADOW;
1515 #ifdef CONFIG_X86_64
1516                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
1517                                 CPU_BASED_CR8_LOAD_EXITING;
1518 #endif
1519         }
1520         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
1521
1522         if (cpu_has_secondary_exec_ctrls()) {
1523                 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
1524                 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
1525                         exec_control &=
1526                                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1527                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
1528         }
1529
1530         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
1531         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
1532         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
1533
1534         vmcs_writel(HOST_CR0, read_cr0());  /* 22.2.3 */
1535         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
1536         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
1537
1538         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
1539         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
1540         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
1541         vmcs_write16(HOST_FS_SELECTOR, read_fs());    /* 22.2.4 */
1542         vmcs_write16(HOST_GS_SELECTOR, read_gs());    /* 22.2.4 */
1543         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
1544 #ifdef CONFIG_X86_64
1545         rdmsrl(MSR_FS_BASE, a);
1546         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
1547         rdmsrl(MSR_GS_BASE, a);
1548         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
1549 #else
1550         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
1551         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
1552 #endif
1553
1554         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
1555
1556         get_idt(&dt);
1557         vmcs_writel(HOST_IDTR_BASE, dt.base);   /* 22.2.4 */
1558
1559         asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
1560         vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
1561         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
1562         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
1563         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
1564
1565         rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
1566         vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
1567         rdmsrl(MSR_IA32_SYSENTER_ESP, a);
1568         vmcs_writel(HOST_IA32_SYSENTER_ESP, a);   /* 22.2.3 */
1569         rdmsrl(MSR_IA32_SYSENTER_EIP, a);
1570         vmcs_writel(HOST_IA32_SYSENTER_EIP, a);   /* 22.2.3 */
1571
1572         for (i = 0; i < NR_VMX_MSR; ++i) {
1573                 u32 index = vmx_msr_index[i];
1574                 u32 data_low, data_high;
1575                 u64 data;
1576                 int j = vmx->nmsrs;
1577
1578                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
1579                         continue;
1580                 if (wrmsr_safe(index, data_low, data_high) < 0)
1581                         continue;
1582                 data = data_low | ((u64)data_high << 32);
1583                 vmx->host_msrs[j].index = index;
1584                 vmx->host_msrs[j].reserved = 0;
1585                 vmx->host_msrs[j].data = data;
1586                 vmx->guest_msrs[j] = vmx->host_msrs[j];
1587                 ++vmx->nmsrs;
1588         }
1589
1590         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
1591
1592         /* 22.2.1, 20.8.1 */
1593         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
1594
1595         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
1596         vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
1597
1598         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
1599                 if (alloc_apic_access_page(vmx->vcpu.kvm) != 0)
1600                         return -ENOMEM;
1601
1602         return 0;
1603 }
1604
1605 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
1606 {
1607         struct vcpu_vmx *vmx = to_vmx(vcpu);
1608         u64 msr;
1609         int ret;
1610
1611         if (!init_rmode_tss(vmx->vcpu.kvm)) {
1612                 ret = -ENOMEM;
1613                 goto out;
1614         }
1615
1616         vmx->vcpu.rmode.active = 0;
1617
1618         vmx->vcpu.regs[VCPU_REGS_RDX] = get_rdx_init_val();
1619         set_cr8(&vmx->vcpu, 0);
1620         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1621         if (vmx->vcpu.vcpu_id == 0)
1622                 msr |= MSR_IA32_APICBASE_BSP;
1623         kvm_set_apic_base(&vmx->vcpu, msr);
1624
1625         fx_init(&vmx->vcpu);
1626
1627         /*
1628          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
1629          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
1630          */
1631         if (vmx->vcpu.vcpu_id == 0) {
1632                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
1633                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
1634         } else {
1635                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.sipi_vector << 8);
1636                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.sipi_vector << 12);
1637         }
1638         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1639         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1640
1641         seg_setup(VCPU_SREG_DS);
1642         seg_setup(VCPU_SREG_ES);
1643         seg_setup(VCPU_SREG_FS);
1644         seg_setup(VCPU_SREG_GS);
1645         seg_setup(VCPU_SREG_SS);
1646
1647         vmcs_write16(GUEST_TR_SELECTOR, 0);
1648         vmcs_writel(GUEST_TR_BASE, 0);
1649         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
1650         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1651
1652         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
1653         vmcs_writel(GUEST_LDTR_BASE, 0);
1654         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
1655         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
1656
1657         vmcs_write32(GUEST_SYSENTER_CS, 0);
1658         vmcs_writel(GUEST_SYSENTER_ESP, 0);
1659         vmcs_writel(GUEST_SYSENTER_EIP, 0);
1660
1661         vmcs_writel(GUEST_RFLAGS, 0x02);
1662         if (vmx->vcpu.vcpu_id == 0)
1663                 vmcs_writel(GUEST_RIP, 0xfff0);
1664         else
1665                 vmcs_writel(GUEST_RIP, 0);
1666         vmcs_writel(GUEST_RSP, 0);
1667
1668         /* todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0 */
1669         vmcs_writel(GUEST_DR7, 0x400);
1670
1671         vmcs_writel(GUEST_GDTR_BASE, 0);
1672         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
1673
1674         vmcs_writel(GUEST_IDTR_BASE, 0);
1675         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
1676
1677         vmcs_write32(GUEST_ACTIVITY_STATE, 0);
1678         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
1679         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
1680
1681         guest_write_tsc(0);
1682
1683         /* Special registers */
1684         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
1685
1686         setup_msrs(vmx);
1687
1688         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
1689
1690         if (cpu_has_vmx_tpr_shadow()) {
1691                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
1692                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
1693                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
1694                                      page_to_phys(vmx->vcpu.apic->regs_page));
1695                 vmcs_write32(TPR_THRESHOLD, 0);
1696         }
1697
1698         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
1699                 vmcs_write64(APIC_ACCESS_ADDR,
1700                              page_to_phys(vmx->vcpu.kvm->apic_access_page));
1701
1702         vmx->vcpu.cr0 = 0x60000010;
1703         vmx_set_cr0(&vmx->vcpu, vmx->vcpu.cr0); /* enter rmode */
1704         vmx_set_cr4(&vmx->vcpu, 0);
1705 #ifdef CONFIG_X86_64
1706         vmx_set_efer(&vmx->vcpu, 0);
1707 #endif
1708         vmx_fpu_activate(&vmx->vcpu);
1709         update_exception_bitmap(&vmx->vcpu);
1710
1711         return 0;
1712
1713 out:
1714         return ret;
1715 }
1716
1717 static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
1718 {
1719         struct vcpu_vmx *vmx = to_vmx(vcpu);
1720
1721         if (vcpu->rmode.active) {
1722                 vmx->rmode.irq.pending = true;
1723                 vmx->rmode.irq.vector = irq;
1724                 vmx->rmode.irq.rip = vmcs_readl(GUEST_RIP);
1725                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1726                              irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
1727                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
1728                 vmcs_writel(GUEST_RIP, vmx->rmode.irq.rip - 1);
1729                 return;
1730         }
1731         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1732                         irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1733 }
1734
1735 static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
1736 {
1737         int word_index = __ffs(vcpu->irq_summary);
1738         int bit_index = __ffs(vcpu->irq_pending[word_index]);
1739         int irq = word_index * BITS_PER_LONG + bit_index;
1740
1741         clear_bit(bit_index, &vcpu->irq_pending[word_index]);
1742         if (!vcpu->irq_pending[word_index])
1743                 clear_bit(word_index, &vcpu->irq_summary);
1744         vmx_inject_irq(vcpu, irq);
1745 }
1746
1747
1748 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1749                                        struct kvm_run *kvm_run)
1750 {
1751         u32 cpu_based_vm_exec_control;
1752
1753         vcpu->interrupt_window_open =
1754                 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
1755                  (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
1756
1757         if (vcpu->interrupt_window_open &&
1758             vcpu->irq_summary &&
1759             !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK))
1760                 /*
1761                  * If interrupts enabled, and not blocked by sti or mov ss. Good.
1762                  */
1763                 kvm_do_inject_irq(vcpu);
1764
1765         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
1766         if (!vcpu->interrupt_window_open &&
1767             (vcpu->irq_summary || kvm_run->request_interrupt_window))
1768                 /*
1769                  * Interrupts blocked.  Wait for unblock.
1770                  */
1771                 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
1772         else
1773                 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
1774         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
1775 }
1776
1777 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
1778 {
1779         int ret;
1780         struct kvm_userspace_memory_region tss_mem = {
1781                 .slot = 8,
1782                 .guest_phys_addr = addr,
1783                 .memory_size = PAGE_SIZE * 3,
1784                 .flags = 0,
1785         };
1786
1787         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
1788         if (ret)
1789                 return ret;
1790         kvm->tss_addr = addr;
1791         return 0;
1792 }
1793
1794 static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
1795 {
1796         struct kvm_guest_debug *dbg = &vcpu->guest_debug;
1797
1798         set_debugreg(dbg->bp[0], 0);
1799         set_debugreg(dbg->bp[1], 1);
1800         set_debugreg(dbg->bp[2], 2);
1801         set_debugreg(dbg->bp[3], 3);
1802
1803         if (dbg->singlestep) {
1804                 unsigned long flags;
1805
1806                 flags = vmcs_readl(GUEST_RFLAGS);
1807                 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1808                 vmcs_writel(GUEST_RFLAGS, flags);
1809         }
1810 }
1811
1812 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
1813                                   int vec, u32 err_code)
1814 {
1815         if (!vcpu->rmode.active)
1816                 return 0;
1817
1818         /*
1819          * Instruction with address size override prefix opcode 0x67
1820          * Cause the #SS fault with 0 error code in VM86 mode.
1821          */
1822         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
1823                 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
1824                         return 1;
1825         return 0;
1826 }
1827
1828 static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1829 {
1830         struct vcpu_vmx *vmx = to_vmx(vcpu);
1831         u32 intr_info, error_code;
1832         unsigned long cr2, rip;
1833         u32 vect_info;
1834         enum emulation_result er;
1835
1836         vect_info = vmx->idt_vectoring_info;
1837         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
1838
1839         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
1840                                                 !is_page_fault(intr_info))
1841                 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
1842                        "intr info 0x%x\n", __FUNCTION__, vect_info, intr_info);
1843
1844         if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) {
1845                 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
1846                 set_bit(irq, vcpu->irq_pending);
1847                 set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary);
1848         }
1849
1850         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
1851                 return 1;  /* already handled by vmx_vcpu_run() */
1852
1853         if (is_no_device(intr_info)) {
1854                 vmx_fpu_activate(vcpu);
1855                 return 1;
1856         }
1857
1858         if (is_invalid_opcode(intr_info)) {
1859                 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
1860                 if (er != EMULATE_DONE)
1861                         kvm_queue_exception(vcpu, UD_VECTOR);
1862                 return 1;
1863         }
1864
1865         error_code = 0;
1866         rip = vmcs_readl(GUEST_RIP);
1867         if (intr_info & INTR_INFO_DELIEVER_CODE_MASK)
1868                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
1869         if (is_page_fault(intr_info)) {
1870                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
1871                 return kvm_mmu_page_fault(vcpu, cr2, error_code);
1872         }
1873
1874         if (vcpu->rmode.active &&
1875             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
1876                                                                 error_code)) {
1877                 if (vcpu->halt_request) {
1878                         vcpu->halt_request = 0;
1879                         return kvm_emulate_halt(vcpu);
1880                 }
1881                 return 1;
1882         }
1883
1884         if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) ==
1885             (INTR_TYPE_EXCEPTION | 1)) {
1886                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1887                 return 0;
1888         }
1889         kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
1890         kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
1891         kvm_run->ex.error_code = error_code;
1892         return 0;
1893 }
1894
1895 static int handle_external_interrupt(struct kvm_vcpu *vcpu,
1896                                      struct kvm_run *kvm_run)
1897 {
1898         ++vcpu->stat.irq_exits;
1899         return 1;
1900 }
1901
1902 static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1903 {
1904         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1905         return 0;
1906 }
1907
1908 static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1909 {
1910         unsigned long exit_qualification;
1911         int size, down, in, string, rep;
1912         unsigned port;
1913
1914         ++vcpu->stat.io_exits;
1915         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1916         string = (exit_qualification & 16) != 0;
1917
1918         if (string) {
1919                 if (emulate_instruction(vcpu,
1920                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
1921                         return 0;
1922                 return 1;
1923         }
1924
1925         size = (exit_qualification & 7) + 1;
1926         in = (exit_qualification & 8) != 0;
1927         down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
1928         rep = (exit_qualification & 32) != 0;
1929         port = exit_qualification >> 16;
1930
1931         return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
1932 }
1933
1934 static void
1935 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1936 {
1937         /*
1938          * Patch in the VMCALL instruction:
1939          */
1940         hypercall[0] = 0x0f;
1941         hypercall[1] = 0x01;
1942         hypercall[2] = 0xc1;
1943 }
1944
1945 static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1946 {
1947         unsigned long exit_qualification;
1948         int cr;
1949         int reg;
1950
1951         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1952         cr = exit_qualification & 15;
1953         reg = (exit_qualification >> 8) & 15;
1954         switch ((exit_qualification >> 4) & 3) {
1955         case 0: /* mov to cr */
1956                 switch (cr) {
1957                 case 0:
1958                         vcpu_load_rsp_rip(vcpu);
1959                         set_cr0(vcpu, vcpu->regs[reg]);
1960                         skip_emulated_instruction(vcpu);
1961                         return 1;
1962                 case 3:
1963                         vcpu_load_rsp_rip(vcpu);
1964                         set_cr3(vcpu, vcpu->regs[reg]);
1965                         skip_emulated_instruction(vcpu);
1966                         return 1;
1967                 case 4:
1968                         vcpu_load_rsp_rip(vcpu);
1969                         set_cr4(vcpu, vcpu->regs[reg]);
1970                         skip_emulated_instruction(vcpu);
1971                         return 1;
1972                 case 8:
1973                         vcpu_load_rsp_rip(vcpu);
1974                         set_cr8(vcpu, vcpu->regs[reg]);
1975                         skip_emulated_instruction(vcpu);
1976                         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1977                         return 0;
1978                 };
1979                 break;
1980         case 2: /* clts */
1981                 vcpu_load_rsp_rip(vcpu);
1982                 vmx_fpu_deactivate(vcpu);
1983                 vcpu->cr0 &= ~X86_CR0_TS;
1984                 vmcs_writel(CR0_READ_SHADOW, vcpu->cr0);
1985                 vmx_fpu_activate(vcpu);
1986                 skip_emulated_instruction(vcpu);
1987                 return 1;
1988         case 1: /*mov from cr*/
1989                 switch (cr) {
1990                 case 3:
1991                         vcpu_load_rsp_rip(vcpu);
1992                         vcpu->regs[reg] = vcpu->cr3;
1993                         vcpu_put_rsp_rip(vcpu);
1994                         skip_emulated_instruction(vcpu);
1995                         return 1;
1996                 case 8:
1997                         vcpu_load_rsp_rip(vcpu);
1998                         vcpu->regs[reg] = get_cr8(vcpu);
1999                         vcpu_put_rsp_rip(vcpu);
2000                         skip_emulated_instruction(vcpu);
2001                         return 1;
2002                 }
2003                 break;
2004         case 3: /* lmsw */
2005                 lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
2006
2007                 skip_emulated_instruction(vcpu);
2008                 return 1;
2009         default:
2010                 break;
2011         }
2012         kvm_run->exit_reason = 0;
2013         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
2014                (int)(exit_qualification >> 4) & 3, cr);
2015         return 0;
2016 }
2017
2018 static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2019 {
2020         unsigned long exit_qualification;
2021         unsigned long val;
2022         int dr, reg;
2023
2024         /*
2025          * FIXME: this code assumes the host is debugging the guest.
2026          *        need to deal with guest debugging itself too.
2027          */
2028         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2029         dr = exit_qualification & 7;
2030         reg = (exit_qualification >> 8) & 15;
2031         vcpu_load_rsp_rip(vcpu);
2032         if (exit_qualification & 16) {
2033                 /* mov from dr */
2034                 switch (dr) {
2035                 case 6:
2036                         val = 0xffff0ff0;
2037                         break;
2038                 case 7:
2039                         val = 0x400;
2040                         break;
2041                 default:
2042                         val = 0;
2043                 }
2044                 vcpu->regs[reg] = val;
2045         } else {
2046                 /* mov to dr */
2047         }
2048         vcpu_put_rsp_rip(vcpu);
2049         skip_emulated_instruction(vcpu);
2050         return 1;
2051 }
2052
2053 static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2054 {
2055         kvm_emulate_cpuid(vcpu);
2056         return 1;
2057 }
2058
2059 static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2060 {
2061         u32 ecx = vcpu->regs[VCPU_REGS_RCX];
2062         u64 data;
2063
2064         if (vmx_get_msr(vcpu, ecx, &data)) {
2065                 kvm_inject_gp(vcpu, 0);
2066                 return 1;
2067         }
2068
2069         /* FIXME: handling of bits 32:63 of rax, rdx */
2070         vcpu->regs[VCPU_REGS_RAX] = data & -1u;
2071         vcpu->regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
2072         skip_emulated_instruction(vcpu);
2073         return 1;
2074 }
2075
2076 static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2077 {
2078         u32 ecx = vcpu->regs[VCPU_REGS_RCX];
2079         u64 data = (vcpu->regs[VCPU_REGS_RAX] & -1u)
2080                 | ((u64)(vcpu->regs[VCPU_REGS_RDX] & -1u) << 32);
2081
2082         if (vmx_set_msr(vcpu, ecx, data) != 0) {
2083                 kvm_inject_gp(vcpu, 0);
2084                 return 1;
2085         }
2086
2087         skip_emulated_instruction(vcpu);
2088         return 1;
2089 }
2090
2091 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2092                                       struct kvm_run *kvm_run)
2093 {
2094         return 1;
2095 }
2096
2097 static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2098                                    struct kvm_run *kvm_run)
2099 {
2100         u32 cpu_based_vm_exec_control;
2101
2102         /* clear pending irq */
2103         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2104         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2105         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2106         /*
2107          * If the user space waits to inject interrupts, exit as soon as
2108          * possible
2109          */
2110         if (kvm_run->request_interrupt_window &&
2111             !vcpu->irq_summary) {
2112                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2113                 ++vcpu->stat.irq_window_exits;
2114                 return 0;
2115         }
2116         return 1;
2117 }
2118
2119 static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2120 {
2121         skip_emulated_instruction(vcpu);
2122         return kvm_emulate_halt(vcpu);
2123 }
2124
2125 static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2126 {
2127         skip_emulated_instruction(vcpu);
2128         kvm_emulate_hypercall(vcpu);
2129         return 1;
2130 }
2131
2132 static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2133 {
2134         skip_emulated_instruction(vcpu);
2135         /* TODO: Add support for VT-d/pass-through device */
2136         return 1;
2137 }
2138
2139 static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2140 {
2141         u64 exit_qualification;
2142         enum emulation_result er;
2143         unsigned long offset;
2144
2145         exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2146         offset = exit_qualification & 0xffful;
2147
2148         er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2149
2150         if (er !=  EMULATE_DONE) {
2151                 printk(KERN_ERR
2152                        "Fail to handle apic access vmexit! Offset is 0x%lx\n",
2153                        offset);
2154                 return -ENOTSUPP;
2155         }
2156         return 1;
2157 }
2158
2159 /*
2160  * The exit handlers return 1 if the exit was handled fully and guest execution
2161  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
2162  * to be done to userspace and return 0.
2163  */
2164 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
2165                                       struct kvm_run *kvm_run) = {
2166         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
2167         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
2168         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
2169         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
2170         [EXIT_REASON_CR_ACCESS]               = handle_cr,
2171         [EXIT_REASON_DR_ACCESS]               = handle_dr,
2172         [EXIT_REASON_CPUID]                   = handle_cpuid,
2173         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
2174         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
2175         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
2176         [EXIT_REASON_HLT]                     = handle_halt,
2177         [EXIT_REASON_VMCALL]                  = handle_vmcall,
2178         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
2179         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
2180         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
2181 };
2182
2183 static const int kvm_vmx_max_exit_handlers =
2184         ARRAY_SIZE(kvm_vmx_exit_handlers);
2185
2186 /*
2187  * The guest has exited.  See if we can fix it or if we need userspace
2188  * assistance.
2189  */
2190 static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2191 {
2192         u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
2193         struct vcpu_vmx *vmx = to_vmx(vcpu);
2194         u32 vectoring_info = vmx->idt_vectoring_info;
2195
2196         if (unlikely(vmx->fail)) {
2197                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2198                 kvm_run->fail_entry.hardware_entry_failure_reason
2199                         = vmcs_read32(VM_INSTRUCTION_ERROR);
2200                 return 0;
2201         }
2202
2203         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
2204                                 exit_reason != EXIT_REASON_EXCEPTION_NMI)
2205                 printk(KERN_WARNING "%s: unexpected, valid vectoring info and "
2206                        "exit reason is 0x%x\n", __FUNCTION__, exit_reason);
2207         if (exit_reason < kvm_vmx_max_exit_handlers
2208             && kvm_vmx_exit_handlers[exit_reason])
2209                 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
2210         else {
2211                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2212                 kvm_run->hw.hardware_exit_reason = exit_reason;
2213         }
2214         return 0;
2215 }
2216
2217 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2218 {
2219 }
2220
2221 static void update_tpr_threshold(struct kvm_vcpu *vcpu)
2222 {
2223         int max_irr, tpr;
2224
2225         if (!vm_need_tpr_shadow(vcpu->kvm))
2226                 return;
2227
2228         if (!kvm_lapic_enabled(vcpu) ||
2229             ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) {
2230                 vmcs_write32(TPR_THRESHOLD, 0);
2231                 return;
2232         }
2233
2234         tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4;
2235         vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4);
2236 }
2237
2238 static void enable_irq_window(struct kvm_vcpu *vcpu)
2239 {
2240         u32 cpu_based_vm_exec_control;
2241
2242         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2243         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2244         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2245 }
2246
2247 static void vmx_intr_assist(struct kvm_vcpu *vcpu)
2248 {
2249         struct vcpu_vmx *vmx = to_vmx(vcpu);
2250         u32 idtv_info_field, intr_info_field;
2251         int has_ext_irq, interrupt_window_open;
2252         int vector;
2253
2254         update_tpr_threshold(vcpu);
2255
2256         has_ext_irq = kvm_cpu_has_interrupt(vcpu);
2257         intr_info_field = vmcs_read32(VM_ENTRY_INTR_INFO_FIELD);
2258         idtv_info_field = vmx->idt_vectoring_info;
2259         if (intr_info_field & INTR_INFO_VALID_MASK) {
2260                 if (idtv_info_field & INTR_INFO_VALID_MASK) {
2261                         /* TODO: fault when IDT_Vectoring */
2262                         printk(KERN_ERR "Fault when IDT_Vectoring\n");
2263                 }
2264                 if (has_ext_irq)
2265                         enable_irq_window(vcpu);
2266                 return;
2267         }
2268         if (unlikely(idtv_info_field & INTR_INFO_VALID_MASK)) {
2269                 if ((idtv_info_field & VECTORING_INFO_TYPE_MASK)
2270                     == INTR_TYPE_EXT_INTR
2271                     && vcpu->rmode.active) {
2272                         u8 vect = idtv_info_field & VECTORING_INFO_VECTOR_MASK;
2273
2274                         vmx_inject_irq(vcpu, vect);
2275                         if (unlikely(has_ext_irq))
2276                                 enable_irq_window(vcpu);
2277                         return;
2278                 }
2279
2280                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, idtv_info_field);
2281                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2282                                 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
2283
2284                 if (unlikely(idtv_info_field & INTR_INFO_DELIEVER_CODE_MASK))
2285                         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
2286                                 vmcs_read32(IDT_VECTORING_ERROR_CODE));
2287                 if (unlikely(has_ext_irq))
2288                         enable_irq_window(vcpu);
2289                 return;
2290         }
2291         if (!has_ext_irq)
2292                 return;
2293         interrupt_window_open =
2294                 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2295                  (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
2296         if (interrupt_window_open) {
2297                 vector = kvm_cpu_get_interrupt(vcpu);
2298                 vmx_inject_irq(vcpu, vector);
2299                 kvm_timer_intr_post(vcpu, vector);
2300         } else
2301                 enable_irq_window(vcpu);
2302 }
2303
2304 /*
2305  * Failure to inject an interrupt should give us the information
2306  * in IDT_VECTORING_INFO_FIELD.  However, if the failure occurs
2307  * when fetching the interrupt redirection bitmap in the real-mode
2308  * tss, this doesn't happen.  So we do it ourselves.
2309  */
2310 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
2311 {
2312         vmx->rmode.irq.pending = 0;
2313         if (vmcs_readl(GUEST_RIP) + 1 != vmx->rmode.irq.rip)
2314                 return;
2315         vmcs_writel(GUEST_RIP, vmx->rmode.irq.rip);
2316         if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
2317                 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
2318                 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
2319                 return;
2320         }
2321         vmx->idt_vectoring_info =
2322                 VECTORING_INFO_VALID_MASK
2323                 | INTR_TYPE_EXT_INTR
2324                 | vmx->rmode.irq.vector;
2325 }
2326
2327 static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2328 {
2329         struct vcpu_vmx *vmx = to_vmx(vcpu);
2330         u32 intr_info;
2331
2332         /*
2333          * Loading guest fpu may have cleared host cr0.ts
2334          */
2335         vmcs_writel(HOST_CR0, read_cr0());
2336
2337         asm(
2338                 /* Store host registers */
2339 #ifdef CONFIG_X86_64
2340                 "push %%rdx; push %%rbp;"
2341                 "push %%rcx \n\t"
2342 #else
2343                 "push %%edx; push %%ebp;"
2344                 "push %%ecx \n\t"
2345 #endif
2346                 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
2347                 /* Check if vmlaunch of vmresume is needed */
2348                 "cmpl $0, %c[launched](%0) \n\t"
2349                 /* Load guest registers.  Don't clobber flags. */
2350 #ifdef CONFIG_X86_64
2351                 "mov %c[cr2](%0), %%rax \n\t"
2352                 "mov %%rax, %%cr2 \n\t"
2353                 "mov %c[rax](%0), %%rax \n\t"
2354                 "mov %c[rbx](%0), %%rbx \n\t"
2355                 "mov %c[rdx](%0), %%rdx \n\t"
2356                 "mov %c[rsi](%0), %%rsi \n\t"
2357                 "mov %c[rdi](%0), %%rdi \n\t"
2358                 "mov %c[rbp](%0), %%rbp \n\t"
2359                 "mov %c[r8](%0),  %%r8  \n\t"
2360                 "mov %c[r9](%0),  %%r9  \n\t"
2361                 "mov %c[r10](%0), %%r10 \n\t"
2362                 "mov %c[r11](%0), %%r11 \n\t"
2363                 "mov %c[r12](%0), %%r12 \n\t"
2364                 "mov %c[r13](%0), %%r13 \n\t"
2365                 "mov %c[r14](%0), %%r14 \n\t"
2366                 "mov %c[r15](%0), %%r15 \n\t"
2367                 "mov %c[rcx](%0), %%rcx \n\t" /* kills %0 (rcx) */
2368 #else
2369                 "mov %c[cr2](%0), %%eax \n\t"
2370                 "mov %%eax,   %%cr2 \n\t"
2371                 "mov %c[rax](%0), %%eax \n\t"
2372                 "mov %c[rbx](%0), %%ebx \n\t"
2373                 "mov %c[rdx](%0), %%edx \n\t"
2374                 "mov %c[rsi](%0), %%esi \n\t"
2375                 "mov %c[rdi](%0), %%edi \n\t"
2376                 "mov %c[rbp](%0), %%ebp \n\t"
2377                 "mov %c[rcx](%0), %%ecx \n\t" /* kills %0 (ecx) */
2378 #endif
2379                 /* Enter guest mode */
2380                 "jne .Llaunched \n\t"
2381                 ASM_VMX_VMLAUNCH "\n\t"
2382                 "jmp .Lkvm_vmx_return \n\t"
2383                 ".Llaunched: " ASM_VMX_VMRESUME "\n\t"
2384                 ".Lkvm_vmx_return: "
2385                 /* Save guest registers, load host registers, keep flags */
2386 #ifdef CONFIG_X86_64
2387                 "xchg %0,     (%%rsp) \n\t"
2388                 "mov %%rax, %c[rax](%0) \n\t"
2389                 "mov %%rbx, %c[rbx](%0) \n\t"
2390                 "pushq (%%rsp); popq %c[rcx](%0) \n\t"
2391                 "mov %%rdx, %c[rdx](%0) \n\t"
2392                 "mov %%rsi, %c[rsi](%0) \n\t"
2393                 "mov %%rdi, %c[rdi](%0) \n\t"
2394                 "mov %%rbp, %c[rbp](%0) \n\t"
2395                 "mov %%r8,  %c[r8](%0) \n\t"
2396                 "mov %%r9,  %c[r9](%0) \n\t"
2397                 "mov %%r10, %c[r10](%0) \n\t"
2398                 "mov %%r11, %c[r11](%0) \n\t"
2399                 "mov %%r12, %c[r12](%0) \n\t"
2400                 "mov %%r13, %c[r13](%0) \n\t"
2401                 "mov %%r14, %c[r14](%0) \n\t"
2402                 "mov %%r15, %c[r15](%0) \n\t"
2403                 "mov %%cr2, %%rax   \n\t"
2404                 "mov %%rax, %c[cr2](%0) \n\t"
2405
2406                 "pop  %%rbp; pop  %%rbp; pop  %%rdx \n\t"
2407 #else
2408                 "xchg %0, (%%esp) \n\t"
2409                 "mov %%eax, %c[rax](%0) \n\t"
2410                 "mov %%ebx, %c[rbx](%0) \n\t"
2411                 "pushl (%%esp); popl %c[rcx](%0) \n\t"
2412                 "mov %%edx, %c[rdx](%0) \n\t"
2413                 "mov %%esi, %c[rsi](%0) \n\t"
2414                 "mov %%edi, %c[rdi](%0) \n\t"
2415                 "mov %%ebp, %c[rbp](%0) \n\t"
2416                 "mov %%cr2, %%eax  \n\t"
2417                 "mov %%eax, %c[cr2](%0) \n\t"
2418
2419                 "pop %%ebp; pop %%ebp; pop %%edx \n\t"
2420 #endif
2421                 "setbe %c[fail](%0) \n\t"
2422               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
2423                 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
2424                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
2425                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_RAX])),
2426                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_RBX])),
2427                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_RCX])),
2428                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_RDX])),
2429                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_RSI])),
2430                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_RDI])),
2431                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_RBP])),
2432 #ifdef CONFIG_X86_64
2433                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_R8])),
2434                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_R9])),
2435                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_R10])),
2436                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_R11])),
2437                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_R12])),
2438                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_R13])),
2439                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_R14])),
2440                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_R15])),
2441 #endif
2442                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.cr2))
2443               : "cc", "memory"
2444 #ifdef CONFIG_X86_64
2445                 , "rbx", "rdi", "rsi"
2446                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2447 #else
2448                 , "ebx", "edi", "rsi"
2449 #endif
2450               );
2451
2452         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
2453         if (vmx->rmode.irq.pending)
2454                 fixup_rmode_irq(vmx);
2455
2456         vcpu->interrupt_window_open =
2457                 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0;
2458
2459         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
2460         vmx->launched = 1;
2461
2462         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2463
2464         /* We need to handle NMIs before interrupts are enabled */
2465         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
2466                 asm("int $2");
2467 }
2468
2469 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
2470 {
2471         struct vcpu_vmx *vmx = to_vmx(vcpu);
2472
2473         if (vmx->vmcs) {
2474                 on_each_cpu(__vcpu_clear, vmx, 0, 1);
2475                 free_vmcs(vmx->vmcs);
2476                 vmx->vmcs = NULL;
2477         }
2478 }
2479
2480 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
2481 {
2482         struct vcpu_vmx *vmx = to_vmx(vcpu);
2483
2484         vmx_free_vmcs(vcpu);
2485         kfree(vmx->host_msrs);
2486         kfree(vmx->guest_msrs);
2487         kvm_vcpu_uninit(vcpu);
2488         kmem_cache_free(kvm_vcpu_cache, vmx);
2489 }
2490
2491 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
2492 {
2493         int err;
2494         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
2495         int cpu;
2496
2497         if (!vmx)
2498                 return ERR_PTR(-ENOMEM);
2499
2500         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
2501         if (err)
2502                 goto free_vcpu;
2503
2504         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2505         if (!vmx->guest_msrs) {
2506                 err = -ENOMEM;
2507                 goto uninit_vcpu;
2508         }
2509
2510         vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2511         if (!vmx->host_msrs)
2512                 goto free_guest_msrs;
2513
2514         vmx->vmcs = alloc_vmcs();
2515         if (!vmx->vmcs)
2516                 goto free_msrs;
2517
2518         vmcs_clear(vmx->vmcs);
2519
2520         cpu = get_cpu();
2521         vmx_vcpu_load(&vmx->vcpu, cpu);
2522         err = vmx_vcpu_setup(vmx);
2523         vmx_vcpu_put(&vmx->vcpu);
2524         put_cpu();
2525         if (err)
2526                 goto free_vmcs;
2527
2528         return &vmx->vcpu;
2529
2530 free_vmcs:
2531         free_vmcs(vmx->vmcs);
2532 free_msrs:
2533         kfree(vmx->host_msrs);
2534 free_guest_msrs:
2535         kfree(vmx->guest_msrs);
2536 uninit_vcpu:
2537         kvm_vcpu_uninit(&vmx->vcpu);
2538 free_vcpu:
2539         kmem_cache_free(kvm_vcpu_cache, vmx);
2540         return ERR_PTR(err);
2541 }
2542
2543 static void __init vmx_check_processor_compat(void *rtn)
2544 {
2545         struct vmcs_config vmcs_conf;
2546
2547         *(int *)rtn = 0;
2548         if (setup_vmcs_config(&vmcs_conf) < 0)
2549                 *(int *)rtn = -EIO;
2550         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
2551                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
2552                                 smp_processor_id());
2553                 *(int *)rtn = -EIO;
2554         }
2555 }
2556
2557 static struct kvm_x86_ops vmx_x86_ops = {
2558         .cpu_has_kvm_support = cpu_has_kvm_support,
2559         .disabled_by_bios = vmx_disabled_by_bios,
2560         .hardware_setup = hardware_setup,
2561         .hardware_unsetup = hardware_unsetup,
2562         .check_processor_compatibility = vmx_check_processor_compat,
2563         .hardware_enable = hardware_enable,
2564         .hardware_disable = hardware_disable,
2565
2566         .vcpu_create = vmx_create_vcpu,
2567         .vcpu_free = vmx_free_vcpu,
2568         .vcpu_reset = vmx_vcpu_reset,
2569
2570         .prepare_guest_switch = vmx_save_host_state,
2571         .vcpu_load = vmx_vcpu_load,
2572         .vcpu_put = vmx_vcpu_put,
2573         .vcpu_decache = vmx_vcpu_decache,
2574
2575         .set_guest_debug = set_guest_debug,
2576         .guest_debug_pre = kvm_guest_debug_pre,
2577         .get_msr = vmx_get_msr,
2578         .set_msr = vmx_set_msr,
2579         .get_segment_base = vmx_get_segment_base,
2580         .get_segment = vmx_get_segment,
2581         .set_segment = vmx_set_segment,
2582         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
2583         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
2584         .set_cr0 = vmx_set_cr0,
2585         .set_cr3 = vmx_set_cr3,
2586         .set_cr4 = vmx_set_cr4,
2587 #ifdef CONFIG_X86_64
2588         .set_efer = vmx_set_efer,
2589 #endif
2590         .get_idt = vmx_get_idt,
2591         .set_idt = vmx_set_idt,
2592         .get_gdt = vmx_get_gdt,
2593         .set_gdt = vmx_set_gdt,
2594         .cache_regs = vcpu_load_rsp_rip,
2595         .decache_regs = vcpu_put_rsp_rip,
2596         .get_rflags = vmx_get_rflags,
2597         .set_rflags = vmx_set_rflags,
2598
2599         .tlb_flush = vmx_flush_tlb,
2600
2601         .run = vmx_vcpu_run,
2602         .handle_exit = kvm_handle_exit,
2603         .skip_emulated_instruction = skip_emulated_instruction,
2604         .patch_hypercall = vmx_patch_hypercall,
2605         .get_irq = vmx_get_irq,
2606         .set_irq = vmx_inject_irq,
2607         .queue_exception = vmx_queue_exception,
2608         .exception_injected = vmx_exception_injected,
2609         .inject_pending_irq = vmx_intr_assist,
2610         .inject_pending_vectors = do_interrupt_requests,
2611
2612         .set_tss_addr = vmx_set_tss_addr,
2613 };
2614
2615 static int __init vmx_init(void)
2616 {
2617         void *iova;
2618         int r;
2619
2620         vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2621         if (!vmx_io_bitmap_a)
2622                 return -ENOMEM;
2623
2624         vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2625         if (!vmx_io_bitmap_b) {
2626                 r = -ENOMEM;
2627                 goto out;
2628         }
2629
2630         /*
2631          * Allow direct access to the PC debug port (it is often used for I/O
2632          * delays, but the vmexits simply slow things down).
2633          */
2634         iova = kmap(vmx_io_bitmap_a);
2635         memset(iova, 0xff, PAGE_SIZE);
2636         clear_bit(0x80, iova);
2637         kunmap(vmx_io_bitmap_a);
2638
2639         iova = kmap(vmx_io_bitmap_b);
2640         memset(iova, 0xff, PAGE_SIZE);
2641         kunmap(vmx_io_bitmap_b);
2642
2643         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
2644         if (r)
2645                 goto out1;
2646
2647         if (bypass_guest_pf)
2648                 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
2649
2650         return 0;
2651
2652 out1:
2653         __free_page(vmx_io_bitmap_b);
2654 out:
2655         __free_page(vmx_io_bitmap_a);
2656         return r;
2657 }
2658
2659 static void __exit vmx_exit(void)
2660 {
2661         __free_page(vmx_io_bitmap_b);
2662         __free_page(vmx_io_bitmap_a);
2663
2664         kvm_exit();
2665 }
2666
2667 module_init(vmx_init)
2668 module_exit(vmx_exit)