2 Conexant cx24123/cx24109 - DVB QPSK Satellite demod/tuner driver
4 Copyright (C) 2005 Steven Toth <stoth@hauppauge.com>
6 Support for KWorld DVB-S 100 by Vadim Catana <skystar@moldova.cc>
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/slab.h>
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/init.h>
29 #include "dvb_frontend.h"
34 static int force_band;
36 #define dprintk(args...) \
38 if (debug) printk (KERN_DEBUG "cx24123: " args); \
43 struct i2c_adapter* i2c;
44 struct dvb_frontend_ops ops;
45 const struct cx24123_config* config;
47 struct dvb_frontend frontend;
52 /* Some PLL specifics for tuning */
59 /* The Demod/Tuner can't easily provide these, we cache them */
61 u32 currentsymbolrate;
64 /* Various tuner defaults need to be established for a given symbol rate Sps */
72 } cx24123_AGC_vals[] =
75 .symbolrate_low = 1000000,
76 .symbolrate_high = 4999999,
77 /* the specs recommend other values for VGA offsets,
78 but tests show they are wrong */
79 .VGAprogdata = (1 << 19) | (0x180 << 9) | 0x1e0,
80 .VCAprogdata = (2 << 19) | (0x07 << 9) | 0x07,
81 .FILTune = 0x27f /* 0.41 V */
84 .symbolrate_low = 5000000,
85 .symbolrate_high = 14999999,
86 .VGAprogdata = (1 << 19) | (0x180 << 9) | 0x1e0,
87 .VCAprogdata = (2 << 19) | (0x07 << 9) | 0x1f,
88 .FILTune = 0x317 /* 0.90 V */
91 .symbolrate_low = 15000000,
92 .symbolrate_high = 45000000,
93 .VGAprogdata = (1 << 19) | (0x100 << 9) | 0x180,
94 .VCAprogdata = (2 << 19) | (0x07 << 9) | 0x3f,
95 .FILTune = 0x145 /* 2.70 V */
100 * Various tuner defaults need to be established for a given frequency kHz.
101 * fixme: The bounds on the bands do not match the doc in real life.
102 * fixme: Some of them have been moved, other might need adjustment.
110 } cx24123_bandselect_vals[] =
115 .freq_high = 1074999,
117 .progdata = (0 << 19) | (0 << 9) | 0x40,
123 .freq_high = 1177999,
125 .progdata = (0 << 19) | (0 << 9) | 0x80,
131 .freq_high = 1295999,
133 .progdata = (0 << 19) | (1 << 9) | 0x01,
139 .freq_high = 1431999,
141 .progdata = (0 << 19) | (1 << 9) | 0x02,
147 .freq_high = 1575999,
149 .progdata = (0 << 19) | (1 << 9) | 0x04,
155 .freq_high = 1717999,
157 .progdata = (0 << 19) | (1 << 9) | 0x08,
163 .freq_high = 1855999,
165 .progdata = (0 << 19) | (1 << 9) | 0x10,
171 .freq_high = 2035999,
173 .progdata = (0 << 19) | (1 << 9) | 0x20,
179 .freq_high = 2150000,
181 .progdata = (0 << 19) | (1 << 9) | 0x40,
188 } cx24123_regdata[] =
190 {0x00, 0x03}, /* Reset system */
191 {0x00, 0x00}, /* Clear reset */
192 {0x03, 0x07}, /* QPSK, DVB, Auto Acquisition (default) */
193 {0x04, 0x10}, /* MPEG */
194 {0x05, 0x04}, /* MPEG */
195 {0x06, 0x31}, /* MPEG (default) */
196 {0x0b, 0x00}, /* Freq search start point (default) */
197 {0x0c, 0x00}, /* Demodulator sample gain (default) */
198 {0x0d, 0x02}, /* Frequency search range = Fsymbol / 4 (default) */
199 {0x0e, 0x03}, /* Default non-inverted, FEC 3/4 (default) */
200 {0x0f, 0xfe}, /* FEC search mask (all supported codes) */
201 {0x10, 0x01}, /* Default search inversion, no repeat (default) */
202 {0x16, 0x00}, /* Enable reading of frequency */
203 {0x17, 0x01}, /* Enable EsNO Ready Counter */
204 {0x1c, 0x80}, /* Enable error counter */
205 {0x20, 0x00}, /* Tuner burst clock rate = 500KHz */
206 {0x21, 0x15}, /* Tuner burst mode, word length = 0x15 */
207 {0x28, 0x00}, /* Enable FILTERV with positive pol., DiSEqC 2.x off */
208 {0x29, 0x00}, /* DiSEqC LNB_DC off */
209 {0x2a, 0xb0}, /* DiSEqC Parameters (default) */
210 {0x2b, 0x73}, /* DiSEqC Tone Frequency (default) */
211 {0x2c, 0x00}, /* DiSEqC Message (0x2c - 0x31) */
217 {0x32, 0x8c}, /* DiSEqC Parameters (default) */
218 {0x33, 0x00}, /* Interrupts off (0x33 - 0x34) */
220 {0x35, 0x03}, /* DiSEqC Tone Amplitude (default) */
221 {0x36, 0x02}, /* DiSEqC Parameters (default) */
222 {0x37, 0x3a}, /* DiSEqC Parameters (default) */
223 {0x3a, 0x00}, /* Enable AGC accumulator (for signal strength) */
224 {0x44, 0x00}, /* Constellation (default) */
225 {0x45, 0x00}, /* Symbol count (default) */
226 {0x46, 0x0d}, /* Symbol rate estimator on (default) */
227 {0x56, 0x41}, /* Various (default) */
228 {0x57, 0xff}, /* Error Counter Window (default) */
229 {0x67, 0x83}, /* Non-DCII symbol clock */
232 static int cx24123_writereg(struct cx24123_state* state, int reg, int data)
234 u8 buf[] = { reg, data };
235 struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };
239 printk("cx24123: %s: write reg 0x%02x, value 0x%02x\n",
240 __FUNCTION__,reg, data);
242 if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) {
243 printk("%s: writereg error(err == %i, reg == 0x%02x,"
244 " data == 0x%02x)\n", __FUNCTION__, err, reg, data);
251 static int cx24123_readreg(struct cx24123_state* state, u8 reg)
256 struct i2c_msg msg[] = {
257 { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 },
258 { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 }
261 ret = i2c_transfer(state->i2c, msg, 2);
264 printk("%s: reg=0x%x (error=%d)\n", __FUNCTION__, reg, ret);
269 printk("cx24123: read reg 0x%02x, value 0x%02x\n",reg, ret);
274 static int cx24123_set_inversion(struct cx24123_state* state, fe_spectral_inversion_t inversion)
276 u8 nom_reg = cx24123_readreg(state, 0x0e);
277 u8 auto_reg = cx24123_readreg(state, 0x10);
281 dprintk("%s: inversion off\n",__FUNCTION__);
282 cx24123_writereg(state, 0x0e, nom_reg & ~0x80);
283 cx24123_writereg(state, 0x10, auto_reg | 0x80);
286 dprintk("%s: inversion on\n",__FUNCTION__);
287 cx24123_writereg(state, 0x0e, nom_reg | 0x80);
288 cx24123_writereg(state, 0x10, auto_reg | 0x80);
291 dprintk("%s: inversion auto\n",__FUNCTION__);
292 cx24123_writereg(state, 0x10, auto_reg & ~0x80);
301 static int cx24123_get_inversion(struct cx24123_state* state, fe_spectral_inversion_t *inversion)
305 val = cx24123_readreg(state, 0x1b) >> 7;
308 dprintk("%s: read inversion off\n",__FUNCTION__);
309 *inversion = INVERSION_OFF;
311 dprintk("%s: read inversion on\n",__FUNCTION__);
312 *inversion = INVERSION_ON;
318 static int cx24123_set_fec(struct cx24123_state* state, fe_code_rate_t fec)
320 u8 nom_reg = cx24123_readreg(state, 0x0e) & ~0x07;
322 if ( (fec < FEC_NONE) || (fec > FEC_AUTO) )
327 dprintk("%s: set FEC to 1/2\n",__FUNCTION__);
328 cx24123_writereg(state, 0x0e, nom_reg | 0x01);
329 cx24123_writereg(state, 0x0f, 0x02);
332 dprintk("%s: set FEC to 2/3\n",__FUNCTION__);
333 cx24123_writereg(state, 0x0e, nom_reg | 0x02);
334 cx24123_writereg(state, 0x0f, 0x04);
337 dprintk("%s: set FEC to 3/4\n",__FUNCTION__);
338 cx24123_writereg(state, 0x0e, nom_reg | 0x03);
339 cx24123_writereg(state, 0x0f, 0x08);
342 dprintk("%s: set FEC to 4/5\n",__FUNCTION__);
343 cx24123_writereg(state, 0x0e, nom_reg | 0x04);
344 cx24123_writereg(state, 0x0f, 0x10);
347 dprintk("%s: set FEC to 5/6\n",__FUNCTION__);
348 cx24123_writereg(state, 0x0e, nom_reg | 0x05);
349 cx24123_writereg(state, 0x0f, 0x20);
352 dprintk("%s: set FEC to 6/7\n",__FUNCTION__);
353 cx24123_writereg(state, 0x0e, nom_reg | 0x06);
354 cx24123_writereg(state, 0x0f, 0x40);
357 dprintk("%s: set FEC to 7/8\n",__FUNCTION__);
358 cx24123_writereg(state, 0x0e, nom_reg | 0x07);
359 cx24123_writereg(state, 0x0f, 0x80);
362 dprintk("%s: set FEC to auto\n",__FUNCTION__);
363 cx24123_writereg(state, 0x0f, 0xfe);
372 static int cx24123_get_fec(struct cx24123_state* state, fe_code_rate_t *fec)
376 ret = cx24123_readreg (state, 0x1b);
404 /* this can happen when there's no lock */
411 /* Approximation of closest integer of log2(a/b). It actually gives the
412 lowest integer i such that 2^i >= round(a/b) */
413 static u32 cx24123_int_log2(u32 a, u32 b)
415 u32 exp, nearest = 0;
417 if(a % b >= b / 2) ++div;
420 for(exp = 1; div > exp; nearest++)
426 static int cx24123_set_symbolrate(struct cx24123_state* state, u32 srate)
428 u32 tmp, sample_rate, ratio, sample_gain;
431 /* check if symbol rate is within limits */
432 if ((srate > state->ops.info.symbol_rate_max) ||
433 (srate < state->ops.info.symbol_rate_min))
436 /* choose the sampling rate high enough for the required operation,
437 while optimizing the power consumed by the demodulator */
438 if (srate < (XTAL*2)/2)
440 else if (srate < (XTAL*3)/2)
442 else if (srate < (XTAL*4)/2)
444 else if (srate < (XTAL*5)/2)
446 else if (srate < (XTAL*6)/2)
448 else if (srate < (XTAL*7)/2)
450 else if (srate < (XTAL*8)/2)
456 sample_rate = pll_mult * XTAL;
459 SYSSymbolRate[21:0] = (srate << 23) / sample_rate
461 We have to use 32 bit unsigned arithmetic without precision loss.
462 The maximum srate is 45000000 or 0x02AEA540. This number has
463 only 6 clear bits on top, hence we can shift it left only 6 bits
464 at a time. Borrowed from cx24110.c
468 ratio = tmp / sample_rate;
470 tmp = (tmp % sample_rate) << 6;
471 ratio = (ratio << 6) + (tmp / sample_rate);
473 tmp = (tmp % sample_rate) << 6;
474 ratio = (ratio << 6) + (tmp / sample_rate);
476 tmp = (tmp % sample_rate) << 5;
477 ratio = (ratio << 5) + (tmp / sample_rate);
480 cx24123_writereg(state, 0x01, pll_mult * 6);
482 cx24123_writereg(state, 0x08, (ratio >> 16) & 0x3f );
483 cx24123_writereg(state, 0x09, (ratio >> 8) & 0xff );
484 cx24123_writereg(state, 0x0a, (ratio ) & 0xff );
486 /* also set the demodulator sample gain */
487 sample_gain = cx24123_int_log2(sample_rate, srate);
488 tmp = cx24123_readreg(state, 0x0c) & ~0xe0;
489 cx24123_writereg(state, 0x0c, tmp | sample_gain << 5);
491 dprintk("%s: srate=%d, ratio=0x%08x, sample_rate=%i sample_gain=%d\n", __FUNCTION__, srate, ratio, sample_rate, sample_gain);
497 * Based on the required frequency and symbolrate, the tuner AGC has to be configured
498 * and the correct band selected. Calculate those values
500 static int cx24123_pll_calculate(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
502 struct cx24123_state *state = fe->demodulator_priv;
503 u32 ndiv = 0, adiv = 0, vco_div = 0;
507 int num_bands = sizeof(cx24123_bandselect_vals) / sizeof(cx24123_bandselect_vals[0]);
509 /* Defaults for low freq, low rate */
510 state->VCAarg = cx24123_AGC_vals[0].VCAprogdata;
511 state->VGAarg = cx24123_AGC_vals[0].VGAprogdata;
512 state->bandselectarg = cx24123_bandselect_vals[0].progdata;
513 vco_div = cx24123_bandselect_vals[0].VCOdivider;
515 /* For the given symbol rate, determine the VCA, VGA and FILTUNE programming bits */
516 for (i = 0; i < sizeof(cx24123_AGC_vals) / sizeof(cx24123_AGC_vals[0]); i++)
518 if ((cx24123_AGC_vals[i].symbolrate_low <= p->u.qpsk.symbol_rate) &&
519 (cx24123_AGC_vals[i].symbolrate_high >= p->u.qpsk.symbol_rate) ) {
520 state->VCAarg = cx24123_AGC_vals[i].VCAprogdata;
521 state->VGAarg = cx24123_AGC_vals[i].VGAprogdata;
522 state->FILTune = cx24123_AGC_vals[i].FILTune;
526 /* determine the band to use */
527 if(force_band < 1 || force_band > num_bands)
529 for (i = 0; i < num_bands; i++)
531 if ((cx24123_bandselect_vals[i].freq_low <= p->frequency) &&
532 (cx24123_bandselect_vals[i].freq_high >= p->frequency) )
537 band = force_band - 1;
539 state->bandselectarg = cx24123_bandselect_vals[band].progdata;
540 vco_div = cx24123_bandselect_vals[band].VCOdivider;
542 /* determine the charge pump current */
543 if ( p->frequency < (cx24123_bandselect_vals[band].freq_low + cx24123_bandselect_vals[band].freq_high)/2 )
548 /* Determine the N/A dividers for the requested lband freq (in kHz). */
549 /* Note: the reference divider R=10, frequency is in KHz, XTAL is in Hz */
550 ndiv = ( ((p->frequency * vco_div * 10) / (2 * XTAL / 1000)) / 32) & 0x1ff;
551 adiv = ( ((p->frequency * vco_div * 10) / (2 * XTAL / 1000)) % 32) & 0x1f;
556 /* control bits 11, refdiv 11, charge pump polarity 1, charge pump current, ndiv, adiv */
557 state->pllarg = (3 << 19) | (3 << 17) | (1 << 16) | (pump << 14) | (ndiv << 5) | adiv;
563 * Tuner data is 21 bits long, must be left-aligned in data.
564 * Tuner cx24109 is written through a dedicated 3wire interface on the demod chip.
566 static int cx24123_pll_writereg(struct dvb_frontend* fe, struct dvb_frontend_parameters *p, u32 data)
568 struct cx24123_state *state = fe->demodulator_priv;
569 unsigned long timeout;
571 dprintk("%s: pll writereg called, data=0x%08x\n",__FUNCTION__,data);
573 /* align the 21 bytes into to bit23 boundary */
576 /* Reset the demod pll word length to 0x15 bits */
577 cx24123_writereg(state, 0x21, 0x15);
579 /* write the msb 8 bits, wait for the send to be completed */
580 timeout = jiffies + msecs_to_jiffies(40);
581 cx24123_writereg(state, 0x22, (data >> 16) & 0xff);
582 while ((cx24123_readreg(state, 0x20) & 0x40) == 0) {
583 if (time_after(jiffies, timeout)) {
584 printk("%s: demodulator is not responding, possibly hung, aborting.\n", __FUNCTION__);
590 /* send another 8 bytes, wait for the send to be completed */
591 timeout = jiffies + msecs_to_jiffies(40);
592 cx24123_writereg(state, 0x22, (data>>8) & 0xff );
593 while ((cx24123_readreg(state, 0x20) & 0x40) == 0) {
594 if (time_after(jiffies, timeout)) {
595 printk("%s: demodulator is not responding, possibly hung, aborting.\n", __FUNCTION__);
601 /* send the lower 5 bits of this byte, padded with 3 LBB, wait for the send to be completed */
602 timeout = jiffies + msecs_to_jiffies(40);
603 cx24123_writereg(state, 0x22, (data) & 0xff );
604 while ((cx24123_readreg(state, 0x20) & 0x80)) {
605 if (time_after(jiffies, timeout)) {
606 printk("%s: demodulator is not responding, possibly hung, aborting.\n", __FUNCTION__);
612 /* Trigger the demod to configure the tuner */
613 cx24123_writereg(state, 0x20, cx24123_readreg(state, 0x20) | 2);
614 cx24123_writereg(state, 0x20, cx24123_readreg(state, 0x20) & 0xfd);
619 static int cx24123_pll_tune(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
621 struct cx24123_state *state = fe->demodulator_priv;
624 dprintk("frequency=%i\n", p->frequency);
626 if (cx24123_pll_calculate(fe, p) != 0) {
627 printk("%s: cx24123_pll_calcutate failed\n",__FUNCTION__);
631 /* Write the new VCO/VGA */
632 cx24123_pll_writereg(fe, p, state->VCAarg);
633 cx24123_pll_writereg(fe, p, state->VGAarg);
635 /* Write the new bandselect and pll args */
636 cx24123_pll_writereg(fe, p, state->bandselectarg);
637 cx24123_pll_writereg(fe, p, state->pllarg);
639 /* set the FILTUNE voltage */
640 val = cx24123_readreg(state, 0x28) & ~0x3;
641 cx24123_writereg(state, 0x27, state->FILTune >> 2);
642 cx24123_writereg(state, 0x28, val | (state->FILTune & 0x3));
644 dprintk("%s: pll tune VCA=%d, band=%d, pll=%d\n",__FUNCTION__,state->VCAarg,
645 state->bandselectarg,state->pllarg);
650 static int cx24123_initfe(struct dvb_frontend* fe)
652 struct cx24123_state *state = fe->demodulator_priv;
655 dprintk("%s: init frontend\n",__FUNCTION__);
657 /* Configure the demod to a good set of defaults */
658 for (i = 0; i < sizeof(cx24123_regdata) / sizeof(cx24123_regdata[0]); i++)
659 cx24123_writereg(state, cx24123_regdata[i].reg, cx24123_regdata[i].data);
664 static int cx24123_set_voltage(struct dvb_frontend* fe, fe_sec_voltage_t voltage)
666 struct cx24123_state *state = fe->demodulator_priv;
669 val = cx24123_readreg(state, 0x29) & ~0x40;
673 dprintk("%s: setting voltage 13V\n", __FUNCTION__);
674 return cx24123_writereg(state, 0x29, val | 0x80);
676 dprintk("%s: setting voltage 18V\n", __FUNCTION__);
677 return cx24123_writereg(state, 0x29, val & 0x7f);
685 /* wait for diseqc queue to become ready (or timeout) */
686 static void cx24123_wait_for_diseqc(struct cx24123_state *state)
688 unsigned long timeout = jiffies + msecs_to_jiffies(200);
689 while (!(cx24123_readreg(state, 0x29) & 0x40)) {
690 if(time_after(jiffies, timeout)) {
691 printk("%s: diseqc queue not ready, command may be lost.\n", __FUNCTION__);
698 static int cx24123_send_diseqc_msg(struct dvb_frontend* fe, struct dvb_diseqc_master_cmd *cmd)
700 struct cx24123_state *state = fe->demodulator_priv;
703 dprintk("%s:\n",__FUNCTION__);
705 /* stop continuous tone if enabled */
706 tone = cx24123_readreg(state, 0x29);
708 cx24123_writereg(state, 0x29, tone & ~0x50);
710 /* wait for diseqc queue ready */
711 cx24123_wait_for_diseqc(state);
713 /* select tone mode */
714 cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) & 0xfb);
716 for (i = 0; i < cmd->msg_len; i++)
717 cx24123_writereg(state, 0x2C + i, cmd->msg[i]);
719 val = cx24123_readreg(state, 0x29);
720 cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40) | ((cmd->msg_len-3) & 3));
722 /* wait for diseqc message to finish sending */
723 cx24123_wait_for_diseqc(state);
725 /* restart continuous tone if enabled */
727 cx24123_writereg(state, 0x29, tone & ~0x40);
733 static int cx24123_diseqc_send_burst(struct dvb_frontend* fe, fe_sec_mini_cmd_t burst)
735 struct cx24123_state *state = fe->demodulator_priv;
738 dprintk("%s:\n", __FUNCTION__);
740 /* stop continuous tone if enabled */
741 tone = cx24123_readreg(state, 0x29);
743 cx24123_writereg(state, 0x29, tone & ~0x50);
745 /* wait for diseqc queue ready */
746 cx24123_wait_for_diseqc(state);
748 /* select tone mode */
749 cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) | 0x4);
751 val = cx24123_readreg(state, 0x29);
752 if (burst == SEC_MINI_A)
753 cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40 | 0x00));
754 else if (burst == SEC_MINI_B)
755 cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40 | 0x08));
759 cx24123_wait_for_diseqc(state);
760 cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) & 0xfb);
762 /* restart continuous tone if enabled */
764 cx24123_writereg(state, 0x29, tone & ~0x40);
769 static int cx24123_read_status(struct dvb_frontend* fe, fe_status_t* status)
771 struct cx24123_state *state = fe->demodulator_priv;
773 int sync = cx24123_readreg(state, 0x14);
774 int lock = cx24123_readreg(state, 0x20);
778 *status |= FE_HAS_SIGNAL;
780 *status |= FE_HAS_CARRIER;
782 *status |= FE_HAS_VITERBI;
784 *status |= FE_HAS_SYNC;
786 *status |= FE_HAS_LOCK;
792 * Configured to return the measurement of errors in blocks, because no UCBLOCKS value
793 * is available, so this value doubles up to satisfy both measurements
795 static int cx24123_read_ber(struct dvb_frontend* fe, u32* ber)
797 struct cx24123_state *state = fe->demodulator_priv;
800 ((cx24123_readreg(state, 0x1c) & 0x3f) << 16) |
801 (cx24123_readreg(state, 0x1d) << 8 |
802 cx24123_readreg(state, 0x1e));
804 /* Do the signal quality processing here, it's derived from the BER. */
805 /* Scale the BER from a 24bit to a SNR 16 bit where higher = better */
806 if (state->lastber < 5000)
807 state->snr = 655*100;
808 else if ( (state->lastber >= 5000) && (state->lastber < 55000) )
810 else if ( (state->lastber >= 55000) && (state->lastber < 150000) )
812 else if ( (state->lastber >= 150000) && (state->lastber < 250000) )
814 else if ( (state->lastber >= 250000) && (state->lastber < 450000) )
819 dprintk("%s: BER = %d, S/N index = %d\n",__FUNCTION__,state->lastber, state->snr);
821 *ber = state->lastber;
826 static int cx24123_read_signal_strength(struct dvb_frontend* fe, u16* signal_strength)
828 struct cx24123_state *state = fe->demodulator_priv;
829 *signal_strength = cx24123_readreg(state, 0x3b) << 8; /* larger = better */
831 dprintk("%s: Signal strength = %d\n",__FUNCTION__,*signal_strength);
836 static int cx24123_read_snr(struct dvb_frontend* fe, u16* snr)
838 struct cx24123_state *state = fe->demodulator_priv;
841 dprintk("%s: read S/N index = %d\n",__FUNCTION__,*snr);
846 static int cx24123_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
848 struct cx24123_state *state = fe->demodulator_priv;
849 *ucblocks = state->lastber;
851 dprintk("%s: ucblocks (ber) = %d\n",__FUNCTION__,*ucblocks);
856 static int cx24123_set_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
858 struct cx24123_state *state = fe->demodulator_priv;
860 dprintk("%s: set_frontend\n",__FUNCTION__);
862 if (state->config->set_ts_params)
863 state->config->set_ts_params(fe, 0);
865 state->currentfreq=p->frequency;
866 state->currentsymbolrate = p->u.qpsk.symbol_rate;
868 cx24123_set_inversion(state, p->inversion);
869 cx24123_set_fec(state, p->u.qpsk.fec_inner);
870 cx24123_set_symbolrate(state, p->u.qpsk.symbol_rate);
871 cx24123_pll_tune(fe, p);
873 /* Enable automatic aquisition and reset cycle */
874 cx24123_writereg(state, 0x03, (cx24123_readreg(state, 0x03) | 0x07));
875 cx24123_writereg(state, 0x00, 0x10);
876 cx24123_writereg(state, 0x00, 0);
881 static int cx24123_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
883 struct cx24123_state *state = fe->demodulator_priv;
885 dprintk("%s: get_frontend\n",__FUNCTION__);
887 if (cx24123_get_inversion(state, &p->inversion) != 0) {
888 printk("%s: Failed to get inversion status\n",__FUNCTION__);
891 if (cx24123_get_fec(state, &p->u.qpsk.fec_inner) != 0) {
892 printk("%s: Failed to get fec status\n",__FUNCTION__);
895 p->frequency = state->currentfreq;
896 p->u.qpsk.symbol_rate = state->currentsymbolrate;
901 static int cx24123_set_tone(struct dvb_frontend* fe, fe_sec_tone_mode_t tone)
903 struct cx24123_state *state = fe->demodulator_priv;
906 /* wait for diseqc queue ready */
907 cx24123_wait_for_diseqc(state);
909 val = cx24123_readreg(state, 0x29) & ~0x40;
913 dprintk("%s: setting tone on\n", __FUNCTION__);
914 return cx24123_writereg(state, 0x29, val | 0x10);
916 dprintk("%s: setting tone off\n",__FUNCTION__);
917 return cx24123_writereg(state, 0x29, val & 0xef);
919 printk("%s: CASE reached default with tone=%d\n", __FUNCTION__, tone);
926 static void cx24123_release(struct dvb_frontend* fe)
928 struct cx24123_state* state = fe->demodulator_priv;
929 dprintk("%s\n",__FUNCTION__);
933 static struct dvb_frontend_ops cx24123_ops;
935 struct dvb_frontend* cx24123_attach(const struct cx24123_config* config,
936 struct i2c_adapter* i2c)
938 struct cx24123_state* state = NULL;
941 dprintk("%s\n",__FUNCTION__);
943 /* allocate memory for the internal state */
944 state = kmalloc(sizeof(struct cx24123_state), GFP_KERNEL);
946 printk("Unable to kmalloc\n");
950 /* setup the state */
951 state->config = config;
953 memcpy(&state->ops, &cx24123_ops, sizeof(struct dvb_frontend_ops));
958 state->bandselectarg = 0;
960 state->currentfreq = 0;
961 state->currentsymbolrate = 0;
963 /* check if the demod is there */
964 ret = cx24123_readreg(state, 0x00);
965 if ((ret != 0xd1) && (ret != 0xe1)) {
966 printk("Version != d1 or e1\n");
970 /* create dvb_frontend */
971 state->frontend.ops = &state->ops;
972 state->frontend.demodulator_priv = state;
973 return &state->frontend;
981 static struct dvb_frontend_ops cx24123_ops = {
984 .name = "Conexant CX24123/CX24109",
986 .frequency_min = 950000,
987 .frequency_max = 2150000,
988 .frequency_stepsize = 1011, /* kHz for QPSK frontends */
989 .frequency_tolerance = 5000,
990 .symbol_rate_min = 1000000,
991 .symbol_rate_max = 45000000,
992 .caps = FE_CAN_INVERSION_AUTO |
993 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
994 FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 |
995 FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
996 FE_CAN_QPSK | FE_CAN_RECOVER
999 .release = cx24123_release,
1001 .init = cx24123_initfe,
1002 .set_frontend = cx24123_set_frontend,
1003 .get_frontend = cx24123_get_frontend,
1004 .read_status = cx24123_read_status,
1005 .read_ber = cx24123_read_ber,
1006 .read_signal_strength = cx24123_read_signal_strength,
1007 .read_snr = cx24123_read_snr,
1008 .read_ucblocks = cx24123_read_ucblocks,
1009 .diseqc_send_master_cmd = cx24123_send_diseqc_msg,
1010 .diseqc_send_burst = cx24123_diseqc_send_burst,
1011 .set_tone = cx24123_set_tone,
1012 .set_voltage = cx24123_set_voltage,
1015 module_param(debug, int, 0644);
1016 MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)");
1018 module_param(force_band, int, 0644);
1019 MODULE_PARM_DESC(force_band, "Force a specific band select (1-9, default:off).");
1021 MODULE_DESCRIPTION("DVB Frontend module for Conexant cx24123/cx24109 hardware");
1022 MODULE_AUTHOR("Steven Toth");
1023 MODULE_LICENSE("GPL");
1025 EXPORT_SYMBOL(cx24123_attach);