drivers/media/video/cx23885/cx23885-core.c

   1 /*
   2  *  Driver for the Conexant CX23885 PCIe bridge
   3  *
   4  *  Copyright (c) 2006 Steven Toth <stoth@hauppauge.com>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License, or
   9  *  (at your option) any later version.
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *
  15  *  GNU General Public License for more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License
  18  *  along with this program; if not, write to the Free Software
  19  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20  */
  21
  22 #include <linux/init.h>
  23 #include <linux/list.h>
  24 #include <linux/module.h>
  25 #include <linux/moduleparam.h>
  26 #include <linux/kmod.h>
  27 #include <linux/kernel.h>
  28 #include <linux/slab.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/delay.h>
  31 #include <asm/div64.h>
  32
  33 #include "cx23885.h"
  34
  35 MODULE_DESCRIPTION("Driver for cx23885 based TV cards");
  36 MODULE_AUTHOR("Steven Toth <stoth@hauppauge.com>");
  37 MODULE_LICENSE("GPL");
  38
  39 static unsigned int debug = 0;
  40 module_param(debug,int,0644);
  41 MODULE_PARM_DESC(debug,"enable debug messages");
  42
  43 static unsigned int card[]  = {[0 ... (CX23885_MAXBOARDS - 1)] = UNSET };
  44 module_param_array(card,  int, NULL, 0444);
  45 MODULE_PARM_DESC(card,"card type");
  46
  47 #define dprintk(level,fmt, arg...)      if (debug >= level) \
  48         printk(KERN_DEBUG "%s/0: " fmt, dev->name , ## arg)
  49
  50 static unsigned int cx23885_devcount;
  51
  52 static DEFINE_MUTEX(devlist);
  53 static LIST_HEAD(cx23885_devlist);
  54
  55 #define NO_SYNC_LINE (-1U)
  56
  57 /*
  58  * CX23885 Assumptions
  59  * 1 line = 16 bytes of CDT
  60  * cmds size = 80
  61  * cdt size = 16 * linesize
  62  * iqsize = 64
  63  * maxlines = 6
  64  *
  65  * Address Space:
  66  * 0x00000000 0x00008fff FIFO clusters
  67  * 0x00010000 0x000104af Channel Management Data Structures
  68  * 0x000104b0 0x000104ff Free
  69  * 0x00010500 0x000108bf 15 channels * iqsize
  70  * 0x000108c0 0x000108ff Free
  71  * 0x00010900 0x00010e9f IQ's + Cluster Descriptor Tables
  72  *                       15 channels * (iqsize + (maxlines * linesize))
  73  * 0x00010ea0 0x00010xxx Free
  74  */
  75
  76 struct sram_channel cx23885_sram_channels[] = {
  77         [SRAM_CH01] = {
  78                 .name           = "test ch1",
  79                 .cmds_start     = 0x10000,
  80                 .ctrl_start     = 0x10500,
  81                 .cdt            = 0x10900,
  82                 .fifo_start     = 0x3000,
  83                 .fifo_size      = 0x1000,
  84                 .ptr1_reg       = DMA1_PTR1,
  85                 .ptr2_reg       = DMA1_PTR2,
  86                 .cnt1_reg       = DMA1_CNT1,
  87                 .cnt2_reg       = DMA1_CNT2,
  88                 .jumponly       = 1,
  89         },
  90         [SRAM_CH02] = {
  91                 .name           = "ch2",
  92                 .cmds_start     = 0x0,
  93                 .ctrl_start     = 0x0,
  94                 .cdt            = 0x0,
  95                 .fifo_start     = 0x0,
  96                 .fifo_size      = 0x0,
  97                 .ptr1_reg       = DMA2_PTR1,
  98                 .ptr2_reg       = DMA2_PTR2,
  99                 .cnt1_reg       = DMA2_CNT1,
 100                 .cnt2_reg       = DMA2_CNT2,
 101         },
 102         [SRAM_CH03] = {
 103                 .name           = "ch3",
 104                 .cmds_start     = 0x0,
 105                 .ctrl_start     = 0x0,
 106                 .cdt            = 0x0,
 107                 .fifo_start     = 0x0,
 108                 .fifo_size      = 0x0,
 109                 .ptr1_reg       = DMA3_PTR1,
 110                 .ptr2_reg       = DMA3_PTR2,
 111                 .cnt1_reg       = DMA3_CNT1,
 112                 .cnt2_reg       = DMA3_CNT2,
 113         },
 114         [SRAM_CH04] = {
 115                 .name           = "ch4",
 116                 .cmds_start     = 0x0,
 117                 .ctrl_start     = 0x0,
 118                 .cdt            = 0x0,
 119                 .fifo_start     = 0x0,
 120                 .fifo_size      = 0x0,
 121                 .ptr1_reg       = DMA4_PTR1,
 122                 .ptr2_reg       = DMA4_PTR2,
 123                 .cnt1_reg       = DMA4_CNT1,
 124                 .cnt2_reg       = DMA4_CNT2,
 125         },
 126         [SRAM_CH05] = {
 127                 .name           = "ch5",
 128                 .cmds_start     = 0x0,
 129                 .ctrl_start     = 0x0,
 130                 .cdt            = 0x0,
 131                 .fifo_start     = 0x0,
 132                 .fifo_size      = 0x0,
 133                 .ptr1_reg       = DMA5_PTR1,
 134                 .ptr2_reg       = DMA5_PTR2,
 135                 .cnt1_reg       = DMA5_CNT1,
 136                 .cnt2_reg       = DMA5_CNT2,
 137         },
 138         [SRAM_CH06] = {
 139                 .name           = "TS2 C",
 140                 .cmds_start     = 0x10140,
 141                 .ctrl_start     = 0x10680,
 142                 .cdt            = 0x10480,
 143                 .fifo_start     = 0x6000,
 144                 .fifo_size      = 0x1000,
 145                 .ptr1_reg       = DMA5_PTR1,
 146                 .ptr2_reg       = DMA5_PTR2,
 147                 .cnt1_reg       = DMA5_CNT1,
 148                 .cnt2_reg       = DMA5_CNT2,
 149         },
 150         [SRAM_CH07] = {
 151                 .name           = "ch7",
 152                 .cmds_start     = 0x0,
 153                 .ctrl_start     = 0x0,
 154                 .cdt            = 0x0,
 155                 .fifo_start     = 0x0,
 156                 .fifo_size      = 0x0,
 157                 .ptr1_reg       = DMA6_PTR1,
 158                 .ptr2_reg       = DMA6_PTR2,
 159                 .cnt1_reg       = DMA6_CNT1,
 160                 .cnt2_reg       = DMA6_CNT2,
 161         },
 162         [SRAM_CH08] = {
 163                 .name           = "ch8",
 164                 .cmds_start     = 0x0,
 165                 .ctrl_start     = 0x0,
 166                 .cdt            = 0x0,
 167                 .fifo_start     = 0x0,
 168                 .fifo_size      = 0x0,
 169                 .ptr1_reg       = DMA7_PTR1,
 170                 .ptr2_reg       = DMA7_PTR2,
 171                 .cnt1_reg       = DMA7_CNT1,
 172                 .cnt2_reg       = DMA7_CNT2,
 173         },
 174         [SRAM_CH09] = {
 175                 .name           = "ch9",
 176                 .cmds_start     = 0x0,
 177                 .ctrl_start     = 0x0,
 178                 .cdt            = 0x0,
 179                 .fifo_start     = 0x0,
 180                 .fifo_size      = 0x0,
 181                 .ptr1_reg       = DMA8_PTR1,
 182                 .ptr2_reg       = DMA8_PTR2,
 183                 .cnt1_reg       = DMA8_CNT1,
 184                 .cnt2_reg       = DMA8_CNT2,
 185         },
 186 };
 187
 188 /* FIXME, these allocations will change when
 189  * analog arrives. The be reviewed.
 190  * CX23887 Assumptions
 191  * 1 line = 16 bytes of CDT
 192  * cmds size = 80
 193  * cdt size = 16 * linesize
 194  * iqsize = 64
 195  * maxlines = 6
 196  *
 197  * Address Space:
 198  * 0x00000000 0x00008fff FIFO clusters
 199  * 0x00010000 0x000104af Channel Management Data Structures
 200  * 0x000104b0 0x000104ff Free
 201  * 0x00010500 0x000108bf 15 channels * iqsize
 202  * 0x000108c0 0x000108ff Free
 203  * 0x00010900 0x00010e9f IQ's + Cluster Descriptor Tables
 204  *                       15 channels * (iqsize + (maxlines * linesize))
 205  * 0x00010ea0 0x00010xxx Free
 206  */
 207
 208 struct sram_channel cx23887_sram_channels[] = {
 209         [SRAM_CH01] = {
 210                 .name           = "test ch1",
 211                 .cmds_start     = 0x0,
 212                 .ctrl_start     = 0x0,
 213                 .cdt            = 0x0,
 214                 .fifo_start     = 0x0,
 215                 .fifo_size      = 0x0,
 216                 .ptr1_reg       = DMA1_PTR1,
 217                 .ptr2_reg       = DMA1_PTR2,
 218                 .cnt1_reg       = DMA1_CNT1,
 219                 .cnt2_reg       = DMA1_CNT2,
 220         },
 221         [SRAM_CH02] = {
 222                 .name           = "ch2",
 223                 .cmds_start     = 0x0,
 224                 .ctrl_start     = 0x0,
 225                 .cdt            = 0x0,
 226                 .fifo_start     = 0x0,
 227                 .fifo_size      = 0x0,
 228                 .ptr1_reg       = DMA2_PTR1,
 229                 .ptr2_reg       = DMA2_PTR2,
 230                 .cnt1_reg       = DMA2_CNT1,
 231                 .cnt2_reg       = DMA2_CNT2,
 232         },
 233         [SRAM_CH03] = {
 234                 .name           = "ch3",
 235                 .cmds_start     = 0x0,
 236                 .ctrl_start     = 0x0,
 237                 .cdt            = 0x0,
 238                 .fifo_start     = 0x0,
 239                 .fifo_size      = 0x0,
 240                 .ptr1_reg       = DMA3_PTR1,
 241                 .ptr2_reg       = DMA3_PTR2,
 242                 .cnt1_reg       = DMA3_CNT1,
 243                 .cnt2_reg       = DMA3_CNT2,
 244         },
 245         [SRAM_CH04] = {
 246                 .name           = "ch4",
 247                 .cmds_start     = 0x0,
 248                 .ctrl_start     = 0x0,
 249                 .cdt            = 0x0,
 250                 .fifo_start     = 0x0,
 251                 .fifo_size      = 0x0,
 252                 .ptr1_reg       = DMA4_PTR1,
 253                 .ptr2_reg       = DMA4_PTR2,
 254                 .cnt1_reg       = DMA4_CNT1,
 255                 .cnt2_reg       = DMA4_CNT2,
 256         },
 257         [SRAM_CH05] = {
 258                 .name           = "ch5",
 259                 .cmds_start     = 0x0,
 260                 .ctrl_start     = 0x0,
 261                 .cdt            = 0x0,
 262                 .fifo_start     = 0x0,
 263                 .fifo_size      = 0x0,
 264                 .ptr1_reg       = DMA5_PTR1,
 265                 .ptr2_reg       = DMA5_PTR2,
 266                 .cnt1_reg       = DMA5_CNT1,
 267                 .cnt2_reg       = DMA5_CNT2,
 268         },
 269         [SRAM_CH06] = {
 270                 .name           = "TS2 C",
 271                 .cmds_start     = 0x10140,
 272                 .ctrl_start     = 0x10680,
 273                 .cdt            = 0x108d0,
 274                 .fifo_start     = 0x6000,
 275                 .fifo_size      = 0x1000,
 276                 .ptr1_reg       = DMA5_PTR1,
 277                 .ptr2_reg       = DMA5_PTR2,
 278                 .cnt1_reg       = DMA5_CNT1,
 279                 .cnt2_reg       = DMA5_CNT2,
 280         },
 281         [SRAM_CH07] = {
 282                 .name           = "ch7",
 283                 .cmds_start     = 0x0,
 284                 .ctrl_start     = 0x0,
 285                 .cdt            = 0x0,
 286                 .fifo_start     = 0x0,
 287                 .fifo_size      = 0x0,
 288                 .ptr1_reg       = DMA6_PTR1,
 289                 .ptr2_reg       = DMA6_PTR2,
 290                 .cnt1_reg       = DMA6_CNT1,
 291                 .cnt2_reg       = DMA6_CNT2,
 292         },
 293         [SRAM_CH08] = {
 294                 .name           = "ch8",
 295                 .cmds_start     = 0x0,
 296                 .ctrl_start     = 0x0,
 297                 .cdt            = 0x0,
 298                 .fifo_start     = 0x0,
 299                 .fifo_size      = 0x0,
 300                 .ptr1_reg       = DMA7_PTR1,
 301                 .ptr2_reg       = DMA7_PTR2,
 302                 .cnt1_reg       = DMA7_CNT1,
 303                 .cnt2_reg       = DMA7_CNT2,
 304         },
 305         [SRAM_CH09] = {
 306                 .name           = "ch9",
 307                 .cmds_start     = 0x0,
 308                 .ctrl_start     = 0x0,
 309                 .cdt            = 0x0,
 310                 .fifo_start     = 0x0,
 311                 .fifo_size      = 0x0,
 312                 .ptr1_reg       = DMA8_PTR1,
 313                 .ptr2_reg       = DMA8_PTR2,
 314                 .cnt1_reg       = DMA8_CNT1,
 315                 .cnt2_reg       = DMA8_CNT2,
 316         },
 317 };
 318
 319 static int cx23885_risc_decode(u32 risc)
 320 {
 321         static char *instr[16] = {
 322                 [ RISC_SYNC    >> 28 ] = "sync",
 323                 [ RISC_WRITE   >> 28 ] = "write",
 324                 [ RISC_WRITEC  >> 28 ] = "writec",
 325                 [ RISC_READ    >> 28 ] = "read",
 326                 [ RISC_READC   >> 28 ] = "readc",
 327                 [ RISC_JUMP    >> 28 ] = "jump",
 328                 [ RISC_SKIP    >> 28 ] = "skip",
 329                 [ RISC_WRITERM >> 28 ] = "writerm",
 330                 [ RISC_WRITECM >> 28 ] = "writecm",
 331                 [ RISC_WRITECR >> 28 ] = "writecr",
 332         };
 333         static int incr[16] = {
 334                 [ RISC_WRITE   >> 28 ] = 3, // 2
 335                 [ RISC_JUMP    >> 28 ] = 3, // 2
 336                 [ RISC_SKIP    >> 28 ] = 1,
 337                 [ RISC_SYNC    >> 28 ] = 1,
 338                 [ RISC_WRITERM >> 28 ] = 3,
 339                 [ RISC_WRITECM >> 28 ] = 3,
 340                 [ RISC_WRITECR >> 28 ] = 4,
 341         };
 342         static char *bits[] = {
 343                 "12",   "13",   "14",   "resync",
 344                 "cnt0", "cnt1", "18",   "19",
 345                 "20",   "21",   "22",   "23",
 346                 "irq1", "irq2", "eol",  "sol",
 347         };
 348         int i;
 349
 350         printk("0x%08x [ %s", risc,
 351                instr[risc >> 28] ? instr[risc >> 28] : "INVALID");
 352         for (i = ARRAY_SIZE(bits) - 1; i >= 0; i--)
 353                 if (risc & (1 << (i + 12)))
 354                         printk(" %s", bits[i]);
 355         printk(" count=%d ]\n", risc & 0xfff);
 356         return incr[risc >> 28] ? incr[risc >> 28] : 1;
 357 }
 358
 359 void cx23885_wakeup(struct cx23885_tsport *port,
 360                     struct cx23885_dmaqueue *q, u32 count)
 361 {
 362         struct cx23885_dev *dev = port->dev;
 363         struct cx23885_buffer *buf;
 364         int bc;
 365
 366         for (bc = 0;; bc++) {
 367                 if (list_empty(&q->active))
 368                         break;
 369                 buf = list_entry(q->active.next,
 370                                  struct cx23885_buffer, vb.queue);
 371
 372                 /* count comes from the hw and is is 16bit wide --
 373                  * this trick handles wrap-arounds correctly for
 374                  * up to 32767 buffers in flight... */
 375                 if ((s16) (count - buf->count) < 0)
 376                         break;
 377
 378                 do_gettimeofday(&buf->vb.ts);
 379                 dprintk(2, "[%p/%d] wakeup reg=%d buf=%d\n", buf, buf->vb.i,
 380                         count, buf->count);
 381                 buf->vb.state = STATE_DONE;
 382                 list_del(&buf->vb.queue);
 383                 wake_up(&buf->vb.done);
 384         }
 385         if (list_empty(&q->active)) {
 386                 del_timer(&q->timeout);
 387         } else {
 388                 mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
 389         }
 390         if (bc != 1)
 391                 printk("%s: %d buffers handled (should be 1)\n",
 392                        __FUNCTION__, bc);
 393 }
 394 void cx23885_sram_channel_dump(struct cx23885_dev *dev,
 395                                struct sram_channel *ch);
 396
 397 int cx23885_sram_channel_setup(struct cx23885_dev *dev,
 398                                struct sram_channel *ch,
 399                                unsigned int bpl, u32 risc)
 400 {
 401         unsigned int i, lines;
 402         u32 cdt;
 403
 404         if (ch->cmds_start == 0)
 405         {
 406                 dprintk(1, "%s() Erasing channel [%s]\n", __FUNCTION__,
 407                         ch->name);
 408                 cx_write(ch->ptr1_reg, 0);
 409                 cx_write(ch->ptr2_reg, 0);
 410                 cx_write(ch->cnt2_reg, 0);
 411                 cx_write(ch->cnt1_reg, 0);
 412                 return 0;
 413         } else {
 414                 dprintk(1, "%s() Configuring channel [%s]\n", __FUNCTION__,
 415                         ch->name);
 416         }
 417
 418         bpl   = (bpl + 7) & ~7; /* alignment */
 419         cdt   = ch->cdt;
 420         lines = ch->fifo_size / bpl;
 421         if (lines > 6)
 422                 lines = 6;
 423         BUG_ON(lines < 2);
 424
 425         cx_write(8 + 0, cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC) );
 426         cx_write(8 + 4, cpu_to_le32(8) );
 427         cx_write(8 + 8, cpu_to_le32(0) );
 428
 429         /* write CDT */
 430         for (i = 0; i < lines; i++) {
 431                 dprintk(2, "%s() 0x%08x <- 0x%08x\n", __FUNCTION__, cdt + 16*i,
 432                         ch->fifo_start + bpl*i);
 433                 cx_write(cdt + 16*i, ch->fifo_start + bpl*i);
 434                 cx_write(cdt + 16*i +  4, 0);
 435                 cx_write(cdt + 16*i +  8, 0);
 436                 cx_write(cdt + 16*i + 12, 0);
 437         }
 438
 439         /* write CMDS */
 440         if (ch->jumponly)
 441                 cx_write(ch->cmds_start +  0, 8);
 442         else
 443                 cx_write(ch->cmds_start +  0, risc);
 444         cx_write(ch->cmds_start +  4, 0); /* 64 bits 63-32 */
 445         cx_write(ch->cmds_start +  8, cdt);
 446         cx_write(ch->cmds_start + 12, (lines*16) >> 3);
 447         cx_write(ch->cmds_start + 16, ch->ctrl_start);
 448         if (ch->jumponly)
 449                 cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2) );
 450         else
 451                 cx_write(ch->cmds_start + 20, 64 >> 2);
 452         for (i = 24; i < 80; i += 4)
 453                 cx_write(ch->cmds_start + i, 0);
 454
 455         /* fill registers */
 456         cx_write(ch->ptr1_reg, ch->fifo_start);
 457         cx_write(ch->ptr2_reg, cdt);
 458         cx_write(ch->cnt2_reg, (lines*16) >> 3);
 459         cx_write(ch->cnt1_reg, (bpl >> 3) -1);
 460
 461         dprintk(2,"[bridge %d] sram setup %s: bpl=%d lines=%d\n",
 462                 dev->bridge,
 463                 ch->name,
 464                 bpl,
 465                 lines);
 466
 467         return 0;
 468 }
 469
 470 void cx23885_sram_channel_dump(struct cx23885_dev *dev,
 471                                struct sram_channel *ch)
 472 {
 473         static char *name[] = {
 474                 "init risc lo",
 475                 "init risc hi",
 476                 "cdt base",
 477                 "cdt size",
 478                 "iq base",
 479                 "iq size",
 480                 "risc pc lo",
 481                 "risc pc hi",
 482                 "iq wr ptr",
 483                 "iq rd ptr",
 484                 "cdt current",
 485                 "pci target lo",
 486                 "pci target hi",
 487                 "line / byte",
 488         };
 489         u32 risc;
 490         unsigned int i, j, n;
 491
 492         printk("%s: %s - dma channel status dump\n",
 493                dev->name, ch->name);
 494         for (i = 0; i < ARRAY_SIZE(name); i++)
 495                 printk("%s:   cmds: %-15s: 0x%08x\n",
 496                        dev->name, name[i],
 497                        cx_read(ch->cmds_start + 4*i));
 498
 499         for (i = 0; i < 4; i++) {
 500                 risc = cx_read(ch->cmds_start + 4 * (i + 14));
 501                 printk("%s:   risc%d: ", dev->name, i);
 502                 cx23885_risc_decode(risc);
 503         }
 504         for (i = 0; i < (64 >> 2); i += n) {
 505                 risc = cx_read(ch->ctrl_start + 4 * i);
 506                 /* No consideration for bits 63-32 */
 507
 508                 printk("%s:   (0x%08x) iq %x: ", dev->name,
 509                        ch->ctrl_start + 4 * i, i);
 510                 n = cx23885_risc_decode(risc);
 511                 for (j = 1; j < n; j++) {
 512                         risc = cx_read(ch->ctrl_start + 4 * (i + j));
 513                         printk("%s:   iq %x: 0x%08x [ arg #%d ]\n",
 514                                dev->name, i+j, risc, j);
 515                 }
 516         }
 517
 518         printk("%s: fifo: 0x%08x -> 0x%x\n",
 519                dev->name, ch->fifo_start, ch->fifo_start+ch->fifo_size);
 520         printk("%s: ctrl: 0x%08x -> 0x%x\n",
 521                dev->name, ch->ctrl_start, ch->ctrl_start + 6*16);
 522         printk("%s:   ptr1_reg: 0x%08x\n",
 523                dev->name, cx_read(ch->ptr1_reg));
 524         printk("%s:   ptr2_reg: 0x%08x\n",
 525                dev->name, cx_read(ch->ptr2_reg));
 526         printk("%s:   cnt1_reg: 0x%08x\n",
 527                dev->name, cx_read(ch->cnt1_reg));
 528         printk("%s:   cnt2_reg: 0x%08x\n",
 529                dev->name, cx_read(ch->cnt2_reg));
 530 }
 531
 532 void cx23885_risc_disasm(struct cx23885_tsport *port,
 533                          struct btcx_riscmem *risc)
 534 {
 535         struct cx23885_dev *dev = port->dev;
 536         unsigned int i, j, n;
 537
 538         printk("%s: risc disasm: %p [dma=0x%08lx]\n",
 539                dev->name, risc->cpu, (unsigned long)risc->dma);
 540         for (i = 0; i < (risc->size >> 2); i += n) {
 541                 printk("%s:   %04d: ", dev->name, i);
 542                 n = cx23885_risc_decode(risc->cpu[i]);
 543                 for (j = 1; j < n; j++)
 544                         printk("%s:   %04d: 0x%08x [ arg #%d ]\n",
 545                                dev->name, i + j, risc->cpu[i + j], j);
 546                 if (risc->cpu[i] == RISC_JUMP)
 547                         break;
 548         }
 549 }
 550
 551 void cx23885_shutdown(struct cx23885_dev *dev)
 552 {
 553         /* disable RISC controller */
 554         cx_write(DEV_CNTRL2, 0);
 555
 556         /* Disable all IR activity */
 557         cx_write(IR_CNTRL_REG, 0);
 558
 559         /* Disable Video A/B activity */
 560         cx_write(VID_A_DMA_CTL, 0);
 561         cx_write(VID_B_DMA_CTL, 0);
 562         cx_write(VID_C_DMA_CTL, 0);
 563
 564         /* Disable Audio activity */
 565         cx_write(AUD_INT_DMA_CTL, 0);
 566         cx_write(AUD_EXT_DMA_CTL, 0);
 567
 568         /* Disable Serial port */
 569         cx_write(UART_CTL, 0);
 570
 571         /* Disable Interrupts */
 572         cx_write(PCI_INT_MSK, 0);
 573         cx_write(VID_A_INT_MSK, 0);
 574         cx_write(VID_B_INT_MSK, 0);
 575         cx_write(VID_C_INT_MSK, 0);
 576         cx_write(AUDIO_INT_INT_MSK, 0);
 577         cx_write(AUDIO_EXT_INT_MSK, 0);
 578
 579 }
 580
 581 void cx23885_reset(struct cx23885_dev *dev)
 582 {
 583         dprintk(1, "%s()\n", __FUNCTION__);
 584
 585         cx23885_shutdown(dev);
 586
 587         cx_write(PCI_INT_STAT, 0xffffffff);
 588         cx_write(VID_A_INT_STAT, 0xffffffff);
 589         cx_write(VID_B_INT_STAT, 0xffffffff);
 590         cx_write(VID_C_INT_STAT, 0xffffffff);
 591         cx_write(AUDIO_INT_INT_STAT, 0xffffffff);
 592         cx_write(AUDIO_EXT_INT_STAT, 0xffffffff);
 593         cx_write(CLK_DELAY, cx_read(CLK_DELAY) & 0x80000000);
 594
 595         mdelay(100);
 596
 597         cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH01 ], 188*4, 0);
 598         cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH02 ], 128, 0);
 599         cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH03 ], 128, 0);
 600         cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH04 ], 128, 0);
 601         cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH05 ], 128, 0);
 602         cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH06 ], 188*4, 0);
 603         cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH07 ], 128, 0);
 604         cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH08 ], 128, 0);
 605         cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH09 ], 128, 0);
 606
 607         switch(dev->board) {
 608         case CX23885_BOARD_HAUPPAUGE_HVR1250:
 609                 /* GPIO-0 cx24227 demodulator reset */
 610                 dprintk( 1, "%s() Configuring HVR1250 GPIO's\n", __FUNCTION__);
 611                 cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
 612                 break;
 613         case CX23885_BOARD_HAUPPAUGE_HVR1800:
 614                 /* GPIO-0 656_CLK */
 615                 /* GPIO-1 656_D0 */
 616                 /* GPIO-2 8295A Reset */
 617                 /* GPIO-3-10 cx23417 data0-7 */
 618                 /* GPIO-11-14 cx23417 addr0-3 */
 619                 /* GPIO-15-18 cx23417 READY, CS, RD, WR */
 620                 /* GPIO-19 IR_RX */
 621                 dprintk( 1, "%s() Configuring HVR1800 GPIO's\n", __FUNCTION__);
 622                 // FIXME: Analog requires the tuner is brought out of reset
 623                 break;
 624         }
 625 }
 626
 627
 628 static int cx23885_pci_quirks(struct cx23885_dev *dev)
 629 {
 630         dprintk(1, "%s()\n", __FUNCTION__);
 631
 632         if(dev->bridge == CX23885_BRIDGE_885)
 633                 cx_clear(RDR_TLCTL0, 1 << 4);
 634
 635         return 0;
 636 }
 637
 638 static int get_resources(struct cx23885_dev *dev)
 639 {
 640         if (request_mem_region(pci_resource_start(dev->pci,0),
 641                                pci_resource_len(dev->pci,0),
 642                                dev->name))
 643                 return 0;
 644
 645         printk(KERN_ERR "%s: can't get MMIO memory @ 0x%llx\n",
 646                 dev->name, (unsigned long long)pci_resource_start(dev->pci,0));
 647
 648         return -EBUSY;
 649 }
 650
 651 static void cx23885_timeout(unsigned long data);
 652 int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
 653                          u32 reg, u32 mask, u32 value);
 654
 655 static int cx23885_ir_init(struct cx23885_dev *dev)
 656 {
 657         dprintk(1, "%s()\n", __FUNCTION__);
 658
 659         switch (dev->board) {
 660         case CX23885_BOARD_HAUPPAUGE_HVR1250:
 661         case CX23885_BOARD_HAUPPAUGE_HVR1800:
 662                 dprintk(1, "%s() FIXME - Implement IR support\n", __FUNCTION__);
 663                 break;
 664         }
 665
 666         return 0;
 667 }
 668
 669 static int cx23885_dev_setup(struct cx23885_dev *dev)
 670 {
 671         int i;
 672
 673         mutex_init(&dev->lock);
 674
 675         atomic_inc(&dev->refcount);
 676
 677         dev->nr = cx23885_devcount++;
 678         dev->pci_bus  = dev->pci->bus->number;
 679         dev->pci_slot = PCI_SLOT(dev->pci->devfn);
 680         dev->pci_irqmask = 0x001f00;
 681
 682         /* External Master 1 Bus */
 683         dev->i2c_bus[0].nr = 0;
 684         dev->i2c_bus[0].dev = dev;
 685         dev->i2c_bus[0].reg_stat  = I2C1_STAT;
 686         dev->i2c_bus[0].reg_ctrl  = I2C1_CTRL;
 687         dev->i2c_bus[0].reg_addr  = I2C1_ADDR;
 688         dev->i2c_bus[0].reg_rdata = I2C1_RDATA;
 689         dev->i2c_bus[0].reg_wdata = I2C1_WDATA;
 690         dev->i2c_bus[0].i2c_period = (0x9d << 24); /* 100kHz */
 691
 692         /* External Master 2 Bus */
 693         dev->i2c_bus[1].nr = 1;
 694         dev->i2c_bus[1].dev = dev;
 695         dev->i2c_bus[1].reg_stat  = I2C2_STAT;
 696         dev->i2c_bus[1].reg_ctrl  = I2C2_CTRL;
 697         dev->i2c_bus[1].reg_addr  = I2C2_ADDR;
 698         dev->i2c_bus[1].reg_rdata = I2C2_RDATA;
 699         dev->i2c_bus[1].reg_wdata = I2C2_WDATA;
 700         dev->i2c_bus[1].i2c_period = (0x9d << 24); /* 100kHz */
 701
 702         /* Internal Master 3 Bus */
 703         dev->i2c_bus[2].nr = 2;
 704         dev->i2c_bus[2].dev = dev;
 705         dev->i2c_bus[2].reg_stat  = I2C3_STAT;
 706         dev->i2c_bus[2].reg_ctrl  = I2C3_CTRL;
 707         dev->i2c_bus[2].reg_addr  = I2C3_ADDR;
 708         dev->i2c_bus[2].reg_rdata = I2C3_RDATA;
 709         dev->i2c_bus[2].reg_wdata = I2C3_WDATA;
 710         dev->i2c_bus[2].i2c_period = (0x07 << 24); /* 1.95MHz */
 711
 712         /* Transport bus init dma queue */
 713         spin_lock_init(&dev->ts2.slock);
 714         dev->ts2.dev = dev;
 715         dev->ts2.nr = 2;
 716         dev->ts2.sram_chno = SRAM_CH06;
 717         INIT_LIST_HEAD(&dev->ts2.mpegq.active);
 718         INIT_LIST_HEAD(&dev->ts2.mpegq.queued);
 719         dev->ts2.mpegq.timeout.function = cx23885_timeout;
 720         dev->ts2.mpegq.timeout.data     = (unsigned long)&dev->ts2;
 721         init_timer(&dev->ts2.mpegq.timeout);
 722
 723         dev->ts2.reg_gpcnt = VID_C_GPCNT;
 724         dev->ts2.reg_gpcnt_ctl = VID_C_GPCNT_CTL;
 725         dev->ts2.reg_dma_ctl = VID_C_DMA_CTL;
 726         dev->ts2.reg_lngth = VID_C_LNGTH;
 727         dev->ts2.reg_hw_sop_ctrl = VID_C_HW_SOP_CTL;
 728         dev->ts2.reg_gen_ctrl = VID_C_GEN_CTL;
 729         dev->ts2.reg_bd_pkt_status = VID_C_BD_PKT_STATUS;
 730         dev->ts2.reg_sop_status = VID_C_SOP_STATUS;
 731         dev->ts2.reg_fifo_ovfl_stat = VID_C_FIFO_OVFL_STAT;
 732         dev->ts2.reg_vld_misc = VID_C_VLD_MISC;
 733         dev->ts2.reg_ts_clk_en = VID_C_TS_CLK_EN;
 734         dev->ts2.reg_ts_int_msk = VID_C_INT_MSK;
 735
 736         // FIXME: Make this board specific
 737         dev->ts2.pci_irqmask = 0x04; /* TS Port 2 bit */
 738         dev->ts2.dma_ctl_val = 0x11; /* Enable RISC controller and Fifo */
 739         dev->ts2.ts_int_msk_val = 0x1111; /* TS port bits for RISC */
 740         dev->ts2.gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
 741         dev->ts2.ts_clk_en_val = 0x1; /* Enable TS_CLK */
 742
 743         cx23885_risc_stopper(dev->pci, &dev->ts2.mpegq.stopper,
 744                              dev->ts2.reg_dma_ctl, dev->ts2.dma_ctl_val, 0x00);
 745
 746         sprintf(dev->name, "cx23885[%d]", dev->nr);
 747
 748         if (get_resources(dev) < 0) {
 749                 printk(KERN_ERR "CORE %s No more PCIe resources for "
 750                        "subsystem: %04x:%04x\n",
 751                        dev->name, dev->pci->subsystem_vendor,
 752                        dev->pci->subsystem_device);
 753
 754                 cx23885_devcount--;
 755                 goto fail_free;
 756         }
 757
 758         mutex_lock(&devlist);
 759         list_add_tail(&dev->devlist, &cx23885_devlist);
 760         mutex_unlock(&devlist);
 761
 762         /* PCIe stuff */
 763         dev->lmmio = ioremap(pci_resource_start(dev->pci,0),
 764                              pci_resource_len(dev->pci,0));
 765
 766         dev->bmmio = (u8 __iomem *)dev->lmmio;
 767
 768         /* board config */
 769         dev->board = UNSET;
 770         if (card[dev->nr] < cx23885_bcount)
 771                 dev->board = card[dev->nr];
 772         for (i = 0; UNSET == dev->board  &&  i < cx23885_idcount; i++)
 773                 if (dev->pci->subsystem_vendor == cx23885_subids[i].subvendor &&
 774                     dev->pci->subsystem_device == cx23885_subids[i].subdevice)
 775                         dev->board = cx23885_subids[i].card;
 776         if (UNSET == dev->board) {
 777                 dev->board = CX23885_BOARD_UNKNOWN;
 778                 cx23885_card_list(dev);
 779         }
 780         printk(KERN_INFO "CORE %s: subsystem: %04x:%04x, board: %s [card=%d,%s]\n",
 781                dev->name, dev->pci->subsystem_vendor,
 782                dev->pci->subsystem_device, cx23885_boards[dev->board].name,
 783                dev->board, card[dev->nr] == dev->board ?
 784                "insmod option" : "autodetected");
 785
 786         /* Configure the internal memory */
 787         if(dev->pci->device == 0x8880) {
 788                 dev->bridge = CX23885_BRIDGE_887;
 789                 dev->sram_channels = cx23887_sram_channels;
 790         } else
 791         if(dev->pci->device == 0x8852) {
 792                 dev->bridge = CX23885_BRIDGE_885;
 793                 dev->sram_channels = cx23885_sram_channels;
 794         }
 795         dprintk(1, "%s() Memory configured for PCIe bridge type %d\n",
 796                 __FUNCTION__, dev->bridge);
 797
 798         cx23885_pci_quirks(dev);
 799
 800         /* init hardware */
 801         cx23885_reset(dev);
 802
 803         cx23885_i2c_register(&dev->i2c_bus[0]);
 804         cx23885_i2c_register(&dev->i2c_bus[1]);
 805         cx23885_i2c_register(&dev->i2c_bus[2]);
 806         cx23885_call_i2c_clients (&dev->i2c_bus[0], TUNER_SET_STANDBY, NULL);
 807
 808         cx23885_card_setup(dev);
 809         cx23885_ir_init(dev);
 810
 811         if (cx23885_dvb_register(&dev->ts2) < 0) {
 812                 printk(KERN_ERR "%s() Failed to register dvb adapters\n",
 813                        __FUNCTION__);
 814         }
 815
 816         return 0;
 817
 818 fail_free:
 819         kfree(dev);
 820         return -ENODEV;
 821 }
 822
 823 void cx23885_dev_unregister(struct cx23885_dev *dev)
 824 {
 825         release_mem_region(pci_resource_start(dev->pci,0),
 826                            pci_resource_len(dev->pci,0));
 827
 828         if (!atomic_dec_and_test(&dev->refcount))
 829                 return;
 830
 831         cx23885_dvb_unregister(&dev->ts2);
 832         cx23885_i2c_unregister(&dev->i2c_bus[2]);
 833         cx23885_i2c_unregister(&dev->i2c_bus[1]);
 834         cx23885_i2c_unregister(&dev->i2c_bus[0]);
 835
 836         iounmap(dev->lmmio);
 837 }
 838
 839 static u32* cx23885_risc_field(u32 *rp, struct scatterlist *sglist,
 840                                unsigned int offset, u32 sync_line,
 841                                unsigned int bpl, unsigned int padding,
 842                                unsigned int lines)
 843 {
 844         struct scatterlist *sg;
 845         unsigned int line, todo;
 846
 847         /* sync instruction */
 848         if (sync_line != NO_SYNC_LINE)
 849                 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
 850
 851         /* scan lines */
 852         sg = sglist;
 853         for (line = 0; line < lines; line++) {
 854                 while (offset && offset >= sg_dma_len(sg)) {
 855                         offset -= sg_dma_len(sg);
 856                         sg++;
 857                 }
 858                 if (bpl <= sg_dma_len(sg)-offset) {
 859                         /* fits into current chunk */
 860                         *(rp++)=cpu_to_le32(RISC_WRITE|RISC_SOL|RISC_EOL|bpl);
 861                         *(rp++)=cpu_to_le32(sg_dma_address(sg)+offset);
 862                         *(rp++)=cpu_to_le32(0); /* bits 63-32 */
 863                         offset+=bpl;
 864                 } else {
 865                         /* scanline needs to be split */
 866                         todo = bpl;
 867                         *(rp++)=cpu_to_le32(RISC_WRITE|RISC_SOL|
 868                                             (sg_dma_len(sg)-offset));
 869                         *(rp++)=cpu_to_le32(sg_dma_address(sg)+offset);
 870                         *(rp++)=cpu_to_le32(0); /* bits 63-32 */
 871                         todo -= (sg_dma_len(sg)-offset);
 872                         offset = 0;
 873                         sg++;
 874                         while (todo > sg_dma_len(sg)) {
 875                                 *(rp++)=cpu_to_le32(RISC_WRITE|
 876                                                     sg_dma_len(sg));
 877                                 *(rp++)=cpu_to_le32(sg_dma_address(sg));
 878                                 *(rp++)=cpu_to_le32(0); /* bits 63-32 */
 879                                 todo -= sg_dma_len(sg);
 880                                 sg++;
 881                         }
 882                         *(rp++)=cpu_to_le32(RISC_WRITE|RISC_EOL|todo);
 883                         *(rp++)=cpu_to_le32(sg_dma_address(sg));
 884                         *(rp++)=cpu_to_le32(0); /* bits 63-32 */
 885                         offset += todo;
 886                 }
 887                 offset += padding;
 888         }
 889
 890         return rp;
 891 }
 892
 893 int cx23885_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc,
 894                         struct scatterlist *sglist, unsigned int top_offset,
 895                         unsigned int bottom_offset, unsigned int bpl,
 896                         unsigned int padding, unsigned int lines)
 897 {
 898         u32 instructions, fields;
 899         u32 *rp;
 900         int rc;
 901
 902         fields = 0;
 903         if (UNSET != top_offset)
 904                 fields++;
 905         if (UNSET != bottom_offset)
 906                 fields++;
 907
 908         /* estimate risc mem: worst case is one write per page border +
 909            one write per scan line + syncs + jump (all 2 dwords).  Padding
 910            can cause next bpl to start close to a page border.  First DMA
 911            region may be smaller than PAGE_SIZE */
 912         /* write and jump need and extra dword */
 913         instructions  = fields * (1 + ((bpl + padding) * lines) / PAGE_SIZE + lines);
 914         instructions += 2;
 915         if ((rc = btcx_riscmem_alloc(pci,risc,instructions*12)) < 0)
 916                 return rc;
 917
 918         /* write risc instructions */
 919         rp = risc->cpu;
 920         if (UNSET != top_offset)
 921                 rp = cx23885_risc_field(rp, sglist, top_offset, 0,
 922                                         bpl, padding, lines);
 923         if (UNSET != bottom_offset)
 924                 rp = cx23885_risc_field(rp, sglist, bottom_offset, 0x200,
 925                                         bpl, padding, lines);
 926
 927         /* save pointer to jmp instruction address */
 928         risc->jmp = rp;
 929         BUG_ON((risc->jmp - risc->cpu + 2) * sizeof (*risc->cpu) > risc->size);
 930         return 0;
 931 }
 932
 933 int cx23885_risc_databuffer(struct pci_dev *pci, struct btcx_riscmem *risc,
 934                             struct scatterlist *sglist, unsigned int bpl,
 935                             unsigned int lines)
 936 {
 937         u32 instructions;
 938         u32 *rp;
 939         int rc;
 940
 941         /* estimate risc mem: worst case is one write per page border +
 942            one write per scan line + syncs + jump (all 2 dwords).  Here
 943            there is no padding and no sync.  First DMA region may be smaller
 944            than PAGE_SIZE */
 945         /* Jump and write need an extra dword */
 946         instructions  = 1 + (bpl * lines) / PAGE_SIZE + lines;
 947         instructions += 1;
 948
 949         if ((rc = btcx_riscmem_alloc(pci,risc,instructions*12)) < 0)
 950                 return rc;
 951
 952         /* write risc instructions */
 953         rp = risc->cpu;
 954         rp = cx23885_risc_field(rp, sglist, 0, NO_SYNC_LINE, bpl, 0, lines);
 955
 956         /* save pointer to jmp instruction address */
 957         risc->jmp = rp;
 958         BUG_ON((risc->jmp - risc->cpu + 2) * sizeof (*risc->cpu) > risc->size);
 959         return 0;
 960 }
 961
 962 int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
 963                          u32 reg, u32 mask, u32 value)
 964 {
 965         u32 *rp;
 966         int rc;
 967
 968         if ((rc = btcx_riscmem_alloc(pci, risc, 4*16)) < 0)
 969                 return rc;
 970
 971         /* write risc instructions */
 972         rp = risc->cpu;
 973         *(rp++) = cpu_to_le32(RISC_WRITECR  | RISC_IRQ2);
 974         *(rp++) = cpu_to_le32(reg);
 975         *(rp++) = cpu_to_le32(value);
 976         *(rp++) = cpu_to_le32(mask);
 977         *(rp++) = cpu_to_le32(RISC_JUMP);
 978         *(rp++) = cpu_to_le32(risc->dma);
 979         *(rp++) = cpu_to_le32(0); /* bits 63-32 */
 980         return 0;
 981 }
 982
 983 void cx23885_free_buffer(struct videobuf_queue *q, struct cx23885_buffer *buf)
 984 {
 985         BUG_ON(in_interrupt());
 986         videobuf_waiton(&buf->vb, 0, 0);
 987         videobuf_dma_unmap(q, &buf->vb.dma);
 988         videobuf_dma_free(&buf->vb.dma);
 989         btcx_riscmem_free((struct pci_dev *)q->dev, &buf->risc);
 990         buf->vb.state = STATE_NEEDS_INIT;
 991 }
 992
 993 static int cx23885_start_dma(struct cx23885_tsport *port,
 994                              struct cx23885_dmaqueue *q,
 995                              struct cx23885_buffer   *buf)
 996 {
 997         struct cx23885_dev *dev = port->dev;
 998
 999         dprintk(1, "%s() w: %d, h: %d, f: %d\n", __FUNCTION__,
1000                 buf->vb.width, buf->vb.height, buf->vb.field);
1001
1002         /* setup fifo + format */
1003         cx23885_sram_channel_setup(dev,
1004                                    &dev->sram_channels[ port->sram_chno ],
1005                                    port->ts_packet_size, buf->risc.dma);
1006         if(debug > 5) {
1007                 cx23885_sram_channel_dump(dev, &dev->sram_channels[ port->sram_chno ] );
1008                 cx23885_risc_disasm(port, &buf->risc);
1009         }
1010
1011         /* write TS length to chip */
1012         cx_write(port->reg_lngth, buf->vb.width);
1013
1014         if (!(cx23885_boards[dev->board].portc & CX23885_MPEG_DVB)) {
1015                 printk( "%s() Failed. Unsupported value in .portc (0x%08x)\n",
1016                         __FUNCTION__, cx23885_boards[dev->board].portc );
1017                 return -EINVAL;
1018         }
1019
1020         udelay(100);
1021
1022         cx_write(port->reg_hw_sop_ctrl, 0x47 << 16 | 188 << 4);
1023         cx_write(port->reg_ts_clk_en, port->ts_clk_en_val);
1024
1025         switch (dev->board) {
1026         case CX23885_BOARD_HAUPPAUGE_HVR1250:
1027         case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
1028         case CX23885_BOARD_HAUPPAUGE_HVR1800:
1029                 cx_write(port->reg_vld_misc, 0x00);
1030                 dprintk(1, "%s() Configuring HVR1800/lp/1500 board\n",
1031                         __FUNCTION__);
1032                 break;
1033         default:
1034                 printk(KERN_ERR "%s() error, default case", __FUNCTION__ );
1035         }
1036
1037         cx_write(port->reg_gen_ctrl, port->gen_ctrl_val);
1038         udelay(100);
1039
1040         /* reset counter to zero */
1041         cx_write(port->reg_gpcnt_ctl, 3);
1042         q->count = 1;
1043
1044         switch(dev->bridge) {
1045         case CX23885_BRIDGE_885:
1046         case CX23885_BRIDGE_887:
1047                 /* enable irqs */
1048                 dprintk(1, "%s() enabling TS int's and DMA\n", __FUNCTION__ );
1049                 cx_set(port->reg_ts_int_msk,  port->ts_int_msk_val);
1050                 cx_set(port->reg_dma_ctl, port->dma_ctl_val);
1051                 cx_set(PCI_INT_MSK, dev->pci_irqmask | port->pci_irqmask);
1052                 break;
1053         default:
1054                 printk(KERN_ERR "%s() error, default case", __FUNCTION__ );
1055         }
1056
1057         cx_set(DEV_CNTRL2, (1<<5)); /* Enable RISC controller */
1058
1059         return 0;
1060 }
1061
1062 static int cx23885_stop_dma(struct cx23885_tsport *port)
1063 {
1064         struct cx23885_dev *dev = port->dev;
1065         dprintk(1, "%s()\n", __FUNCTION__);
1066
1067         /* Stop interrupts and DMA */
1068         cx_clear(port->reg_ts_int_msk, port->ts_int_msk_val);
1069         cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1070
1071         return 0;
1072 }
1073
1074 static int cx23885_restart_queue(struct cx23885_tsport *port,
1075                                 struct cx23885_dmaqueue *q)
1076 {
1077         struct cx23885_dev *dev = port->dev;
1078         struct cx23885_buffer *buf;
1079         struct list_head *item;
1080
1081         dprintk(5, "%s()\n", __FUNCTION__);
1082         if (list_empty(&q->active))
1083         {
1084                 struct cx23885_buffer *prev;
1085                 prev = NULL;
1086
1087                 dprintk(5, "%s() queue is empty\n", __FUNCTION__);
1088
1089                 for (;;) {
1090                         if (list_empty(&q->queued))
1091                                 return 0;
1092                         buf = list_entry(q->queued.next, struct cx23885_buffer,
1093                                          vb.queue);
1094                         if (NULL == prev) {
1095                                 list_del(&buf->vb.queue);
1096                                 list_add_tail(&buf->vb.queue, &q->active);
1097                                 cx23885_start_dma(port, q, buf);
1098                                 buf->vb.state = STATE_ACTIVE;
1099                                 buf->count    = q->count++;
1100                                 mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT);
1101                                 dprintk(5, "[%p/%d] restart_queue - first active\n",
1102                                         buf, buf->vb.i);
1103
1104                         } else if (prev->vb.width  == buf->vb.width  &&
1105                                    prev->vb.height == buf->vb.height &&
1106                                    prev->fmt       == buf->fmt) {
1107                                 list_del(&buf->vb.queue);
1108                                 list_add_tail(&buf->vb.queue, &q->active);
1109                                 buf->vb.state = STATE_ACTIVE;
1110                                 buf->count    = q->count++;
1111                                 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
1112                                 prev->risc.jmp[2] = cpu_to_le32(0); /* 64 bit bits 63-32 */
1113                                 dprintk(5,"[%p/%d] restart_queue - move to active\n",
1114                                         buf, buf->vb.i);
1115                         } else {
1116                                 return 0;
1117                         }
1118                         prev = buf;
1119                 }
1120                 return 0;
1121         }
1122
1123         buf = list_entry(q->active.next, struct cx23885_buffer, vb.queue);
1124         dprintk(2, "restart_queue [%p/%d]: restart dma\n",
1125                 buf, buf->vb.i);
1126         cx23885_start_dma(port, q, buf);
1127         list_for_each(item, &q->active) {
1128                 buf = list_entry(item, struct cx23885_buffer, vb.queue);
1129                 buf->count = q->count++;
1130         }
1131         mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
1132         return 0;
1133 }
1134
1135 /* ------------------------------------------------------------------ */
1136
1137 int cx23885_buf_prepare(struct videobuf_queue *q, struct cx23885_tsport *port,
1138                         struct cx23885_buffer *buf, enum v4l2_field field)
1139 {
1140         struct cx23885_dev *dev = port->dev;
1141         int size = port->ts_packet_size * port->ts_packet_count;
1142         int rc;
1143
1144         dprintk(1, "%s: %p\n", __FUNCTION__, buf);
1145         if (0 != buf->vb.baddr  &&  buf->vb.bsize < size)
1146                 return -EINVAL;
1147
1148         if (STATE_NEEDS_INIT == buf->vb.state) {
1149                 buf->vb.width  = port->ts_packet_size;
1150                 buf->vb.height = port->ts_packet_count;
1151                 buf->vb.size   = size;
1152                 buf->vb.field  = field /*V4L2_FIELD_TOP*/;
1153
1154                 if (0 != (rc = videobuf_iolock(q, &buf->vb, NULL)))
1155                         goto fail;
1156                 cx23885_risc_databuffer(dev->pci, &buf->risc,
1157                                      buf->vb.dma.sglist,
1158                                      buf->vb.width, buf->vb.height);
1159         }
1160         buf->vb.state = STATE_PREPARED;
1161         return 0;
1162
1163  fail:
1164         cx23885_free_buffer(q, buf);
1165         return rc;
1166 }
1167
1168 void cx23885_buf_queue(struct cx23885_tsport *port, struct cx23885_buffer *buf)
1169 {
1170         struct cx23885_buffer    *prev;
1171         struct cx23885_dev *dev = port->dev;
1172         struct cx23885_dmaqueue  *cx88q = &port->mpegq;
1173
1174         /* add jump to stopper */
1175         buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
1176         buf->risc.jmp[1] = cpu_to_le32(cx88q->stopper.dma);
1177         buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */
1178
1179         if (list_empty(&cx88q->active)) {
1180                 dprintk( 1, "queue is empty - first active\n" );
1181                 list_add_tail(&buf->vb.queue, &cx88q->active);
1182                 cx23885_start_dma(port, cx88q, buf);
1183                 buf->vb.state = STATE_ACTIVE;
1184                 buf->count    = cx88q->count++;
1185                 mod_timer(&cx88q->timeout, jiffies + BUFFER_TIMEOUT);
1186                 dprintk(1, "[%p/%d] %s - first active\n",
1187                         buf, buf->vb.i, __FUNCTION__);
1188         } else {
1189                 dprintk( 1, "queue is not empty - append to active\n" );
1190                 prev = list_entry(cx88q->active.prev, struct cx23885_buffer,
1191                                   vb.queue);
1192                 list_add_tail(&buf->vb.queue, &cx88q->active);
1193                 buf->vb.state = STATE_ACTIVE;
1194                 buf->count    = cx88q->count++;
1195                 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
1196                 prev->risc.jmp[2] = cpu_to_le32(0); /* 64 bit bits 63-32 */
1197                 dprintk( 1, "[%p/%d] %s - append to active\n",
1198                          buf, buf->vb.i, __FUNCTION__);
1199         }
1200 }
1201
1202 /* ----------------------------------------------------------- */
1203
1204 static void do_cancel_buffers(struct cx23885_tsport *port, char *reason,
1205                               int restart)
1206 {
1207         struct cx23885_dev *dev = port->dev;
1208         struct cx23885_dmaqueue *q = &port->mpegq;
1209         struct cx23885_buffer *buf;
1210         unsigned long flags;
1211
1212         spin_lock_irqsave(&port->slock, flags);
1213         while (!list_empty(&q->active)) {
1214                 buf = list_entry(q->active.next, struct cx23885_buffer,
1215                                  vb.queue);
1216                 list_del(&buf->vb.queue);
1217                 buf->vb.state = STATE_ERROR;
1218                 wake_up(&buf->vb.done);
1219                 dprintk(1, "[%p/%d] %s - dma=0x%08lx\n",
1220                         buf, buf->vb.i, reason, (unsigned long)buf->risc.dma);
1221         }
1222         if (restart) {
1223                 dprintk(1, "restarting queue\n" );
1224                 cx23885_restart_queue(port, q);
1225         }
1226         spin_unlock_irqrestore(&port->slock, flags);
1227 }
1228
1229 void cx23885_cancel_buffers(struct cx23885_tsport *port)
1230 {
1231         struct cx23885_dev *dev = port->dev;
1232         struct cx23885_dmaqueue *q = &port->mpegq;
1233
1234         dprintk(1, "%s()\n", __FUNCTION__);
1235         del_timer_sync(&q->timeout);
1236         cx23885_stop_dma(port);
1237         do_cancel_buffers(port, "cancel", 0);
1238 }
1239
1240 static void cx23885_timeout(unsigned long data)
1241 {
1242         struct cx23885_tsport *port = (struct cx23885_tsport *)data;
1243         struct cx23885_dev *dev = port->dev;
1244
1245         dprintk(1, "%s()\n",__FUNCTION__);
1246
1247         if (debug > 5)
1248                 cx23885_sram_channel_dump(dev, &dev->sram_channels[ port->sram_chno ]);
1249
1250         cx23885_stop_dma(port);
1251         do_cancel_buffers(port, "timeout", 1);
1252 }
1253
1254 #define PCI_MSK_APB_DMA   (1 << 12)
1255 #define PCI_MSK_AL_WR     (1 << 11)
1256 #define PCI_MSK_AL_RD     (1 << 10)
1257 #define PCI_MSK_RISC_WR   (1 <<  9)
1258 #define PCI_MSK_RISC_RD   (1 <<  8)
1259
1260 #define PCI_MSK_AUD_EXT   (1 <<  4)
1261 #define PCI_MSK_AUD_INT   (1 <<  3)
1262 #define PCI_MSK_VID_C     (1 <<  2)
1263 #define PCI_MSK_VID_B     (1 <<  1)
1264 #define PCI_MSK_VID_A      1
1265
1266 #define VID_C_MSK_BAD_PKT (1 << 20)
1267 #define VID_C_MSK_OPC_ERR (1 << 16)
1268 #define VID_C_MSK_SYNC    (1 << 12)
1269 #define VID_C_MSK_OF      (1 <<  8)
1270 #define VID_C_MSK_RISCI2  (1 <<  4)
1271 #define VID_C_MSK_RISCI1   1
1272
1273 static irqreturn_t cx23885_irq(int irq, void *dev_id)
1274 {
1275         struct cx23885_dev *dev = dev_id;
1276         struct cx23885_tsport *port = &dev->ts2;
1277         u32 pci_status, pci_mask;
1278         u32 ts2_status, ts2_mask;
1279         int count = 0, handled = 0;
1280
1281         pci_status = cx_read(PCI_INT_STAT);
1282         pci_mask = cx_read(PCI_INT_MSK);
1283
1284         ts2_status = cx_read(VID_C_INT_STAT);
1285         ts2_mask = cx_read(VID_C_INT_MSK);
1286
1287         if ( (pci_status == 0) && (ts2_status == 0) )
1288                 goto out;
1289
1290         count = cx_read(port->reg_gpcnt);
1291         dprintk(7, "pci_status: 0x%08x  pci_mask: 0x%08x\n", pci_status, pci_mask );
1292         dprintk(7, "ts2_status: 0x%08x  ts2_mask: 0x%08x count: 0x%x\n", ts2_status, ts2_mask, count );
1293
1294         if ( (pci_status & PCI_MSK_RISC_RD) ||
1295              (pci_status & PCI_MSK_RISC_WR) ||
1296              (pci_status & PCI_MSK_AL_RD) ||
1297              (pci_status & PCI_MSK_AL_WR) ||
1298              (pci_status & PCI_MSK_APB_DMA) ||
1299              (pci_status & PCI_MSK_VID_C) ||
1300              (pci_status & PCI_MSK_VID_B) ||
1301              (pci_status & PCI_MSK_VID_A) ||
1302              (pci_status & PCI_MSK_AUD_INT) ||
1303              (pci_status & PCI_MSK_AUD_EXT) )
1304         {
1305
1306                 if (pci_status & PCI_MSK_RISC_RD)
1307                         dprintk(7, " (PCI_MSK_RISC_RD   0x%08x)\n", PCI_MSK_RISC_RD);
1308                 if (pci_status & PCI_MSK_RISC_WR)
1309                         dprintk(7, " (PCI_MSK_RISC_WR   0x%08x)\n", PCI_MSK_RISC_WR);
1310                 if (pci_status & PCI_MSK_AL_RD)
1311                         dprintk(7, " (PCI_MSK_AL_RD     0x%08x)\n", PCI_MSK_AL_RD);
1312                 if (pci_status & PCI_MSK_AL_WR)
1313                         dprintk(7, " (PCI_MSK_AL_WR     0x%08x)\n", PCI_MSK_AL_WR);
1314                 if (pci_status & PCI_MSK_APB_DMA)
1315                         dprintk(7, " (PCI_MSK_APB_DMA   0x%08x)\n", PCI_MSK_APB_DMA);
1316                 if (pci_status & PCI_MSK_VID_C)
1317                         dprintk(7, " (PCI_MSK_VID_C     0x%08x)\n", PCI_MSK_VID_C);
1318                 if (pci_status & PCI_MSK_VID_B)
1319                         dprintk(7, " (PCI_MSK_VID_B     0x%08x)\n", PCI_MSK_VID_B);
1320                 if (pci_status & PCI_MSK_VID_A)
1321                         dprintk(7, " (PCI_MSK_VID_A     0x%08x)\n", PCI_MSK_VID_A);
1322                 if (pci_status & PCI_MSK_AUD_INT)
1323                         dprintk(7, " (PCI_MSK_AUD_INT   0x%08x)\n", PCI_MSK_AUD_INT);
1324                 if (pci_status & PCI_MSK_AUD_EXT)
1325                         dprintk(7, " (PCI_MSK_AUD_EXT   0x%08x)\n", PCI_MSK_AUD_EXT);
1326
1327         }
1328
1329         if ( (ts2_status & VID_C_MSK_OPC_ERR) ||
1330              (ts2_status & VID_C_MSK_BAD_PKT) ||
1331              (ts2_status & VID_C_MSK_SYNC) ||
1332              (ts2_status & VID_C_MSK_OF))
1333         {
1334                 if (ts2_status & VID_C_MSK_OPC_ERR)
1335                         dprintk(7, " (VID_C_MSK_OPC_ERR 0x%08x)\n", VID_C_MSK_OPC_ERR);
1336                 if (ts2_status & VID_C_MSK_BAD_PKT)
1337                         dprintk(7, " (VID_C_MSK_BAD_PKT 0x%08x)\n", VID_C_MSK_BAD_PKT);
1338                 if (ts2_status & VID_C_MSK_SYNC)
1339                         dprintk(7, " (VID_C_MSK_SYNC    0x%08x)\n", VID_C_MSK_SYNC);
1340                 if (ts2_status & VID_C_MSK_OF)
1341                         dprintk(7, " (VID_C_MSK_OF      0x%08x)\n", VID_C_MSK_OF);
1342
1343                 printk(KERN_ERR "%s: mpeg risc op code error\n", dev->name);
1344
1345                 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1346                 cx23885_sram_channel_dump(dev, &dev->sram_channels[ port->sram_chno ]);
1347
1348         } else if (ts2_status & VID_C_MSK_RISCI1) {
1349
1350                 dprintk(7, " (RISCI1            0x%08x)\n", VID_C_MSK_RISCI1);
1351
1352                 spin_lock(&port->slock);
1353                 count = cx_read(port->reg_gpcnt);
1354                 cx23885_wakeup(port, &port->mpegq, count);
1355                 spin_unlock(&port->slock);
1356
1357         } else if (ts2_status & VID_C_MSK_RISCI2) {
1358
1359                 dprintk(7, " (RISCI2            0x%08x)\n", VID_C_MSK_RISCI2);
1360
1361                 spin_lock(&port->slock);
1362                 cx23885_restart_queue(port, &port->mpegq);
1363                 spin_unlock(&port->slock);
1364
1365         }
1366
1367         cx_write(VID_C_INT_STAT, ts2_status);
1368         cx_write(PCI_INT_STAT, pci_status);
1369         handled = 1;
1370 out:
1371         return IRQ_RETVAL(handled);
1372 }
1373
1374 static int __devinit cx23885_initdev(struct pci_dev *pci_dev,
1375                                      const struct pci_device_id *pci_id)
1376 {
1377         struct cx23885_dev *dev;
1378         int err;
1379
1380         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1381         if (NULL == dev)
1382                 return -ENOMEM;
1383
1384         /* pci init */
1385         dev->pci = pci_dev;
1386         if (pci_enable_device(pci_dev)) {
1387                 err = -EIO;
1388                 goto fail_free;
1389         }
1390
1391         if (cx23885_dev_setup(dev) < 0) {
1392                 err = -EINVAL;
1393                 goto fail_free;
1394         }
1395
1396         /* print pci info */
1397         pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev);
1398         pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER,  &dev->pci_lat);
1399         printk(KERN_INFO "%s/0: found at %s, rev: %d, irq: %d, "
1400                "latency: %d, mmio: 0x%llx\n", dev->name,
1401                pci_name(pci_dev), dev->pci_rev, pci_dev->irq,
1402                dev->pci_lat, (unsigned long long)pci_resource_start(pci_dev,0));
1403
1404         pci_set_master(pci_dev);
1405         if (!pci_dma_supported(pci_dev, 0xffffffff)) {
1406                 printk("%s/0: Oops: no 32bit PCI DMA ???\n", dev->name);
1407                 err = -EIO;
1408                 goto fail_irq;
1409         }
1410
1411         err = request_irq(pci_dev->irq, cx23885_irq,
1412                           IRQF_SHARED | IRQF_DISABLED, dev->name, dev);
1413         if (err < 0) {
1414                 printk(KERN_ERR "%s: can't get IRQ %d\n",
1415                        dev->name, pci_dev->irq);
1416                 goto fail_irq;
1417         }
1418
1419         pci_set_drvdata(pci_dev, dev);
1420         return 0;
1421
1422 fail_irq:
1423         cx23885_dev_unregister(dev);
1424 fail_free:
1425         kfree(dev);
1426         return err;
1427 }
1428
1429 static void __devexit cx23885_finidev(struct pci_dev *pci_dev)
1430 {
1431         struct cx23885_dev *dev = pci_get_drvdata(pci_dev);
1432
1433         cx23885_shutdown(dev);
1434
1435         pci_disable_device(pci_dev);
1436
1437         /* unregister stuff */
1438         free_irq(pci_dev->irq, dev);
1439         pci_set_drvdata(pci_dev, NULL);
1440
1441         mutex_lock(&devlist);
1442         list_del(&dev->devlist);
1443         mutex_unlock(&devlist);
1444
1445         cx23885_dev_unregister(dev);
1446         kfree(dev);
1447 }
1448
1449 static struct pci_device_id cx23885_pci_tbl[] = {
1450         {
1451                 /* CX23885 */
1452                 .vendor       = 0x14f1,
1453                 .device       = 0x8852,
1454                 .subvendor    = PCI_ANY_ID,
1455                 .subdevice    = PCI_ANY_ID,
1456         },{
1457                 /* CX23887 Rev 2 */
1458                 .vendor       = 0x14f1,
1459                 .device       = 0x8880,
1460                 .subvendor    = PCI_ANY_ID,
1461                 .subdevice    = PCI_ANY_ID,
1462         },{
1463                 /* --- end of list --- */
1464         }
1465 };
1466 MODULE_DEVICE_TABLE(pci, cx23885_pci_tbl);
1467
1468 static struct pci_driver cx23885_pci_driver = {
1469         .name     = "cx23885",
1470         .id_table = cx23885_pci_tbl,
1471         .probe    = cx23885_initdev,
1472         .remove   = __devexit_p(cx23885_finidev),
1473         /* TODO */
1474         .suspend  = NULL,
1475         .resume   = NULL,
1476 };
1477
1478 static int cx23885_init(void)
1479 {
1480         printk(KERN_INFO "cx23885 driver version %d.%d.%d loaded\n",
1481                (CX23885_VERSION_CODE >> 16) & 0xff,
1482                (CX23885_VERSION_CODE >>  8) & 0xff,
1483                CX23885_VERSION_CODE & 0xff);
1484 #ifdef SNAPSHOT
1485         printk(KERN_INFO "cx23885: snapshot date %04d-%02d-%02d\n",
1486                SNAPSHOT/10000, (SNAPSHOT/100)%100, SNAPSHOT%100);
1487 #endif
1488         return pci_register_driver(&cx23885_pci_driver);
1489 }
1490
1491 static void cx23885_fini(void)
1492 {
1493         pci_unregister_driver(&cx23885_pci_driver);
1494 }
1495
1496 module_init(cx23885_init);
1497 module_exit(cx23885_fini);
1498
1499 /* ----------------------------------------------------------- */
1500 /*
1501  * Local variables:
1502  * c-basic-offset: 8
1503  * End:
1504  * kate: eol "unix"; indent-width 3; remove-trailing-space on; replace-trailing-space-save on; tab-width 8; replace-tabs off; space-indent off; mixed-indent off
1505  */