drivers/mtd/nand/cafe.c

   1 /*
   2  * Driver for One Laptop Per Child ‘CAFÉ’ controller, aka Marvell 88ALP01
   3  *
   4  * Copyright © 2006 Red Hat, Inc.
   5  * Copyright © 2006 David Woodhouse <dwmw2@infradead.org>
   6  */
   7
   8 #define DEBUG
   9
  10 #include <linux/device.h>
  11 #undef DEBUG
  12 #include <linux/mtd/mtd.h>
  13 #include <linux/mtd/nand.h>
  14 #include <linux/pci.h>
  15 #include <linux/delay.h>
  16 #include <linux/interrupt.h>
  17 #include <asm/io.h>
  18
  19 #define CAFE_NAND_CTRL1         0x00
  20 #define CAFE_NAND_CTRL2         0x04
  21 #define CAFE_NAND_CTRL3         0x08
  22 #define CAFE_NAND_STATUS        0x0c
  23 #define CAFE_NAND_IRQ           0x10
  24 #define CAFE_NAND_IRQ_MASK      0x14
  25 #define CAFE_NAND_DATA_LEN      0x18
  26 #define CAFE_NAND_ADDR1         0x1c
  27 #define CAFE_NAND_ADDR2         0x20
  28 #define CAFE_NAND_TIMING1       0x24
  29 #define CAFE_NAND_TIMING2       0x28
  30 #define CAFE_NAND_TIMING3       0x2c
  31 #define CAFE_NAND_NONMEM        0x30
  32 #define CAFE_NAND_ECC_RESULT    0x3C
  33 #define CAFE_NAND_DMA_CTRL      0x40
  34 #define CAFE_NAND_DMA_ADDR0     0x44
  35 #define CAFE_NAND_DMA_ADDR1     0x48
  36 #define CAFE_NAND_ECC_SYN01     0x50
  37 #define CAFE_NAND_ECC_SYN23     0x54
  38 #define CAFE_NAND_ECC_SYN45     0x58
  39 #define CAFE_NAND_ECC_SYN67     0x5c
  40 #define CAFE_NAND_READ_DATA     0x1000
  41 #define CAFE_NAND_WRITE_DATA    0x2000
  42
  43 int cafe_correct_ecc(unsigned char *buf,
  44                      unsigned short *chk_syndrome_list);
  45
  46 struct cafe_priv {
  47         struct nand_chip nand;
  48         struct pci_dev *pdev;
  49         void __iomem *mmio;
  50         uint32_t ctl1;
  51         uint32_t ctl2;
  52         int datalen;
  53         int nr_data;
  54         int data_pos;
  55         int page_addr;
  56         dma_addr_t dmaaddr;
  57         unsigned char *dmabuf;
  58
  59 };
  60
  61 static int usedma = 1;
  62 module_param(usedma, int, 0644);
  63
  64 static int skipbbt = 0;
  65 module_param(skipbbt, int, 0644);
  66
  67 static int debug = 0;
  68 module_param(debug, int, 0644);
  69
  70 static int checkecc = 1;
  71 module_param(checkecc, int, 0644);
  72
  73 static int slowtiming = 0;
  74 module_param(slowtiming, int, 0644);
  75
  76 /* Hrm. Why isn't this already conditional on something in the struct device? */
  77 #define cafe_dev_dbg(dev, args...) do { if (debug) dev_dbg(dev, ##args); } while(0)
  78
  79
  80 static int cafe_device_ready(struct mtd_info *mtd)
  81 {
  82         struct cafe_priv *cafe = mtd->priv;
  83         int result = !!(readl(cafe->mmio + CAFE_NAND_STATUS) | 0x40000000);
  84         uint32_t irqs = readl(cafe->mmio + CAFE_NAND_IRQ);
  85
  86         writel(irqs, cafe->mmio+CAFE_NAND_IRQ);
  87
  88         cafe_dev_dbg(&cafe->pdev->dev, "NAND device is%s ready, IRQ %x (%x) (%x,%x)\n",
  89                 result?"":" not", irqs, readl(cafe->mmio + CAFE_NAND_IRQ),
  90                 readl(cafe->mmio + 0x3008), readl(cafe->mmio + 0x300c));
  91
  92         return result;
  93 }
  94
  95
  96 static void cafe_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
  97 {
  98         struct cafe_priv *cafe = mtd->priv;
  99
 100         if (usedma)
 101                 memcpy(cafe->dmabuf + cafe->datalen, buf, len);
 102         else
 103                 memcpy_toio(cafe->mmio + CAFE_NAND_WRITE_DATA + cafe->datalen, buf, len);
 104
 105         cafe->datalen += len;
 106
 107         cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes to write buffer. datalen 0x%x\n",
 108                 len, cafe->datalen);
 109 }
 110
 111 static void cafe_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 112 {
 113         struct cafe_priv *cafe = mtd->priv;
 114
 115         if (usedma)
 116                 memcpy(buf, cafe->dmabuf + cafe->datalen, len);
 117         else
 118                 memcpy_fromio(buf, cafe->mmio + CAFE_NAND_READ_DATA + cafe->datalen, len);
 119
 120         cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes from position 0x%x in read buffer.\n",
 121                   len, cafe->datalen);
 122         cafe->datalen += len;
 123 }
 124
 125 static uint8_t cafe_read_byte(struct mtd_info *mtd)
 126 {
 127         struct cafe_priv *cafe = mtd->priv;
 128         uint8_t d;
 129
 130         cafe_read_buf(mtd, &d, 1);
 131         cafe_dev_dbg(&cafe->pdev->dev, "Read %02x\n", d);
 132
 133         return d;
 134 }
 135
 136 static void cafe_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
 137                               int column, int page_addr)
 138 {
 139         struct cafe_priv *cafe = mtd->priv;
 140         int adrbytes = 0;
 141         uint32_t ctl1;
 142         uint32_t doneint = 0x80000000;
 143
 144         cafe_dev_dbg(&cafe->pdev->dev, "cmdfunc %02x, 0x%x, 0x%x\n",
 145                 command, column, page_addr);
 146
 147         if (command == NAND_CMD_ERASE2 || command == NAND_CMD_PAGEPROG) {
 148                 /* Second half of a command we already calculated */
 149                 writel(cafe->ctl2 | 0x100 | command, cafe->mmio + CAFE_NAND_CTRL2);
 150                 ctl1 = cafe->ctl1;
 151                 cafe_dev_dbg(&cafe->pdev->dev, "Continue command, ctl1 %08x, #data %d\n",
 152                           cafe->ctl1, cafe->nr_data);
 153                 goto do_command;
 154         }
 155         /* Reset ECC engine */
 156         writel(0, cafe->mmio + CAFE_NAND_CTRL2);
 157
 158         /* Emulate NAND_CMD_READOOB on large-page chips */
 159         if (mtd->writesize > 512 &&
 160             command == NAND_CMD_READOOB) {
 161                 column += mtd->writesize;
 162                 command = NAND_CMD_READ0;
 163         }
 164
 165         /* FIXME: Do we need to send read command before sending data
 166            for small-page chips, to position the buffer correctly? */
 167
 168         if (column != -1) {
 169                 writel(column, cafe->mmio + CAFE_NAND_ADDR1);
 170                 adrbytes = 2;
 171                 if (page_addr != -1)
 172                         goto write_adr2;
 173         } else if (page_addr != -1) {
 174                 writel(page_addr & 0xffff, cafe->mmio + CAFE_NAND_ADDR1);
 175                 page_addr >>= 16;
 176         write_adr2:
 177                 writel(page_addr, cafe->mmio+0x20);
 178                 adrbytes += 2;
 179                 if (mtd->size > mtd->writesize << 16)
 180                         adrbytes++;
 181         }
 182
 183         cafe->data_pos = cafe->datalen = 0;
 184
 185         /* Set command valid bit */
 186         ctl1 = 0x80000000 | command;
 187
 188         /* Set RD or WR bits as appropriate */
 189         if (command == NAND_CMD_READID || command == NAND_CMD_STATUS) {
 190                 ctl1 |= (1<<26); /* rd */
 191                 /* Always 5 bytes, for now */
 192                 cafe->datalen = 4;
 193                 /* And one address cycle -- even for STATUS, since the controller doesn't work without */
 194                 adrbytes = 1;
 195         } else if (command == NAND_CMD_READ0 || command == NAND_CMD_READ1 ||
 196                    command == NAND_CMD_READOOB || command == NAND_CMD_RNDOUT) {
 197                 ctl1 |= 1<<26; /* rd */
 198                 /* For now, assume just read to end of page */
 199                 cafe->datalen = mtd->writesize + mtd->oobsize - column;
 200         } else if (command == NAND_CMD_SEQIN)
 201                 ctl1 |= 1<<25; /* wr */
 202
 203         /* Set number of address bytes */
 204         if (adrbytes)
 205                 ctl1 |= ((adrbytes-1)|8) << 27;
 206
 207         if (command == NAND_CMD_SEQIN || command == NAND_CMD_ERASE1) {
 208                 /* Ignore the first command of a pair; the hardware
 209                    deals with them both at once, later */
 210                 cafe->ctl1 = ctl1;
 211                 cafe->ctl2 = 0;
 212                 cafe_dev_dbg(&cafe->pdev->dev, "Setup for delayed command, ctl1 %08x, dlen %x\n",
 213                           cafe->ctl1, cafe->datalen);
 214                 return;
 215         }
 216         /* RNDOUT and READ0 commands need a following byte */
 217         if (command == NAND_CMD_RNDOUT)
 218                 writel(cafe->ctl2 | 0x100 | NAND_CMD_RNDOUTSTART, cafe->mmio + CAFE_NAND_CTRL2);
 219         else if (command == NAND_CMD_READ0 && mtd->writesize > 512)
 220                 writel(cafe->ctl2 | 0x100 | NAND_CMD_READSTART, cafe->mmio + CAFE_NAND_CTRL2);
 221
 222  do_command:
 223 #if 0
 224         /* http://dev.laptop.org/ticket/200
 225            ECC on read only works if we read precisely 0x80e bytes */
 226         if (cafe->datalen == 2112)
 227                 cafe->datalen = 2062;
 228 #endif
 229         cafe_dev_dbg(&cafe->pdev->dev, "dlen %x, ctl1 %x, ctl2 %x\n",
 230                 cafe->datalen, ctl1, readl(cafe->mmio+CAFE_NAND_CTRL2));
 231
 232         /* NB: The datasheet lies -- we really should be subtracting 1 here */
 233         writel(cafe->datalen, cafe->mmio + CAFE_NAND_DATA_LEN);
 234         writel(0x90000000, cafe->mmio + CAFE_NAND_IRQ);
 235         if (usedma && (ctl1 & (3<<25))) {
 236                 uint32_t dmactl = 0xc0000000 + cafe->datalen;
 237                 /* If WR or RD bits set, set up DMA */
 238                 if (ctl1 & (1<<26)) {
 239                         /* It's a read */
 240                         dmactl |= (1<<29);
 241                         /* ... so it's done when the DMA is done, not just
 242                            the command. */
 243                         doneint = 0x10000000;
 244                 }
 245                 writel(dmactl, cafe->mmio + CAFE_NAND_DMA_CTRL);
 246         }
 247         cafe->datalen = 0;
 248
 249 #if 0
 250         { int i;
 251         printk("About to write command %08x\n", ctl1);
 252         for (i=0; i< 0x5c; i+=4)
 253                 printk("Register %x: %08x\n", i, readl(cafe->mmio + i));
 254         }
 255 #endif
 256         writel(ctl1, cafe->mmio + CAFE_NAND_CTRL1);
 257         /* Apply this short delay always to ensure that we do wait tWB in
 258          * any case on any machine. */
 259         ndelay(100);
 260
 261         if (1) {
 262                 int c = 500000;
 263                 uint32_t irqs;
 264
 265                 while (c--) {
 266                         irqs = readl(cafe->mmio + CAFE_NAND_IRQ);
 267                         if (irqs & doneint)
 268                                 break;
 269                         udelay(1);
 270                         if (!(c % 100000))
 271                                 cafe_dev_dbg(&cafe->pdev->dev, "Wait for ready, IRQ %x\n", irqs);
 272                         cpu_relax();
 273                 }
 274                 writel(doneint, cafe->mmio + CAFE_NAND_IRQ);
 275                 cafe_dev_dbg(&cafe->pdev->dev, "Command %x completed after %d usec, irqs %x (%x)\n", command, 50000-c, irqs, readl(cafe->mmio + CAFE_NAND_IRQ));
 276         }
 277
 278
 279         cafe->ctl2 &= ~(1<<8);
 280         cafe->ctl2 &= ~(1<<30);
 281
 282         switch (command) {
 283
 284         case NAND_CMD_CACHEDPROG:
 285         case NAND_CMD_PAGEPROG:
 286         case NAND_CMD_ERASE1:
 287         case NAND_CMD_ERASE2:
 288         case NAND_CMD_SEQIN:
 289         case NAND_CMD_RNDIN:
 290         case NAND_CMD_STATUS:
 291         case NAND_CMD_DEPLETE1:
 292         case NAND_CMD_RNDOUT:
 293         case NAND_CMD_STATUS_ERROR:
 294         case NAND_CMD_STATUS_ERROR0:
 295         case NAND_CMD_STATUS_ERROR1:
 296         case NAND_CMD_STATUS_ERROR2:
 297         case NAND_CMD_STATUS_ERROR3:
 298                 writel(cafe->ctl2, cafe->mmio + CAFE_NAND_CTRL2);
 299                 return;
 300         }
 301         nand_wait_ready(mtd);
 302         writel(cafe->ctl2, cafe->mmio + CAFE_NAND_CTRL2);
 303 }
 304
 305 static void cafe_select_chip(struct mtd_info *mtd, int chipnr)
 306 {
 307         //struct cafe_priv *cafe = mtd->priv;
 308         //      cafe_dev_dbg(&cafe->pdev->dev, "select_chip %d\n", chipnr);
 309 }
 310
 311 static int cafe_nand_interrupt(int irq, void *id, struct pt_regs *regs)
 312 {
 313         struct mtd_info *mtd = id;
 314         struct cafe_priv *cafe = mtd->priv;
 315         uint32_t irqs = readl(cafe->mmio + CAFE_NAND_IRQ);
 316         writel(irqs & ~0x90000000, cafe->mmio + CAFE_NAND_IRQ);
 317         if (!irqs)
 318                 return IRQ_NONE;
 319
 320         cafe_dev_dbg(&cafe->pdev->dev, "irq, bits %x (%x)\n", irqs, readl(cafe->mmio + CAFE_NAND_IRQ));
 321         return IRQ_HANDLED;
 322 }
 323
 324 static void cafe_nand_bug(struct mtd_info *mtd)
 325 {
 326         BUG();
 327 }
 328
 329 static int cafe_nand_write_oob(struct mtd_info *mtd,
 330                                struct nand_chip *chip, int page)
 331 {
 332         int status = 0;
 333
 334         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
 335         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
 336         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
 337         status = chip->waitfunc(mtd, chip);
 338
 339         return status & NAND_STATUS_FAIL ? -EIO : 0;
 340 }
 341
 342 /* Don't use -- use nand_read_oob_std for now */
 343 static int cafe_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
 344                               int page, int sndcmd)
 345 {
 346         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
 347         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 348         return 1;
 349 }
 350 /**
 351  * cafe_nand_read_page_syndrome - {REPLACABLE] hardware ecc syndrom based page read
 352  * @mtd:        mtd info structure
 353  * @chip:       nand chip info structure
 354  * @buf:        buffer to store read data
 355  *
 356  * The hw generator calculates the error syndrome automatically. Therefor
 357  * we need a special oob layout and handling.
 358  */
 359 static int cafe_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
 360                                uint8_t *buf)
 361 {
 362         struct cafe_priv *cafe = mtd->priv;
 363
 364         cafe_dev_dbg(&cafe->pdev->dev, "ECC result %08x SYN1,2 %08x\n",
 365                      readl(cafe->mmio + CAFE_NAND_ECC_RESULT),
 366                      readl(cafe->mmio + CAFE_NAND_ECC_SYN01));
 367
 368         chip->read_buf(mtd, buf, mtd->writesize);
 369         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 370
 371         if (checkecc && readl(cafe->mmio + CAFE_NAND_ECC_RESULT) & (1<<18)) {
 372                 unsigned short syn[8];
 373                 int i;
 374
 375                 for (i=0; i<8; i+=2) {
 376                         uint32_t tmp = readl(cafe->mmio + CAFE_NAND_ECC_SYN01 + (i*2));
 377                         syn[i] = tmp & 0xfff;
 378                         syn[i+1] = (tmp >> 16) & 0xfff;
 379                 }
 380
 381                 if ((i = cafe_correct_ecc(buf, syn)) < 0) {
 382                         dev_dbg(&cafe->pdev->dev, "Failed to correct ECC\n");
 383                         mtd->ecc_stats.failed++;
 384                 } else {
 385                         dev_dbg(&cafe->pdev->dev, "Corrected %d symbol errors\n", i);
 386                         mtd->ecc_stats.corrected += i;
 387                 }
 388         }
 389
 390
 391         return 0;
 392 }
 393
 394 static struct nand_ecclayout cafe_oobinfo_2048 = {
 395         .eccbytes = 14,
 396         .eccpos = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13},
 397         .oobfree = {{14, 50}}
 398 };
 399
 400 /* Ick. The BBT code really ought to be able to work this bit out
 401    for itself from the above, at least for the 2KiB case */
 402 static uint8_t cafe_bbt_pattern_2048[] = { 'B', 'b', 't', '0' };
 403 static uint8_t cafe_mirror_pattern_2048[] = { '1', 't', 'b', 'B' };
 404
 405 static uint8_t cafe_bbt_pattern_512[] = { 0xBB };
 406 static uint8_t cafe_mirror_pattern_512[] = { 0xBC };
 407
 408
 409 static struct nand_bbt_descr cafe_bbt_main_descr_2048 = {
 410         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
 411                 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
 412         .offs = 14,
 413         .len = 4,
 414         .veroffs = 18,
 415         .maxblocks = 4,
 416         .pattern = cafe_bbt_pattern_2048
 417 };
 418
 419 static struct nand_bbt_descr cafe_bbt_mirror_descr_2048 = {
 420         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
 421                 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
 422         .offs = 14,
 423         .len = 4,
 424         .veroffs = 18,
 425         .maxblocks = 4,
 426         .pattern = cafe_mirror_pattern_2048
 427 };
 428
 429 static struct nand_ecclayout cafe_oobinfo_512 = {
 430         .eccbytes = 14,
 431         .eccpos = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13},
 432         .oobfree = {{14, 2}}
 433 };
 434
 435 static struct nand_bbt_descr cafe_bbt_main_descr_512 = {
 436         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
 437                 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
 438         .offs = 14,
 439         .len = 1,
 440         .veroffs = 15,
 441         .maxblocks = 4,
 442         .pattern = cafe_bbt_pattern_512
 443 };
 444
 445 static struct nand_bbt_descr cafe_bbt_mirror_descr_512 = {
 446         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
 447                 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
 448         .offs = 14,
 449         .len = 1,
 450         .veroffs = 15,
 451         .maxblocks = 4,
 452         .pattern = cafe_mirror_pattern_512
 453 };
 454
 455
 456 static void cafe_nand_write_page_lowlevel(struct mtd_info *mtd,
 457                                           struct nand_chip *chip, const uint8_t *buf)
 458 {
 459         struct cafe_priv *cafe = mtd->priv;
 460
 461         chip->write_buf(mtd, buf, mtd->writesize);
 462         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
 463
 464         /* Set up ECC autogeneration */
 465         cafe->ctl2 |= (1<<27) | (1<<30);
 466         if (mtd->writesize == 2048)
 467                 cafe->ctl2 |= (1<<29);
 468 }
 469
 470 static int cafe_nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
 471                                 const uint8_t *buf, int page, int cached, int raw)
 472 {
 473         int status;
 474
 475         chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
 476
 477         if (unlikely(raw))
 478                 chip->ecc.write_page_raw(mtd, chip, buf);
 479         else
 480                 chip->ecc.write_page(mtd, chip, buf);
 481
 482         /*
 483          * Cached progamming disabled for now, Not sure if its worth the
 484          * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
 485          */
 486         cached = 0;
 487
 488         if (!cached || !(chip->options & NAND_CACHEPRG)) {
 489
 490                 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
 491                 status = chip->waitfunc(mtd, chip);
 492                 /*
 493                  * See if operation failed and additional status checks are
 494                  * available
 495                  */
 496                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
 497                         status = chip->errstat(mtd, chip, FL_WRITING, status,
 498                                                page);
 499
 500                 if (status & NAND_STATUS_FAIL)
 501                         return -EIO;
 502         } else {
 503                 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
 504                 status = chip->waitfunc(mtd, chip);
 505         }
 506
 507 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
 508         /* Send command to read back the data */
 509         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
 510
 511         if (chip->verify_buf(mtd, buf, mtd->writesize))
 512                 return -EIO;
 513 #endif
 514         return 0;
 515 }
 516
 517 static int cafe_nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
 518 {
 519         return 0;
 520 }
 521
 522 static int __devinit cafe_nand_probe(struct pci_dev *pdev,
 523                                      const struct pci_device_id *ent)
 524 {
 525         struct mtd_info *mtd;
 526         struct cafe_priv *cafe;
 527         uint32_t ctrl;
 528         int err = 0;
 529
 530         err = pci_enable_device(pdev);
 531         if (err)
 532                 return err;
 533
 534         pci_set_master(pdev);
 535
 536         mtd = kzalloc(sizeof(*mtd) + sizeof(struct cafe_priv), GFP_KERNEL);
 537         if (!mtd) {
 538                 dev_warn(&pdev->dev, "failed to alloc mtd_info\n");
 539                 return  -ENOMEM;
 540         }
 541         cafe = (void *)(&mtd[1]);
 542
 543         mtd->priv = cafe;
 544         mtd->owner = THIS_MODULE;
 545
 546         cafe->pdev = pdev;
 547         cafe->mmio = pci_iomap(pdev, 0, 0);
 548         if (!cafe->mmio) {
 549                 dev_warn(&pdev->dev, "failed to iomap\n");
 550                 err = -ENOMEM;
 551                 goto out_free_mtd;
 552         }
 553         cafe->dmabuf = dma_alloc_coherent(&cafe->pdev->dev, 2112 + sizeof(struct nand_buffers),
 554                                           &cafe->dmaaddr, GFP_KERNEL);
 555         if (!cafe->dmabuf) {
 556                 err = -ENOMEM;
 557                 goto out_ior;
 558         }
 559         cafe->nand.buffers = (void *)cafe->dmabuf + 2112;
 560
 561         cafe->nand.cmdfunc = cafe_nand_cmdfunc;
 562         cafe->nand.dev_ready = cafe_device_ready;
 563         cafe->nand.read_byte = cafe_read_byte;
 564         cafe->nand.read_buf = cafe_read_buf;
 565         cafe->nand.write_buf = cafe_write_buf;
 566         cafe->nand.select_chip = cafe_select_chip;
 567
 568         cafe->nand.chip_delay = 0;
 569
 570         /* Enable the following for a flash based bad block table */
 571         cafe->nand.options = NAND_USE_FLASH_BBT | NAND_NO_AUTOINCR | NAND_OWN_BUFFERS;
 572
 573         if (skipbbt) {
 574                 cafe->nand.options |= NAND_SKIP_BBTSCAN;
 575                 cafe->nand.block_bad = cafe_nand_block_bad;
 576         }
 577
 578         /* Start off by resetting the NAND controller completely */
 579         writel(1, cafe->mmio + 0x3034);
 580         writel(0, cafe->mmio + 0x3034);
 581
 582         /* Timings from Marvell's test code (not verified or calculated by us) */
 583         writel(0xffffffff, cafe->mmio + CAFE_NAND_IRQ_MASK);
 584
 585         if (!slowtiming) {
 586                 writel(0x01010a0a, cafe->mmio + CAFE_NAND_TIMING1);
 587                 writel(0x24121212, cafe->mmio + CAFE_NAND_TIMING2);
 588                 writel(0x11000000, cafe->mmio + CAFE_NAND_TIMING3);
 589         } else {
 590                 writel(0xffffffff, cafe->mmio + CAFE_NAND_TIMING1);
 591                 writel(0xffffffff, cafe->mmio + CAFE_NAND_TIMING2);
 592                 writel(0xffffffff, cafe->mmio + CAFE_NAND_TIMING3);
 593         }
 594         writel(0xffffffff, cafe->mmio + CAFE_NAND_IRQ_MASK);
 595         err = request_irq(pdev->irq, &cafe_nand_interrupt, SA_SHIRQ, "CAFE NAND", mtd);
 596         if (err) {
 597                 dev_warn(&pdev->dev, "Could not register IRQ %d\n", pdev->irq);
 598
 599                 goto out_free_dma;
 600         }
 601 #if 1
 602         /* Disable master reset, enable NAND clock */
 603         ctrl = readl(cafe->mmio + 0x3004);
 604         ctrl &= 0xffffeff0;
 605         ctrl |= 0x00007000;
 606         writel(ctrl | 0x05, cafe->mmio + 0x3004);
 607         writel(ctrl | 0x0a, cafe->mmio + 0x3004);
 608         writel(0, cafe->mmio + CAFE_NAND_DMA_CTRL);
 609
 610         writel(0x7006, cafe->mmio + 0x3004);
 611         writel(0x700a, cafe->mmio + 0x3004);
 612
 613         /* Set up DMA address */
 614         writel(cafe->dmaaddr & 0xffffffff, cafe->mmio + CAFE_NAND_DMA_ADDR0);
 615         if (sizeof(cafe->dmaaddr) > 4)
 616                 /* Shift in two parts to shut the compiler up */
 617                 writel((cafe->dmaaddr >> 16) >> 16, cafe->mmio + CAFE_NAND_DMA_ADDR1);
 618         else
 619                 writel(0, cafe->mmio + CAFE_NAND_DMA_ADDR1);
 620
 621         cafe_dev_dbg(&cafe->pdev->dev, "Set DMA address to %x (virt %p)\n",
 622                 readl(cafe->mmio + CAFE_NAND_DMA_ADDR0), cafe->dmabuf);
 623
 624         /* Enable NAND IRQ in global IRQ mask register */
 625         writel(0x80000007, cafe->mmio + 0x300c);
 626         cafe_dev_dbg(&cafe->pdev->dev, "Control %x, IRQ mask %x\n",
 627                 readl(cafe->mmio + 0x3004), readl(cafe->mmio + 0x300c));
 628 #endif
 629 #if 1
 630         mtd->writesize=2048;
 631         mtd->oobsize = 0x40;
 632         memset(cafe->dmabuf, 0x5a, 2112);
 633         cafe->nand.cmdfunc(mtd, NAND_CMD_READID, 0, -1);
 634         cafe->nand.read_byte(mtd);
 635         cafe->nand.read_byte(mtd);
 636         cafe->nand.read_byte(mtd);
 637         cafe->nand.read_byte(mtd);
 638         cafe->nand.read_byte(mtd);
 639 #endif
 640 #if 0
 641         cafe->nand.cmdfunc(mtd, NAND_CMD_READ0, 0, 0);
 642         //      nand_wait_ready(mtd);
 643         cafe->nand.read_byte(mtd);
 644         cafe->nand.read_byte(mtd);
 645         cafe->nand.read_byte(mtd);
 646         cafe->nand.read_byte(mtd);
 647 #endif
 648 #if 0
 649         writel(0x84600070, cafe->mmio);
 650         udelay(10);
 651         cafe_dev_dbg(&cafe->pdev->dev, "Status %x\n", readl(cafe->mmio + 0x30));
 652 #endif
 653         /* Scan to find existance of the device */
 654         if (nand_scan_ident(mtd, 1)) {
 655                 err = -ENXIO;
 656                 goto out_irq;
 657         }
 658
 659         cafe->ctl2 = 1<<27; /* Reed-Solomon ECC */
 660         if (mtd->writesize == 2048)
 661                 cafe->ctl2 |= 1<<29; /* 2KiB page size */
 662
 663         /* Set up ECC according to the type of chip we found */
 664         if (mtd->writesize == 2048) {
 665                 cafe->nand.ecc.layout = &cafe_oobinfo_2048;
 666                 cafe->nand.bbt_td = &cafe_bbt_main_descr_2048;
 667                 cafe->nand.bbt_md = &cafe_bbt_mirror_descr_2048;
 668         } else if (mtd->writesize == 512) {
 669                 cafe->nand.ecc.layout = &cafe_oobinfo_512;
 670                 cafe->nand.bbt_td = &cafe_bbt_main_descr_512;
 671                 cafe->nand.bbt_md = &cafe_bbt_mirror_descr_512;
 672         } else {
 673                 printk(KERN_WARNING "Unexpected NAND flash writesize %d. Aborting\n",
 674                        mtd->writesize);
 675                 goto out_irq;
 676         }
 677         cafe->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
 678         cafe->nand.ecc.size = mtd->writesize;
 679         cafe->nand.ecc.bytes = 14;
 680         cafe->nand.ecc.hwctl  = (void *)cafe_nand_bug;
 681         cafe->nand.ecc.calculate = (void *)cafe_nand_bug;
 682         cafe->nand.ecc.correct  = (void *)cafe_nand_bug;
 683         cafe->nand.write_page = cafe_nand_write_page;
 684         cafe->nand.ecc.write_page = cafe_nand_write_page_lowlevel;
 685         cafe->nand.ecc.write_oob = cafe_nand_write_oob;
 686         cafe->nand.ecc.read_page = cafe_nand_read_page;
 687         cafe->nand.ecc.read_oob = cafe_nand_read_oob;
 688
 689         err = nand_scan_tail(mtd);
 690         if (err)
 691                 goto out_irq;
 692
 693         pci_set_drvdata(pdev, mtd);
 694         add_mtd_device(mtd);
 695         goto out;
 696
 697  out_irq:
 698         /* Disable NAND IRQ in global IRQ mask register */
 699         writel(~1 & readl(cafe->mmio + 0x300c), cafe->mmio + 0x300c);
 700         free_irq(pdev->irq, mtd);
 701  out_free_dma:
 702         dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr);
 703  out_ior:
 704         pci_iounmap(pdev, cafe->mmio);
 705  out_free_mtd:
 706         kfree(mtd);
 707  out:
 708         return err;
 709 }
 710
 711 static void __devexit cafe_nand_remove(struct pci_dev *pdev)
 712 {
 713         struct mtd_info *mtd = pci_get_drvdata(pdev);
 714         struct cafe_priv *cafe = mtd->priv;
 715
 716         del_mtd_device(mtd);
 717         /* Disable NAND IRQ in global IRQ mask register */
 718         writel(~1 & readl(cafe->mmio + 0x300c), cafe->mmio + 0x300c);
 719         free_irq(pdev->irq, mtd);
 720         nand_release(mtd);
 721         pci_iounmap(pdev, cafe->mmio);
 722         dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr);
 723         kfree(mtd);
 724 }
 725
 726 static struct pci_device_id cafe_nand_tbl[] = {
 727         { 0x11ab, 0x4100, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MEMORY_FLASH << 8, 0xFFFF0 }
 728 };
 729
 730 MODULE_DEVICE_TABLE(pci, cafe_nand_tbl);
 731
 732 static struct pci_driver cafe_nand_pci_driver = {
 733         .name = "CAFÉ NAND",
 734         .id_table = cafe_nand_tbl,
 735         .probe = cafe_nand_probe,
 736         .remove = __devexit_p(cafe_nand_remove),
 737 #ifdef CONFIG_PMx
 738         .suspend = cafe_nand_suspend,
 739         .resume = cafe_nand_resume,
 740 #endif
 741 };
 742
 743 static int cafe_nand_init(void)
 744 {
 745         return pci_register_driver(&cafe_nand_pci_driver);
 746 }
 747
 748 static void cafe_nand_exit(void)
 749 {
 750         pci_unregister_driver(&cafe_nand_pci_driver);
 751 }
 752 module_init(cafe_nand_init);
 753 module_exit(cafe_nand_exit);
 754
 755 MODULE_LICENSE("GPL");
 756 MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
 757 MODULE_DESCRIPTION("NAND flash driver for OLPC CAFE chip");
 758
 759 /* Correct ECC for 2048 bytes of 0xff:
 760    41 a0 71 65 54 27 f3 93 ec a9 be ed 0b a1 */
 761
 762 /* dwmw2's B-test board, in case of completely screwing it:
 763 Bad eraseblock 2394 at 0x12b40000
 764 Bad eraseblock 2627 at 0x14860000
 765 Bad eraseblock 3349 at 0x1a2a0000
 766 */