5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 * Basic support for AG-AND chips is provided.
9 * Additional technical information is available on
10 * http://www.linux-mtd.infradead.org/tech/nand.html
12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
16 * David Woodhouse for adding multichip support
18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19 * rework for 2K page size chips
22 * Enable cached programming for 2k page size chips
23 * Check, if mtd->ecctype should be set to MTD_ECC_HW
24 * if we have HW ecc support.
25 * The AG-AND chips have nice features for speed improvement,
26 * which are not supported yet. Read / program 4 pages in one go.
28 * This program is free software; you can redistribute it and/or modify
29 * it under the terms of the GNU General Public License version 2 as
30 * published by the Free Software Foundation.
34 #include <linux/module.h>
35 #include <linux/delay.h>
36 #include <linux/errno.h>
37 #include <linux/err.h>
38 #include <linux/sched.h>
39 #include <linux/slab.h>
40 #include <linux/types.h>
41 #include <linux/mtd/mtd.h>
42 #include <linux/mtd/nand.h>
43 #include <linux/mtd/nand_ecc.h>
44 #include <linux/mtd/compatmac.h>
45 #include <linux/interrupt.h>
46 #include <linux/bitops.h>
47 #include <linux/leds.h>
50 #ifdef CONFIG_MTD_PARTITIONS
51 #include <linux/mtd/partitions.h>
54 /* Define default oob placement schemes for large and small page devices */
55 static struct nand_ecclayout nand_oob_8 = {
65 static struct nand_ecclayout nand_oob_16 = {
67 .eccpos = {0, 1, 2, 3, 6, 7},
73 static struct nand_ecclayout nand_oob_64 = {
76 40, 41, 42, 43, 44, 45, 46, 47,
77 48, 49, 50, 51, 52, 53, 54, 55,
78 56, 57, 58, 59, 60, 61, 62, 63},
84 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
87 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
88 struct mtd_oob_ops *ops);
91 * For devices which display every fart in the system on a seperate LED. Is
92 * compiled away when LED support is disabled.
94 DEFINE_LED_TRIGGER(nand_led_trigger);
97 * nand_release_device - [GENERIC] release chip
98 * @mtd: MTD device structure
100 * Deselect, release chip lock and wake up anyone waiting on the device
102 static void nand_release_device(struct mtd_info *mtd)
104 struct nand_chip *chip = mtd->priv;
106 /* De-select the NAND device */
107 chip->select_chip(mtd, -1);
109 /* Release the controller and the chip */
110 spin_lock(&chip->controller->lock);
111 chip->controller->active = NULL;
112 chip->state = FL_READY;
113 wake_up(&chip->controller->wq);
114 spin_unlock(&chip->controller->lock);
118 * nand_read_byte - [DEFAULT] read one byte from the chip
119 * @mtd: MTD device structure
121 * Default read function for 8bit buswith
123 static uint8_t nand_read_byte(struct mtd_info *mtd)
125 struct nand_chip *chip = mtd->priv;
126 return readb(chip->IO_ADDR_R);
130 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
131 * @mtd: MTD device structure
133 * Default read function for 16bit buswith with
134 * endianess conversion
136 static uint8_t nand_read_byte16(struct mtd_info *mtd)
138 struct nand_chip *chip = mtd->priv;
139 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
143 * nand_read_word - [DEFAULT] read one word from the chip
144 * @mtd: MTD device structure
146 * Default read function for 16bit buswith without
147 * endianess conversion
149 static u16 nand_read_word(struct mtd_info *mtd)
151 struct nand_chip *chip = mtd->priv;
152 return readw(chip->IO_ADDR_R);
156 * nand_select_chip - [DEFAULT] control CE line
157 * @mtd: MTD device structure
158 * @chipnr: chipnumber to select, -1 for deselect
160 * Default select function for 1 chip devices.
162 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
164 struct nand_chip *chip = mtd->priv;
168 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
179 * nand_write_buf - [DEFAULT] write buffer to chip
180 * @mtd: MTD device structure
182 * @len: number of bytes to write
184 * Default write function for 8bit buswith
186 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
189 struct nand_chip *chip = mtd->priv;
191 for (i = 0; i < len; i++)
192 writeb(buf[i], chip->IO_ADDR_W);
196 * nand_read_buf - [DEFAULT] read chip data into buffer
197 * @mtd: MTD device structure
198 * @buf: buffer to store date
199 * @len: number of bytes to read
201 * Default read function for 8bit buswith
203 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
206 struct nand_chip *chip = mtd->priv;
208 for (i = 0; i < len; i++)
209 buf[i] = readb(chip->IO_ADDR_R);
213 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
214 * @mtd: MTD device structure
215 * @buf: buffer containing the data to compare
216 * @len: number of bytes to compare
218 * Default verify function for 8bit buswith
220 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
223 struct nand_chip *chip = mtd->priv;
225 for (i = 0; i < len; i++)
226 if (buf[i] != readb(chip->IO_ADDR_R))
232 * nand_write_buf16 - [DEFAULT] write buffer to chip
233 * @mtd: MTD device structure
235 * @len: number of bytes to write
237 * Default write function for 16bit buswith
239 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
242 struct nand_chip *chip = mtd->priv;
243 u16 *p = (u16 *) buf;
246 for (i = 0; i < len; i++)
247 writew(p[i], chip->IO_ADDR_W);
252 * nand_read_buf16 - [DEFAULT] read chip data into buffer
253 * @mtd: MTD device structure
254 * @buf: buffer to store date
255 * @len: number of bytes to read
257 * Default read function for 16bit buswith
259 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
262 struct nand_chip *chip = mtd->priv;
263 u16 *p = (u16 *) buf;
266 for (i = 0; i < len; i++)
267 p[i] = readw(chip->IO_ADDR_R);
271 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
272 * @mtd: MTD device structure
273 * @buf: buffer containing the data to compare
274 * @len: number of bytes to compare
276 * Default verify function for 16bit buswith
278 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
281 struct nand_chip *chip = mtd->priv;
282 u16 *p = (u16 *) buf;
285 for (i = 0; i < len; i++)
286 if (p[i] != readw(chip->IO_ADDR_R))
293 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
294 * @mtd: MTD device structure
295 * @ofs: offset from device start
296 * @getchip: 0, if the chip is already selected
298 * Check, if the block is bad.
300 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
302 int page, chipnr, res = 0;
303 struct nand_chip *chip = mtd->priv;
307 page = (int)(ofs >> chip->page_shift);
308 chipnr = (int)(ofs >> chip->chip_shift);
310 nand_get_device(chip, mtd, FL_READING);
312 /* Select the NAND device */
313 chip->select_chip(mtd, chipnr);
317 if (chip->options & NAND_BUSWIDTH_16) {
318 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
319 page & chip->pagemask);
320 bad = cpu_to_le16(chip->read_word(mtd));
321 if (chip->badblockpos & 0x1)
323 if ((bad & 0xFF) != 0xff)
326 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
327 page & chip->pagemask);
328 if (chip->read_byte(mtd) != 0xff)
333 nand_release_device(mtd);
339 * nand_default_block_markbad - [DEFAULT] mark a block bad
340 * @mtd: MTD device structure
341 * @ofs: offset from device start
343 * This is the default implementation, which can be overridden by
344 * a hardware specific driver.
346 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
348 struct nand_chip *chip = mtd->priv;
349 uint8_t buf[2] = { 0, 0 };
352 /* Get block number */
353 block = ((int)ofs) >> chip->bbt_erase_shift;
355 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
357 /* Do we have a flash based bad block table ? */
358 if (chip->options & NAND_USE_FLASH_BBT)
359 ret = nand_update_bbt(mtd, ofs);
361 /* We write two bytes, so we dont have to mess with 16 bit
365 chip->ops.len = chip->ops.ooblen = 2;
366 chip->ops.datbuf = NULL;
367 chip->ops.oobbuf = buf;
368 chip->ops.ooboffs = chip->badblockpos & ~0x01;
370 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
373 mtd->ecc_stats.badblocks++;
378 * nand_check_wp - [GENERIC] check if the chip is write protected
379 * @mtd: MTD device structure
380 * Check, if the device is write protected
382 * The function expects, that the device is already selected
384 static int nand_check_wp(struct mtd_info *mtd)
386 struct nand_chip *chip = mtd->priv;
387 /* Check the WP bit */
388 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
389 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
393 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
394 * @mtd: MTD device structure
395 * @ofs: offset from device start
396 * @getchip: 0, if the chip is already selected
397 * @allowbbt: 1, if its allowed to access the bbt area
399 * Check, if the block is bad. Either by reading the bad block table or
400 * calling of the scan function.
402 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
405 struct nand_chip *chip = mtd->priv;
408 return chip->block_bad(mtd, ofs, getchip);
410 /* Return info from the table */
411 return nand_isbad_bbt(mtd, ofs, allowbbt);
415 * Wait for the ready pin, after a command
416 * The timeout is catched later.
418 void nand_wait_ready(struct mtd_info *mtd)
420 struct nand_chip *chip = mtd->priv;
421 unsigned long timeo = jiffies + 2;
423 led_trigger_event(nand_led_trigger, LED_FULL);
424 /* wait until command is processed or timeout occures */
426 if (chip->dev_ready(mtd))
428 touch_softlockup_watchdog();
429 } while (time_before(jiffies, timeo));
430 led_trigger_event(nand_led_trigger, LED_OFF);
432 EXPORT_SYMBOL_GPL(nand_wait_ready);
435 * nand_command - [DEFAULT] Send command to NAND device
436 * @mtd: MTD device structure
437 * @command: the command to be sent
438 * @column: the column address for this command, -1 if none
439 * @page_addr: the page address for this command, -1 if none
441 * Send command to NAND device. This function is used for small page
442 * devices (256/512 Bytes per page)
444 static void nand_command(struct mtd_info *mtd, unsigned int command,
445 int column, int page_addr)
447 register struct nand_chip *chip = mtd->priv;
448 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
451 * Write out the command to the device.
453 if (command == NAND_CMD_SEQIN) {
456 if (column >= mtd->writesize) {
458 column -= mtd->writesize;
459 readcmd = NAND_CMD_READOOB;
460 } else if (column < 256) {
461 /* First 256 bytes --> READ0 */
462 readcmd = NAND_CMD_READ0;
465 readcmd = NAND_CMD_READ1;
467 chip->cmd_ctrl(mtd, readcmd, ctrl);
468 ctrl &= ~NAND_CTRL_CHANGE;
470 chip->cmd_ctrl(mtd, command, ctrl);
473 * Address cycle, when necessary
475 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
476 /* Serially input address */
478 /* Adjust columns for 16 bit buswidth */
479 if (chip->options & NAND_BUSWIDTH_16)
481 chip->cmd_ctrl(mtd, column, ctrl);
482 ctrl &= ~NAND_CTRL_CHANGE;
484 if (page_addr != -1) {
485 chip->cmd_ctrl(mtd, page_addr, ctrl);
486 ctrl &= ~NAND_CTRL_CHANGE;
487 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
488 /* One more address cycle for devices > 32MiB */
489 if (chip->chipsize > (32 << 20))
490 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
492 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
495 * program and erase have their own busy handlers
496 * status and sequential in needs no delay
500 case NAND_CMD_PAGEPROG:
501 case NAND_CMD_ERASE1:
502 case NAND_CMD_ERASE2:
504 case NAND_CMD_STATUS:
510 udelay(chip->chip_delay);
511 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
512 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
514 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
515 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
518 /* This applies to read commands */
521 * If we don't have access to the busy pin, we apply the given
524 if (!chip->dev_ready) {
525 udelay(chip->chip_delay);
529 /* Apply this short delay always to ensure that we do wait tWB in
530 * any case on any machine. */
533 nand_wait_ready(mtd);
537 * nand_command_lp - [DEFAULT] Send command to NAND large page device
538 * @mtd: MTD device structure
539 * @command: the command to be sent
540 * @column: the column address for this command, -1 if none
541 * @page_addr: the page address for this command, -1 if none
543 * Send command to NAND device. This is the version for the new large page
544 * devices We dont have the separate regions as we have in the small page
545 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
547 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
548 int column, int page_addr)
550 register struct nand_chip *chip = mtd->priv;
552 /* Emulate NAND_CMD_READOOB */
553 if (command == NAND_CMD_READOOB) {
554 column += mtd->writesize;
555 command = NAND_CMD_READ0;
558 /* Command latch cycle */
559 chip->cmd_ctrl(mtd, command & 0xff,
560 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
562 if (column != -1 || page_addr != -1) {
563 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
565 /* Serially input address */
567 /* Adjust columns for 16 bit buswidth */
568 if (chip->options & NAND_BUSWIDTH_16)
570 chip->cmd_ctrl(mtd, column, ctrl);
571 ctrl &= ~NAND_CTRL_CHANGE;
572 chip->cmd_ctrl(mtd, column >> 8, ctrl);
574 if (page_addr != -1) {
575 chip->cmd_ctrl(mtd, page_addr, ctrl);
576 chip->cmd_ctrl(mtd, page_addr >> 8,
577 NAND_NCE | NAND_ALE);
578 /* One more address cycle for devices > 128MiB */
579 if (chip->chipsize > (128 << 20))
580 chip->cmd_ctrl(mtd, page_addr >> 16,
581 NAND_NCE | NAND_ALE);
584 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
587 * program and erase have their own busy handlers
588 * status, sequential in, and deplete1 need no delay
592 case NAND_CMD_CACHEDPROG:
593 case NAND_CMD_PAGEPROG:
594 case NAND_CMD_ERASE1:
595 case NAND_CMD_ERASE2:
598 case NAND_CMD_STATUS:
599 case NAND_CMD_DEPLETE1:
603 * read error status commands require only a short delay
605 case NAND_CMD_STATUS_ERROR:
606 case NAND_CMD_STATUS_ERROR0:
607 case NAND_CMD_STATUS_ERROR1:
608 case NAND_CMD_STATUS_ERROR2:
609 case NAND_CMD_STATUS_ERROR3:
610 udelay(chip->chip_delay);
616 udelay(chip->chip_delay);
617 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
618 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
619 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
620 NAND_NCE | NAND_CTRL_CHANGE);
621 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
624 case NAND_CMD_RNDOUT:
625 /* No ready / busy check necessary */
626 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
627 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
628 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
629 NAND_NCE | NAND_CTRL_CHANGE);
633 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
634 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
635 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
636 NAND_NCE | NAND_CTRL_CHANGE);
638 /* This applies to read commands */
641 * If we don't have access to the busy pin, we apply the given
644 if (!chip->dev_ready) {
645 udelay(chip->chip_delay);
650 /* Apply this short delay always to ensure that we do wait tWB in
651 * any case on any machine. */
654 nand_wait_ready(mtd);
658 * nand_get_device - [GENERIC] Get chip for selected access
659 * @chip: the nand chip descriptor
660 * @mtd: MTD device structure
661 * @new_state: the state which is requested
663 * Get the device and lock it for exclusive access
666 nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
668 spinlock_t *lock = &chip->controller->lock;
669 wait_queue_head_t *wq = &chip->controller->wq;
670 DECLARE_WAITQUEUE(wait, current);
674 /* Hardware controller shared among independend devices */
675 /* Hardware controller shared among independend devices */
676 if (!chip->controller->active)
677 chip->controller->active = chip;
679 if (chip->controller->active == chip && chip->state == FL_READY) {
680 chip->state = new_state;
684 if (new_state == FL_PM_SUSPENDED) {
686 return (chip->state == FL_PM_SUSPENDED) ? 0 : -EAGAIN;
688 set_current_state(TASK_UNINTERRUPTIBLE);
689 add_wait_queue(wq, &wait);
692 remove_wait_queue(wq, &wait);
697 * nand_wait - [DEFAULT] wait until the command is done
698 * @mtd: MTD device structure
699 * @chip: NAND chip structure
701 * Wait for command done. This applies to erase and program only
702 * Erase can take up to 400ms and program up to 20ms according to
703 * general NAND and SmartMedia specs
705 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
708 unsigned long timeo = jiffies;
709 int status, state = chip->state;
711 if (state == FL_ERASING)
712 timeo += (HZ * 400) / 1000;
714 timeo += (HZ * 20) / 1000;
716 led_trigger_event(nand_led_trigger, LED_FULL);
718 /* Apply this short delay always to ensure that we do wait tWB in
719 * any case on any machine. */
722 if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
723 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
725 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
727 while (time_before(jiffies, timeo)) {
728 if (chip->dev_ready) {
729 if (chip->dev_ready(mtd))
732 if (chip->read_byte(mtd) & NAND_STATUS_READY)
737 led_trigger_event(nand_led_trigger, LED_OFF);
739 status = (int)chip->read_byte(mtd);
744 * nand_read_page_raw - [Intern] read raw page data without ecc
745 * @mtd: mtd info structure
746 * @chip: nand chip info structure
747 * @buf: buffer to store read data
749 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
752 chip->read_buf(mtd, buf, mtd->writesize);
753 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
758 * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
759 * @mtd: mtd info structure
760 * @chip: nand chip info structure
761 * @buf: buffer to store read data
763 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
766 int i, eccsize = chip->ecc.size;
767 int eccbytes = chip->ecc.bytes;
768 int eccsteps = chip->ecc.steps;
770 uint8_t *ecc_calc = chip->buffers->ecccalc;
771 uint8_t *ecc_code = chip->buffers->ecccode;
772 int *eccpos = chip->ecc.layout->eccpos;
774 nand_read_page_raw(mtd, chip, buf);
776 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
777 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
779 for (i = 0; i < chip->ecc.total; i++)
780 ecc_code[i] = chip->oob_poi[eccpos[i]];
782 eccsteps = chip->ecc.steps;
785 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
788 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
790 mtd->ecc_stats.failed++;
792 mtd->ecc_stats.corrected += stat;
798 * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
799 * @mtd: mtd info structure
800 * @chip: nand chip info structure
801 * @buf: buffer to store read data
803 * Not for syndrome calculating ecc controllers which need a special oob layout
805 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
808 int i, eccsize = chip->ecc.size;
809 int eccbytes = chip->ecc.bytes;
810 int eccsteps = chip->ecc.steps;
812 uint8_t *ecc_calc = chip->buffers->ecccalc;
813 uint8_t *ecc_code = chip->buffers->ecccode;
814 int *eccpos = chip->ecc.layout->eccpos;
816 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
817 chip->ecc.hwctl(mtd, NAND_ECC_READ);
818 chip->read_buf(mtd, p, eccsize);
819 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
821 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
823 for (i = 0; i < chip->ecc.total; i++)
824 ecc_code[i] = chip->oob_poi[eccpos[i]];
826 eccsteps = chip->ecc.steps;
829 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
832 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
834 mtd->ecc_stats.failed++;
836 mtd->ecc_stats.corrected += stat;
842 * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
843 * @mtd: mtd info structure
844 * @chip: nand chip info structure
845 * @buf: buffer to store read data
847 * The hw generator calculates the error syndrome automatically. Therefor
848 * we need a special oob layout and handling.
850 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
853 int i, eccsize = chip->ecc.size;
854 int eccbytes = chip->ecc.bytes;
855 int eccsteps = chip->ecc.steps;
857 uint8_t *oob = chip->oob_poi;
859 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
862 chip->ecc.hwctl(mtd, NAND_ECC_READ);
863 chip->read_buf(mtd, p, eccsize);
865 if (chip->ecc.prepad) {
866 chip->read_buf(mtd, oob, chip->ecc.prepad);
867 oob += chip->ecc.prepad;
870 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
871 chip->read_buf(mtd, oob, eccbytes);
872 stat = chip->ecc.correct(mtd, p, oob, NULL);
875 mtd->ecc_stats.failed++;
877 mtd->ecc_stats.corrected += stat;
881 if (chip->ecc.postpad) {
882 chip->read_buf(mtd, oob, chip->ecc.postpad);
883 oob += chip->ecc.postpad;
887 /* Calculate remaining oob bytes */
888 i = mtd->oobsize - (oob - chip->oob_poi);
890 chip->read_buf(mtd, oob, i);
896 * nand_transfer_oob - [Internal] Transfer oob to client buffer
897 * @chip: nand chip structure
898 * @oob: oob destination address
899 * @ops: oob ops structure
901 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
902 struct mtd_oob_ops *ops)
904 size_t len = ops->ooblen;
910 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
914 struct nand_oobfree *free = chip->ecc.layout->oobfree;
915 uint32_t boffs = 0, roffs = ops->ooboffs;
918 for(; free->length && len; free++, len -= bytes) {
919 /* Read request not from offset 0 ? */
920 if (unlikely(roffs)) {
921 if (roffs >= free->length) {
922 roffs -= free->length;
925 boffs = free->offset + roffs;
926 bytes = min_t(size_t, len,
927 (free->length - roffs));
930 bytes = min_t(size_t, len, free->length);
931 boffs = free->offset;
933 memcpy(oob, chip->oob_poi + boffs, bytes);
945 * nand_do_read_ops - [Internal] Read data with ECC
947 * @mtd: MTD device structure
948 * @from: offset to read from
949 * @ops: oob ops structure
951 * Internal function. Called with chip held.
953 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
954 struct mtd_oob_ops *ops)
956 int chipnr, page, realpage, col, bytes, aligned;
957 struct nand_chip *chip = mtd->priv;
958 struct mtd_ecc_stats stats;
959 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
962 uint32_t readlen = ops->len;
963 uint8_t *bufpoi, *oob, *buf;
965 stats = mtd->ecc_stats;
967 chipnr = (int)(from >> chip->chip_shift);
968 chip->select_chip(mtd, chipnr);
970 realpage = (int)(from >> chip->page_shift);
971 page = realpage & chip->pagemask;
973 col = (int)(from & (mtd->writesize - 1));
979 bytes = min(mtd->writesize - col, readlen);
980 aligned = (bytes == mtd->writesize);
982 /* Is the current page in the buffer ? */
983 if (realpage != chip->pagebuf || oob) {
984 bufpoi = aligned ? buf : chip->buffers->databuf;
986 if (likely(sndcmd)) {
987 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
991 /* Now read the page into the buffer */
992 if (unlikely(ops->mode == MTD_OOB_RAW))
993 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi);
995 ret = chip->ecc.read_page(mtd, chip, bufpoi);
999 /* Transfer not aligned data */
1001 chip->pagebuf = realpage;
1002 memcpy(buf, chip->buffers->databuf + col, bytes);
1007 if (unlikely(oob)) {
1008 /* Raw mode does data:oob:data:oob */
1009 if (ops->mode != MTD_OOB_RAW)
1010 oob = nand_transfer_oob(chip, oob, ops);
1012 buf = nand_transfer_oob(chip, buf, ops);
1015 if (!(chip->options & NAND_NO_READRDY)) {
1017 * Apply delay or wait for ready/busy pin. Do
1018 * this before the AUTOINCR check, so no
1019 * problems arise if a chip which does auto
1020 * increment is marked as NOAUTOINCR by the
1023 if (!chip->dev_ready)
1024 udelay(chip->chip_delay);
1026 nand_wait_ready(mtd);
1029 memcpy(buf, chip->buffers->databuf + col, bytes);
1038 /* For subsequent reads align to page boundary. */
1040 /* Increment page address */
1043 page = realpage & chip->pagemask;
1044 /* Check, if we cross a chip boundary */
1047 chip->select_chip(mtd, -1);
1048 chip->select_chip(mtd, chipnr);
1051 /* Check, if the chip supports auto page increment
1052 * or if we have hit a block boundary.
1054 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1058 ops->retlen = ops->len - (size_t) readlen;
1063 if (mtd->ecc_stats.failed - stats.failed)
1066 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1070 * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc
1071 * @mtd: MTD device structure
1072 * @from: offset to read from
1073 * @len: number of bytes to read
1074 * @retlen: pointer to variable to store the number of read bytes
1075 * @buf: the databuffer to put data
1077 * Get hold of the chip and call nand_do_read
1079 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1080 size_t *retlen, uint8_t *buf)
1082 struct nand_chip *chip = mtd->priv;
1085 /* Do not allow reads past end of device */
1086 if ((from + len) > mtd->size)
1091 nand_get_device(chip, mtd, FL_READING);
1093 chip->ops.len = len;
1094 chip->ops.datbuf = buf;
1095 chip->ops.oobbuf = NULL;
1097 ret = nand_do_read_ops(mtd, from, &chip->ops);
1099 *retlen = chip->ops.retlen;
1101 nand_release_device(mtd);
1107 * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
1108 * @mtd: mtd info structure
1109 * @chip: nand chip info structure
1110 * @page: page number to read
1111 * @sndcmd: flag whether to issue read command or not
1113 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1114 int page, int sndcmd)
1117 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1120 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1125 * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
1127 * @mtd: mtd info structure
1128 * @chip: nand chip info structure
1129 * @page: page number to read
1130 * @sndcmd: flag whether to issue read command or not
1132 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1133 int page, int sndcmd)
1135 uint8_t *buf = chip->oob_poi;
1136 int length = mtd->oobsize;
1137 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1138 int eccsize = chip->ecc.size;
1139 uint8_t *bufpoi = buf;
1140 int i, toread, sndrnd = 0, pos;
1142 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1143 for (i = 0; i < chip->ecc.steps; i++) {
1145 pos = eccsize + i * (eccsize + chunk);
1146 if (mtd->writesize > 512)
1147 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1149 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1152 toread = min_t(int, length, chunk);
1153 chip->read_buf(mtd, bufpoi, toread);
1158 chip->read_buf(mtd, bufpoi, length);
1164 * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
1165 * @mtd: mtd info structure
1166 * @chip: nand chip info structure
1167 * @page: page number to write
1169 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1173 const uint8_t *buf = chip->oob_poi;
1174 int length = mtd->oobsize;
1176 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1177 chip->write_buf(mtd, buf, length);
1178 /* Send command to program the OOB data */
1179 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1181 status = chip->waitfunc(mtd, chip);
1183 return status & NAND_STATUS_FAIL ? -EIO : 0;
1187 * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
1188 * with syndrome - only for large page flash !
1189 * @mtd: mtd info structure
1190 * @chip: nand chip info structure
1191 * @page: page number to write
1193 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1194 struct nand_chip *chip, int page)
1196 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1197 int eccsize = chip->ecc.size, length = mtd->oobsize;
1198 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1199 const uint8_t *bufpoi = chip->oob_poi;
1202 * data-ecc-data-ecc ... ecc-oob
1204 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1206 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1207 pos = steps * (eccsize + chunk);
1212 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1213 for (i = 0; i < steps; i++) {
1215 if (mtd->writesize <= 512) {
1216 uint32_t fill = 0xFFFFFFFF;
1220 int num = min_t(int, len, 4);
1221 chip->write_buf(mtd, (uint8_t *)&fill,
1226 pos = eccsize + i * (eccsize + chunk);
1227 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1231 len = min_t(int, length, chunk);
1232 chip->write_buf(mtd, bufpoi, len);
1237 chip->write_buf(mtd, bufpoi, length);
1239 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1240 status = chip->waitfunc(mtd, chip);
1242 return status & NAND_STATUS_FAIL ? -EIO : 0;
1246 * nand_do_read_oob - [Intern] NAND read out-of-band
1247 * @mtd: MTD device structure
1248 * @from: offset to read from
1249 * @ops: oob operations description structure
1251 * NAND read out-of-band data from the spare area
1253 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1254 struct mtd_oob_ops *ops)
1256 int page, realpage, chipnr, sndcmd = 1;
1257 struct nand_chip *chip = mtd->priv;
1258 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1259 int readlen = ops->len;
1260 uint8_t *buf = ops->oobbuf;
1262 DEBUG(MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08Lx, len = %i\n",
1263 (unsigned long long)from, readlen);
1265 chipnr = (int)(from >> chip->chip_shift);
1266 chip->select_chip(mtd, chipnr);
1268 /* Shift to get page */
1269 realpage = (int)(from >> chip->page_shift);
1270 page = realpage & chip->pagemask;
1273 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
1274 buf = nand_transfer_oob(chip, buf, ops);
1276 if (!(chip->options & NAND_NO_READRDY)) {
1278 * Apply delay or wait for ready/busy pin. Do this
1279 * before the AUTOINCR check, so no problems arise if a
1280 * chip which does auto increment is marked as
1281 * NOAUTOINCR by the board driver.
1283 if (!chip->dev_ready)
1284 udelay(chip->chip_delay);
1286 nand_wait_ready(mtd);
1289 readlen -= ops->ooblen;
1293 /* Increment page address */
1296 page = realpage & chip->pagemask;
1297 /* Check, if we cross a chip boundary */
1300 chip->select_chip(mtd, -1);
1301 chip->select_chip(mtd, chipnr);
1304 /* Check, if the chip supports auto page increment
1305 * or if we have hit a block boundary.
1307 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1311 ops->retlen = ops->len;
1316 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1317 * @mtd: MTD device structure
1318 * @from: offset to read from
1319 * @ops: oob operation description structure
1321 * NAND read data and/or out-of-band data
1323 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1324 struct mtd_oob_ops *ops)
1326 struct nand_chip *chip = mtd->priv;
1327 int ret = -ENOTSUPP;
1331 /* Do not allow reads past end of device */
1332 if ((from + ops->len) > mtd->size) {
1333 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: "
1334 "Attempt read beyond end of device\n");
1338 nand_get_device(chip, mtd, FL_READING);
1351 ret = nand_do_read_oob(mtd, from, ops);
1353 ret = nand_do_read_ops(mtd, from, ops);
1356 nand_release_device(mtd);
1362 * nand_write_page_raw - [Intern] raw page write function
1363 * @mtd: mtd info structure
1364 * @chip: nand chip info structure
1367 static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1370 chip->write_buf(mtd, buf, mtd->writesize);
1371 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1375 * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
1376 * @mtd: mtd info structure
1377 * @chip: nand chip info structure
1380 static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1383 int i, eccsize = chip->ecc.size;
1384 int eccbytes = chip->ecc.bytes;
1385 int eccsteps = chip->ecc.steps;
1386 uint8_t *ecc_calc = chip->buffers->ecccalc;
1387 const uint8_t *p = buf;
1388 int *eccpos = chip->ecc.layout->eccpos;
1390 /* Software ecc calculation */
1391 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1392 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1394 for (i = 0; i < chip->ecc.total; i++)
1395 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1397 nand_write_page_raw(mtd, chip, buf);
1401 * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
1402 * @mtd: mtd info structure
1403 * @chip: nand chip info structure
1406 static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1409 int i, eccsize = chip->ecc.size;
1410 int eccbytes = chip->ecc.bytes;
1411 int eccsteps = chip->ecc.steps;
1412 uint8_t *ecc_calc = chip->buffers->ecccalc;
1413 const uint8_t *p = buf;
1414 int *eccpos = chip->ecc.layout->eccpos;
1416 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1417 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1418 chip->write_buf(mtd, p, eccsize);
1419 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1422 for (i = 0; i < chip->ecc.total; i++)
1423 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1425 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1429 * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
1430 * @mtd: mtd info structure
1431 * @chip: nand chip info structure
1434 * The hw generator calculates the error syndrome automatically. Therefor
1435 * we need a special oob layout and handling.
1437 static void nand_write_page_syndrome(struct mtd_info *mtd,
1438 struct nand_chip *chip, const uint8_t *buf)
1440 int i, eccsize = chip->ecc.size;
1441 int eccbytes = chip->ecc.bytes;
1442 int eccsteps = chip->ecc.steps;
1443 const uint8_t *p = buf;
1444 uint8_t *oob = chip->oob_poi;
1446 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1448 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1449 chip->write_buf(mtd, p, eccsize);
1451 if (chip->ecc.prepad) {
1452 chip->write_buf(mtd, oob, chip->ecc.prepad);
1453 oob += chip->ecc.prepad;
1456 chip->ecc.calculate(mtd, p, oob);
1457 chip->write_buf(mtd, oob, eccbytes);
1460 if (chip->ecc.postpad) {
1461 chip->write_buf(mtd, oob, chip->ecc.postpad);
1462 oob += chip->ecc.postpad;
1466 /* Calculate remaining oob bytes */
1467 i = mtd->oobsize - (oob - chip->oob_poi);
1469 chip->write_buf(mtd, oob, i);
1473 * nand_write_page - [REPLACEABLE] write one page
1474 * @mtd: MTD device structure
1475 * @chip: NAND chip descriptor
1476 * @buf: the data to write
1477 * @page: page number to write
1478 * @cached: cached programming
1480 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1481 const uint8_t *buf, int page, int cached, int raw)
1485 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
1488 chip->ecc.write_page_raw(mtd, chip, buf);
1490 chip->ecc.write_page(mtd, chip, buf);
1493 * Cached progamming disabled for now, Not sure if its worth the
1494 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
1498 if (!cached || !(chip->options & NAND_CACHEPRG)) {
1500 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1501 status = chip->waitfunc(mtd, chip);
1503 * See if operation failed and additional status checks are
1506 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1507 status = chip->errstat(mtd, chip, FL_WRITING, status,
1510 if (status & NAND_STATUS_FAIL)
1513 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
1514 status = chip->waitfunc(mtd, chip);
1517 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
1518 /* Send command to read back the data */
1519 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1521 if (chip->verify_buf(mtd, buf, mtd->writesize))
1528 * nand_fill_oob - [Internal] Transfer client buffer to oob
1529 * @chip: nand chip structure
1530 * @oob: oob data buffer
1531 * @ops: oob ops structure
1533 static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob,
1534 struct mtd_oob_ops *ops)
1536 size_t len = ops->ooblen;
1542 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
1545 case MTD_OOB_AUTO: {
1546 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1547 uint32_t boffs = 0, woffs = ops->ooboffs;
1550 for(; free->length && len; free++, len -= bytes) {
1551 /* Write request not from offset 0 ? */
1552 if (unlikely(woffs)) {
1553 if (woffs >= free->length) {
1554 woffs -= free->length;
1557 boffs = free->offset + woffs;
1558 bytes = min_t(size_t, len,
1559 (free->length - woffs));
1562 bytes = min_t(size_t, len, free->length);
1563 boffs = free->offset;
1565 memcpy(chip->oob_poi + boffs, oob, bytes);
1576 #define NOTALIGNED(x) (x & (mtd->writesize-1)) != 0
1579 * nand_do_write_ops - [Internal] NAND write with ECC
1580 * @mtd: MTD device structure
1581 * @to: offset to write to
1582 * @ops: oob operations description structure
1584 * NAND write with ECC
1586 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
1587 struct mtd_oob_ops *ops)
1589 int chipnr, realpage, page, blockmask;
1590 struct nand_chip *chip = mtd->priv;
1591 uint32_t writelen = ops->len;
1592 uint8_t *oob = ops->oobbuf;
1593 uint8_t *buf = ops->datbuf;
1594 int bytes = mtd->writesize;
1599 /* reject writes, which are not page aligned */
1600 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
1601 printk(KERN_NOTICE "nand_write: "
1602 "Attempt to write not page aligned data\n");
1609 chipnr = (int)(to >> chip->chip_shift);
1610 chip->select_chip(mtd, chipnr);
1612 /* Check, if it is write protected */
1613 if (nand_check_wp(mtd))
1616 realpage = (int)(to >> chip->page_shift);
1617 page = realpage & chip->pagemask;
1618 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1620 /* Invalidate the page cache, when we write to the cached page */
1621 if (to <= (chip->pagebuf << chip->page_shift) &&
1622 (chip->pagebuf << chip->page_shift) < (to + ops->len))
1625 /* If we're not given explicit OOB data, let it be 0xFF */
1627 memset(chip->oob_poi, 0xff, mtd->oobsize);
1630 int cached = writelen > bytes && page != blockmask;
1633 oob = nand_fill_oob(chip, oob, ops);
1635 ret = chip->write_page(mtd, chip, buf, page, cached,
1636 (ops->mode == MTD_OOB_RAW));
1647 page = realpage & chip->pagemask;
1648 /* Check, if we cross a chip boundary */
1651 chip->select_chip(mtd, -1);
1652 chip->select_chip(mtd, chipnr);
1656 ops->retlen = ops->len - writelen;
1661 * nand_write - [MTD Interface] NAND write with ECC
1662 * @mtd: MTD device structure
1663 * @to: offset to write to
1664 * @len: number of bytes to write
1665 * @retlen: pointer to variable to store the number of written bytes
1666 * @buf: the data to write
1668 * NAND write with ECC
1670 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
1671 size_t *retlen, const uint8_t *buf)
1673 struct nand_chip *chip = mtd->priv;
1676 /* Do not allow reads past end of device */
1677 if ((to + len) > mtd->size)
1682 nand_get_device(chip, mtd, FL_WRITING);
1684 chip->ops.len = len;
1685 chip->ops.datbuf = (uint8_t *)buf;
1686 chip->ops.oobbuf = NULL;
1688 ret = nand_do_write_ops(mtd, to, &chip->ops);
1690 *retlen = chip->ops.retlen;
1692 nand_release_device(mtd);
1698 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
1699 * @mtd: MTD device structure
1700 * @to: offset to write to
1701 * @ops: oob operation description structure
1703 * NAND write out-of-band
1705 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
1706 struct mtd_oob_ops *ops)
1708 int chipnr, page, status;
1709 struct nand_chip *chip = mtd->priv;
1711 DEBUG(MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n",
1712 (unsigned int)to, (int)ops->len);
1714 /* Do not allow write past end of page */
1715 if ((ops->ooboffs + ops->len) > mtd->oobsize) {
1716 DEBUG(MTD_DEBUG_LEVEL0, "nand_write_oob: "
1717 "Attempt to write past end of page\n");
1721 chipnr = (int)(to >> chip->chip_shift);
1722 chip->select_chip(mtd, chipnr);
1724 /* Shift to get page */
1725 page = (int)(to >> chip->page_shift);
1728 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
1729 * of my DiskOnChip 2000 test units) will clear the whole data page too
1730 * if we don't do this. I have no clue why, but I seem to have 'fixed'
1731 * it in the doc2000 driver in August 1999. dwmw2.
1733 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1735 /* Check, if it is write protected */
1736 if (nand_check_wp(mtd))
1739 /* Invalidate the page cache, if we write to the cached page */
1740 if (page == chip->pagebuf)
1743 memset(chip->oob_poi, 0xff, mtd->oobsize);
1744 nand_fill_oob(chip, ops->oobbuf, ops);
1745 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
1746 memset(chip->oob_poi, 0xff, mtd->oobsize);
1751 ops->retlen = ops->len;
1757 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
1758 * @mtd: MTD device structure
1759 * @to: offset to write to
1760 * @ops: oob operation description structure
1762 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
1763 struct mtd_oob_ops *ops)
1765 struct nand_chip *chip = mtd->priv;
1766 int ret = -ENOTSUPP;
1770 /* Do not allow writes past end of device */
1771 if ((to + ops->len) > mtd->size) {
1772 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: "
1773 "Attempt read beyond end of device\n");
1777 nand_get_device(chip, mtd, FL_WRITING);
1790 ret = nand_do_write_oob(mtd, to, ops);
1792 ret = nand_do_write_ops(mtd, to, ops);
1795 nand_release_device(mtd);
1800 * single_erease_cmd - [GENERIC] NAND standard block erase command function
1801 * @mtd: MTD device structure
1802 * @page: the page address of the block which will be erased
1804 * Standard erase command for NAND chips
1806 static void single_erase_cmd(struct mtd_info *mtd, int page)
1808 struct nand_chip *chip = mtd->priv;
1809 /* Send commands to erase a block */
1810 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
1811 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1815 * multi_erease_cmd - [GENERIC] AND specific block erase command function
1816 * @mtd: MTD device structure
1817 * @page: the page address of the block which will be erased
1819 * AND multi block erase command function
1820 * Erase 4 consecutive blocks
1822 static void multi_erase_cmd(struct mtd_info *mtd, int page)
1824 struct nand_chip *chip = mtd->priv;
1825 /* Send commands to erase a block */
1826 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
1827 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
1828 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
1829 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
1830 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1834 * nand_erase - [MTD Interface] erase block(s)
1835 * @mtd: MTD device structure
1836 * @instr: erase instruction
1838 * Erase one ore more blocks
1840 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
1842 return nand_erase_nand(mtd, instr, 0);
1845 #define BBT_PAGE_MASK 0xffffff3f
1847 * nand_erase_nand - [Internal] erase block(s)
1848 * @mtd: MTD device structure
1849 * @instr: erase instruction
1850 * @allowbbt: allow erasing the bbt area
1852 * Erase one ore more blocks
1854 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
1857 int page, len, status, pages_per_block, ret, chipnr;
1858 struct nand_chip *chip = mtd->priv;
1859 int rewrite_bbt[NAND_MAX_CHIPS]={0};
1860 unsigned int bbt_masked_page = 0xffffffff;
1862 DEBUG(MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%08x, len = %i\n",
1863 (unsigned int)instr->addr, (unsigned int)instr->len);
1865 /* Start address must align on block boundary */
1866 if (instr->addr & ((1 << chip->phys_erase_shift) - 1)) {
1867 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n");
1871 /* Length must align on block boundary */
1872 if (instr->len & ((1 << chip->phys_erase_shift) - 1)) {
1873 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
1874 "Length not block aligned\n");
1878 /* Do not allow erase past end of device */
1879 if ((instr->len + instr->addr) > mtd->size) {
1880 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
1881 "Erase past end of device\n");
1885 instr->fail_addr = 0xffffffff;
1887 /* Grab the lock and see if the device is available */
1888 nand_get_device(chip, mtd, FL_ERASING);
1890 /* Shift to get first page */
1891 page = (int)(instr->addr >> chip->page_shift);
1892 chipnr = (int)(instr->addr >> chip->chip_shift);
1894 /* Calculate pages in each block */
1895 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
1897 /* Select the NAND device */
1898 chip->select_chip(mtd, chipnr);
1900 /* Check, if it is write protected */
1901 if (nand_check_wp(mtd)) {
1902 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
1903 "Device is write protected!!!\n");
1904 instr->state = MTD_ERASE_FAILED;
1909 * If BBT requires refresh, set the BBT page mask to see if the BBT
1910 * should be rewritten. Otherwise the mask is set to 0xffffffff which
1911 * can not be matched. This is also done when the bbt is actually
1912 * erased to avoid recusrsive updates
1914 if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
1915 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
1917 /* Loop through the pages */
1920 instr->state = MTD_ERASING;
1924 * heck if we have a bad block, we do not erase bad blocks !
1926 if (nand_block_checkbad(mtd, ((loff_t) page) <<
1927 chip->page_shift, 0, allowbbt)) {
1928 printk(KERN_WARNING "nand_erase: attempt to erase a "
1929 "bad block at page 0x%08x\n", page);
1930 instr->state = MTD_ERASE_FAILED;
1935 * Invalidate the page cache, if we erase the block which
1936 * contains the current cached page
1938 if (page <= chip->pagebuf && chip->pagebuf <
1939 (page + pages_per_block))
1942 chip->erase_cmd(mtd, page & chip->pagemask);
1944 status = chip->waitfunc(mtd, chip);
1947 * See if operation failed and additional status checks are
1950 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1951 status = chip->errstat(mtd, chip, FL_ERASING,
1954 /* See if block erase succeeded */
1955 if (status & NAND_STATUS_FAIL) {
1956 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
1957 "Failed erase, page 0x%08x\n", page);
1958 instr->state = MTD_ERASE_FAILED;
1959 instr->fail_addr = (page << chip->page_shift);
1964 * If BBT requires refresh, set the BBT rewrite flag to the
1967 if (bbt_masked_page != 0xffffffff &&
1968 (page & BBT_PAGE_MASK) == bbt_masked_page)
1969 rewrite_bbt[chipnr] = (page << chip->page_shift);
1971 /* Increment page address and decrement length */
1972 len -= (1 << chip->phys_erase_shift);
1973 page += pages_per_block;
1975 /* Check, if we cross a chip boundary */
1976 if (len && !(page & chip->pagemask)) {
1978 chip->select_chip(mtd, -1);
1979 chip->select_chip(mtd, chipnr);
1982 * If BBT requires refresh and BBT-PERCHIP, set the BBT
1983 * page mask to see if this BBT should be rewritten
1985 if (bbt_masked_page != 0xffffffff &&
1986 (chip->bbt_td->options & NAND_BBT_PERCHIP))
1987 bbt_masked_page = chip->bbt_td->pages[chipnr] &
1991 instr->state = MTD_ERASE_DONE;
1995 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
1996 /* Do call back function */
1998 mtd_erase_callback(instr);
2000 /* Deselect and wake up anyone waiting on the device */
2001 nand_release_device(mtd);
2004 * If BBT requires refresh and erase was successful, rewrite any
2005 * selected bad block tables
2007 if (bbt_masked_page == 0xffffffff || ret)
2010 for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2011 if (!rewrite_bbt[chipnr])
2013 /* update the BBT for chip */
2014 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase_nand: nand_update_bbt "
2015 "(%d:0x%0x 0x%0x)\n", chipnr, rewrite_bbt[chipnr],
2016 chip->bbt_td->pages[chipnr]);
2017 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2020 /* Return more or less happy */
2025 * nand_sync - [MTD Interface] sync
2026 * @mtd: MTD device structure
2028 * Sync is actually a wait for chip ready function
2030 static void nand_sync(struct mtd_info *mtd)
2032 struct nand_chip *chip = mtd->priv;
2034 DEBUG(MTD_DEBUG_LEVEL3, "nand_sync: called\n");
2036 /* Grab the lock and see if the device is available */
2037 nand_get_device(chip, mtd, FL_SYNCING);
2038 /* Release it and go back */
2039 nand_release_device(mtd);
2043 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2044 * @mtd: MTD device structure
2045 * @offs: offset relative to mtd start
2047 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2049 /* Check for invalid offset */
2050 if (offs > mtd->size)
2053 return nand_block_checkbad(mtd, offs, 1, 0);
2057 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2058 * @mtd: MTD device structure
2059 * @ofs: offset relative to mtd start
2061 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2063 struct nand_chip *chip = mtd->priv;
2066 if ((ret = nand_block_isbad(mtd, ofs))) {
2067 /* If it was bad already, return success and do nothing. */
2073 return chip->block_markbad(mtd, ofs);
2077 * nand_suspend - [MTD Interface] Suspend the NAND flash
2078 * @mtd: MTD device structure
2080 static int nand_suspend(struct mtd_info *mtd)
2082 struct nand_chip *chip = mtd->priv;
2084 return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
2088 * nand_resume - [MTD Interface] Resume the NAND flash
2089 * @mtd: MTD device structure
2091 static void nand_resume(struct mtd_info *mtd)
2093 struct nand_chip *chip = mtd->priv;
2095 if (chip->state == FL_PM_SUSPENDED)
2096 nand_release_device(mtd);
2098 printk(KERN_ERR "nand_resume() called for a chip which is not "
2099 "in suspended state\n");
2103 * Set default functions
2105 static void nand_set_defaults(struct nand_chip *chip, int busw)
2107 /* check for proper chip_delay setup, set 20us if not */
2108 if (!chip->chip_delay)
2109 chip->chip_delay = 20;
2111 /* check, if a user supplied command function given */
2112 if (chip->cmdfunc == NULL)
2113 chip->cmdfunc = nand_command;
2115 /* check, if a user supplied wait function given */
2116 if (chip->waitfunc == NULL)
2117 chip->waitfunc = nand_wait;
2119 if (!chip->select_chip)
2120 chip->select_chip = nand_select_chip;
2121 if (!chip->read_byte)
2122 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2123 if (!chip->read_word)
2124 chip->read_word = nand_read_word;
2125 if (!chip->block_bad)
2126 chip->block_bad = nand_block_bad;
2127 if (!chip->block_markbad)
2128 chip->block_markbad = nand_default_block_markbad;
2129 if (!chip->write_buf)
2130 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2131 if (!chip->read_buf)
2132 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2133 if (!chip->verify_buf)
2134 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2135 if (!chip->scan_bbt)
2136 chip->scan_bbt = nand_default_bbt;
2138 if (!chip->controller) {
2139 chip->controller = &chip->hwcontrol;
2140 spin_lock_init(&chip->controller->lock);
2141 init_waitqueue_head(&chip->controller->wq);
2147 * Get the flash and manufacturer id and lookup if the type is supported
2149 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2150 struct nand_chip *chip,
2151 int busw, int *maf_id)
2153 struct nand_flash_dev *type = NULL;
2154 int i, dev_id, maf_idx;
2156 /* Select the device */
2157 chip->select_chip(mtd, 0);
2159 /* Send the command for reading device ID */
2160 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2162 /* Read manufacturer and device IDs */
2163 *maf_id = chip->read_byte(mtd);
2164 dev_id = chip->read_byte(mtd);
2166 /* Lookup the flash id */
2167 for (i = 0; nand_flash_ids[i].name != NULL; i++) {
2168 if (dev_id == nand_flash_ids[i].id) {
2169 type = &nand_flash_ids[i];
2175 return ERR_PTR(-ENODEV);
2178 mtd->name = type->name;
2180 chip->chipsize = type->chipsize << 20;
2182 /* Newer devices have all the information in additional id bytes */
2183 if (!type->pagesize) {
2185 /* The 3rd id byte contains non relevant data ATM */
2186 extid = chip->read_byte(mtd);
2187 /* The 4th id byte is the important one */
2188 extid = chip->read_byte(mtd);
2190 mtd->writesize = 1024 << (extid & 0x3);
2193 mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
2195 /* Calc blocksize. Blocksize is multiples of 64KiB */
2196 mtd->erasesize = (64 * 1024) << (extid & 0x03);
2198 /* Get buswidth information */
2199 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
2203 * Old devices have chip data hardcoded in the device id table
2205 mtd->erasesize = type->erasesize;
2206 mtd->writesize = type->pagesize;
2207 mtd->oobsize = mtd->writesize / 32;
2208 busw = type->options & NAND_BUSWIDTH_16;
2211 /* Try to identify manufacturer */
2212 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
2213 if (nand_manuf_ids[maf_idx].id == *maf_id)
2218 * Check, if buswidth is correct. Hardware drivers should set
2221 if (busw != (chip->options & NAND_BUSWIDTH_16)) {
2222 printk(KERN_INFO "NAND device: Manufacturer ID:"
2223 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
2224 dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
2225 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
2226 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
2228 return ERR_PTR(-EINVAL);
2231 /* Calculate the address shift from the page size */
2232 chip->page_shift = ffs(mtd->writesize) - 1;
2233 /* Convert chipsize to number of pages per chip -1. */
2234 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
2236 chip->bbt_erase_shift = chip->phys_erase_shift =
2237 ffs(mtd->erasesize) - 1;
2238 chip->chip_shift = ffs(chip->chipsize) - 1;
2240 /* Set the bad block position */
2241 chip->badblockpos = mtd->writesize > 512 ?
2242 NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
2244 /* Get chip options, preserve non chip based options */
2245 chip->options &= ~NAND_CHIPOPTIONS_MSK;
2246 chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
2249 * Set chip as a default. Board drivers can override it, if necessary
2251 chip->options |= NAND_NO_AUTOINCR;
2253 /* Check if chip is a not a samsung device. Do not clear the
2254 * options for chips which are not having an extended id.
2256 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
2257 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
2259 /* Check for AND chips with 4 page planes */
2260 if (chip->options & NAND_4PAGE_ARRAY)
2261 chip->erase_cmd = multi_erase_cmd;
2263 chip->erase_cmd = single_erase_cmd;
2265 /* Do not replace user supplied command function ! */
2266 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
2267 chip->cmdfunc = nand_command_lp;
2269 printk(KERN_INFO "NAND device: Manufacturer ID:"
2270 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id,
2271 nand_manuf_ids[maf_idx].name, type->name);
2277 * nand_scan_ident - [NAND Interface] Scan for the NAND device
2278 * @mtd: MTD device structure
2279 * @maxchips: Number of chips to scan for
2281 * This is the first phase of the normal nand_scan() function. It
2282 * reads the flash ID and sets up MTD fields accordingly.
2284 * The mtd->owner field must be set to the module of the caller.
2286 int nand_scan_ident(struct mtd_info *mtd, int maxchips)
2288 int i, busw, nand_maf_id;
2289 struct nand_chip *chip = mtd->priv;
2290 struct nand_flash_dev *type;
2292 /* Get buswidth to select the correct functions */
2293 busw = chip->options & NAND_BUSWIDTH_16;
2294 /* Set the default functions */
2295 nand_set_defaults(chip, busw);
2297 /* Read the flash type */
2298 type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id);
2301 printk(KERN_WARNING "No NAND device found!!!\n");
2302 chip->select_chip(mtd, -1);
2303 return PTR_ERR(type);
2306 /* Check for a chip array */
2307 for (i = 1; i < maxchips; i++) {
2308 chip->select_chip(mtd, i);
2309 /* Send the command for reading device ID */
2310 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2311 /* Read manufacturer and device IDs */
2312 if (nand_maf_id != chip->read_byte(mtd) ||
2313 type->id != chip->read_byte(mtd))
2317 printk(KERN_INFO "%d NAND chips detected\n", i);
2319 /* Store the number of chips and calc total size for mtd */
2321 mtd->size = i * chip->chipsize;
2328 * nand_scan_tail - [NAND Interface] Scan for the NAND device
2329 * @mtd: MTD device structure
2330 * @maxchips: Number of chips to scan for
2332 * This is the second phase of the normal nand_scan() function. It
2333 * fills out all the uninitialized function pointers with the defaults
2334 * and scans for a bad block table if appropriate.
2336 int nand_scan_tail(struct mtd_info *mtd)
2339 struct nand_chip *chip = mtd->priv;
2341 if (!(chip->options & NAND_OWN_BUFFERS))
2342 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
2346 /* Set the internal oob buffer location, just after the page data */
2347 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
2350 * If no default placement scheme is given, select an appropriate one
2352 if (!chip->ecc.layout) {
2353 switch (mtd->oobsize) {
2355 chip->ecc.layout = &nand_oob_8;
2358 chip->ecc.layout = &nand_oob_16;
2361 chip->ecc.layout = &nand_oob_64;
2364 printk(KERN_WARNING "No oob scheme defined for "
2365 "oobsize %d\n", mtd->oobsize);
2370 if (!chip->write_page)
2371 chip->write_page = nand_write_page;
2374 * check ECC mode, default to software if 3byte/512byte hardware ECC is
2375 * selected and we have 256 byte pagesize fallback to software ECC
2377 if (!chip->ecc.read_page_raw)
2378 chip->ecc.read_page_raw = nand_read_page_raw;
2379 if (!chip->ecc.write_page_raw)
2380 chip->ecc.write_page_raw = nand_write_page_raw;
2382 switch (chip->ecc.mode) {
2384 /* Use standard hwecc read page function ? */
2385 if (!chip->ecc.read_page)
2386 chip->ecc.read_page = nand_read_page_hwecc;
2387 if (!chip->ecc.write_page)
2388 chip->ecc.write_page = nand_write_page_hwecc;
2389 if (!chip->ecc.read_oob)
2390 chip->ecc.read_oob = nand_read_oob_std;
2391 if (!chip->ecc.write_oob)
2392 chip->ecc.write_oob = nand_write_oob_std;
2394 case NAND_ECC_HW_SYNDROME:
2395 if (!chip->ecc.calculate || !chip->ecc.correct ||
2397 printk(KERN_WARNING "No ECC functions supplied, "
2398 "Hardware ECC not possible\n");
2401 /* Use standard syndrome read/write page function ? */
2402 if (!chip->ecc.read_page)
2403 chip->ecc.read_page = nand_read_page_syndrome;
2404 if (!chip->ecc.write_page)
2405 chip->ecc.write_page = nand_write_page_syndrome;
2406 if (!chip->ecc.read_oob)
2407 chip->ecc.read_oob = nand_read_oob_syndrome;
2408 if (!chip->ecc.write_oob)
2409 chip->ecc.write_oob = nand_write_oob_syndrome;
2411 if (mtd->writesize >= chip->ecc.size)
2413 printk(KERN_WARNING "%d byte HW ECC not possible on "
2414 "%d byte page size, fallback to SW ECC\n",
2415 chip->ecc.size, mtd->writesize);
2416 chip->ecc.mode = NAND_ECC_SOFT;
2419 chip->ecc.calculate = nand_calculate_ecc;
2420 chip->ecc.correct = nand_correct_data;
2421 chip->ecc.read_page = nand_read_page_swecc;
2422 chip->ecc.write_page = nand_write_page_swecc;
2423 chip->ecc.read_oob = nand_read_oob_std;
2424 chip->ecc.write_oob = nand_write_oob_std;
2425 chip->ecc.size = 256;
2426 chip->ecc.bytes = 3;
2430 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
2431 "This is not recommended !!\n");
2432 chip->ecc.read_page = nand_read_page_raw;
2433 chip->ecc.write_page = nand_write_page_raw;
2434 chip->ecc.read_oob = nand_read_oob_std;
2435 chip->ecc.write_oob = nand_write_oob_std;
2436 chip->ecc.size = mtd->writesize;
2437 chip->ecc.bytes = 0;
2441 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
2447 * The number of bytes available for a client to place data into
2448 * the out of band area
2450 chip->ecc.layout->oobavail = 0;
2451 for (i = 0; chip->ecc.layout->oobfree[i].length; i++)
2452 chip->ecc.layout->oobavail +=
2453 chip->ecc.layout->oobfree[i].length;
2456 * Set the number of read / write steps for one page depending on ECC
2459 chip->ecc.steps = mtd->writesize / chip->ecc.size;
2460 if(chip->ecc.steps * chip->ecc.size != mtd->writesize) {
2461 printk(KERN_WARNING "Invalid ecc parameters\n");
2464 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
2466 /* Initialize state */
2467 chip->state = FL_READY;
2469 /* De-select the device */
2470 chip->select_chip(mtd, -1);
2472 /* Invalidate the pagebuffer reference */
2475 /* Fill in remaining MTD driver data */
2476 mtd->type = MTD_NANDFLASH;
2477 mtd->flags = MTD_CAP_NANDFLASH;
2478 mtd->ecctype = MTD_ECC_SW;
2479 mtd->erase = nand_erase;
2481 mtd->unpoint = NULL;
2482 mtd->read = nand_read;
2483 mtd->write = nand_write;
2484 mtd->read_oob = nand_read_oob;
2485 mtd->write_oob = nand_write_oob;
2486 mtd->sync = nand_sync;
2489 mtd->suspend = nand_suspend;
2490 mtd->resume = nand_resume;
2491 mtd->block_isbad = nand_block_isbad;
2492 mtd->block_markbad = nand_block_markbad;
2494 /* propagate ecc.layout to mtd_info */
2495 mtd->ecclayout = chip->ecc.layout;
2497 /* Check, if we should skip the bad block table scan */
2498 if (chip->options & NAND_SKIP_BBTSCAN)
2501 /* Build bad block table */
2502 return chip->scan_bbt(mtd);
2505 /* module_text_address() isn't exported, and it's mostly a pointless
2506 test if this is a module _anyway_ -- they'd have to try _really_ hard
2507 to call us from in-kernel code if the core NAND support is modular. */
2509 #define caller_is_module() (1)
2511 #define caller_is_module() \
2512 module_text_address((unsigned long)__builtin_return_address(0))
2516 * nand_scan - [NAND Interface] Scan for the NAND device
2517 * @mtd: MTD device structure
2518 * @maxchips: Number of chips to scan for
2520 * This fills out all the uninitialized function pointers
2521 * with the defaults.
2522 * The flash ID is read and the mtd/chip structures are
2523 * filled with the appropriate values.
2524 * The mtd->owner field must be set to the module of the caller
2527 int nand_scan(struct mtd_info *mtd, int maxchips)
2531 /* Many callers got this wrong, so check for it for a while... */
2532 if (!mtd->owner && caller_is_module()) {
2533 printk(KERN_CRIT "nand_scan() called with NULL mtd->owner!\n");
2537 ret = nand_scan_ident(mtd, maxchips);
2539 ret = nand_scan_tail(mtd);
2544 * nand_release - [NAND Interface] Free resources held by the NAND device
2545 * @mtd: MTD device structure
2547 void nand_release(struct mtd_info *mtd)
2549 struct nand_chip *chip = mtd->priv;
2551 #ifdef CONFIG_MTD_PARTITIONS
2552 /* Deregister partitions */
2553 del_mtd_partitions(mtd);
2555 /* Deregister the device */
2556 del_mtd_device(mtd);
2558 /* Free bad block table memory */
2560 if (!(chip->options & NAND_OWN_BUFFERS))
2561 kfree(chip->buffers);
2564 EXPORT_SYMBOL_GPL(nand_scan);
2565 EXPORT_SYMBOL_GPL(nand_scan_ident);
2566 EXPORT_SYMBOL_GPL(nand_scan_tail);
2567 EXPORT_SYMBOL_GPL(nand_release);
2569 static int __init nand_base_init(void)
2571 led_trigger_register_simple("nand-disk", &nand_led_trigger);
2575 static void __exit nand_base_exit(void)
2577 led_trigger_unregister_simple(nand_led_trigger);
2580 module_init(nand_base_init);
2581 module_exit(nand_base_exit);
2583 MODULE_LICENSE("GPL");
2584 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>, Thomas Gleixner <tglx@linutronix.de>");
2585 MODULE_DESCRIPTION("Generic NAND flash driver code");