drivers/net/forcedeth.c

   1 /*
   2  * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
   3  *
   4  * Note: This driver is a cleanroom reimplementation based on reverse
   5  *      engineered documentation written by Carl-Daniel Hailfinger
   6  *      and Andrew de Quincey. It's neither supported nor endorsed
   7  *      by NVIDIA Corp. Use at your own risk.
   8  *
   9  * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
  10  * trademarks of NVIDIA Corporation in the United States and other
  11  * countries.
  12  *
  13  * Copyright (C) 2003,4 Manfred Spraul
  14  * Copyright (C) 2004 Andrew de Quincey (wol support)
  15  * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
  16  *              IRQ rate fixes, bigendian fixes, cleanups, verification)
  17  * Copyright (c) 2004 NVIDIA Corporation
  18  *
  19  * This program is free software; you can redistribute it and/or modify
  20  * it under the terms of the GNU General Public License as published by
  21  * the Free Software Foundation; either version 2 of the License, or
  22  * (at your option) any later version.
  23  *
  24  * This program is distributed in the hope that it will be useful,
  25  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  26  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  27  * GNU General Public License for more details.
  28  *
  29  * You should have received a copy of the GNU General Public License
  30  * along with this program; if not, write to the Free Software
  31  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  32  *
  33  * Changelog:
  34  *      0.01: 05 Oct 2003: First release that compiles without warnings.
  35  *      0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
  36  *                         Check all PCI BARs for the register window.
  37  *                         udelay added to mii_rw.
  38  *      0.03: 06 Oct 2003: Initialize dev->irq.
  39  *      0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
  40  *      0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
  41  *      0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
  42  *                         irq mask updated
  43  *      0.07: 14 Oct 2003: Further irq mask updates.
  44  *      0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
  45  *                         added into irq handler, NULL check for drain_ring.
  46  *      0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
  47  *                         requested interrupt sources.
  48  *      0.10: 20 Oct 2003: First cleanup for release.
  49  *      0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
  50  *                         MAC Address init fix, set_multicast cleanup.
  51  *      0.12: 23 Oct 2003: Cleanups for release.
  52  *      0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
  53  *                         Set link speed correctly. start rx before starting
  54  *                         tx (nv_start_rx sets the link speed).
  55  *      0.14: 25 Oct 2003: Nic dependant irq mask.
  56  *      0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
  57  *                         open.
  58  *      0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
  59  *                         increased to 1628 bytes.
  60  *      0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
  61  *                         the tx length.
  62  *      0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
  63  *      0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
  64  *                         addresses, really stop rx if already running
  65  *                         in nv_start_rx, clean up a bit.
  66  *      0.20: 07 Dec 2003: alloc fixes
  67  *      0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
  68  *      0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
  69  *                         on close.
  70  *      0.23: 26 Jan 2004: various small cleanups
  71  *      0.24: 27 Feb 2004: make driver even less anonymous in backtraces
  72  *      0.25: 09 Mar 2004: wol support
  73  *      0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
  74  *      0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
  75  *                         added CK804/MCP04 device IDs, code fixes
  76  *                         for registers, link status and other minor fixes.
  77  *      0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
  78  *      0.29: 31 Aug 2004: Add backup timer for link change notification.
  79  *      0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
  80  *                         into nv_close, otherwise reenabling for wol can
  81  *                         cause DMA to kfree'd memory.
  82  *      0.31: 14 Nov 2004: ethtool support for getting/setting link
  83  *                         capabilities.
  84  *      0.32: 16 Apr 2005: RX_ERROR4 handling added.
  85  *      0.33: 16 May 2005: Support for MCP51 added.
  86  *      0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
  87  *      0.35: 26 Jun 2005: Support for MCP55 added.
  88  *      0.36: 28 Jun 2005: Add jumbo frame support.
  89  *      0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list
  90  *      0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of
  91  *                         per-packet flags.
  92  *
  93  * Known bugs:
  94  * We suspect that on some hardware no TX done interrupts are generated.
  95  * This means recovery from netif_stop_queue only happens if the hw timer
  96  * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
  97  * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
  98  * If your hardware reliably generates tx done interrupts, then you can remove
  99  * DEV_NEED_TIMERIRQ from the driver_data flags.
 100  * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
 101  * superfluous timer interrupts from the nic.
 102  */
 103 #define FORCEDETH_VERSION               "0.38"
 104 #define DRV_NAME                        "forcedeth"
 105
 106 #include <linux/module.h>
 107 #include <linux/types.h>
 108 #include <linux/pci.h>
 109 #include <linux/interrupt.h>
 110 #include <linux/netdevice.h>
 111 #include <linux/etherdevice.h>
 112 #include <linux/delay.h>
 113 #include <linux/spinlock.h>
 114 #include <linux/ethtool.h>
 115 #include <linux/timer.h>
 116 #include <linux/skbuff.h>
 117 #include <linux/mii.h>
 118 #include <linux/random.h>
 119 #include <linux/init.h>
 120 #include <linux/if_vlan.h>
 121
 122 #include <asm/irq.h>
 123 #include <asm/io.h>
 124 #include <asm/uaccess.h>
 125 #include <asm/system.h>
 126
 127 #if 0
 128 #define dprintk                 printk
 129 #else
 130 #define dprintk(x...)           do { } while (0)
 131 #endif
 132
 133
 134 /*
 135  * Hardware access:
 136  */
 137
 138 #define DEV_NEED_TIMERIRQ       0x0001  /* set the timer irq flag in the irq mask */
 139 #define DEV_NEED_LINKTIMER      0x0002  /* poll link settings. Relies on the timer irq */
 140 #define DEV_HAS_LARGEDESC       0x0004  /* device supports jumbo frames and needs packet format 2 */
 141
 142 enum {
 143         NvRegIrqStatus = 0x000,
 144 #define NVREG_IRQSTAT_MIIEVENT  0x040
 145 #define NVREG_IRQSTAT_MASK              0x1ff
 146         NvRegIrqMask = 0x004,
 147 #define NVREG_IRQ_RX_ERROR              0x0001
 148 #define NVREG_IRQ_RX                    0x0002
 149 #define NVREG_IRQ_RX_NOBUF              0x0004
 150 #define NVREG_IRQ_TX_ERR                0x0008
 151 #define NVREG_IRQ_TX_OK                 0x0010
 152 #define NVREG_IRQ_TIMER                 0x0020
 153 #define NVREG_IRQ_LINK                  0x0040
 154 #define NVREG_IRQ_TX_ERROR              0x0080
 155 #define NVREG_IRQ_TX1                   0x0100
 156 #define NVREG_IRQMASK_WANTED            0x00df
 157
 158 #define NVREG_IRQ_UNKNOWN       (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
 159                                         NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_TX_ERROR| \
 160                                         NVREG_IRQ_TX1))
 161
 162         NvRegUnknownSetupReg6 = 0x008,
 163 #define NVREG_UNKSETUP6_VAL             3
 164
 165 /*
 166  * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
 167  * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
 168  */
 169         NvRegPollingInterval = 0x00c,
 170 #define NVREG_POLL_DEFAULT      970
 171         NvRegMisc1 = 0x080,
 172 #define NVREG_MISC1_HD          0x02
 173 #define NVREG_MISC1_FORCE       0x3b0f3c
 174
 175         NvRegTransmitterControl = 0x084,
 176 #define NVREG_XMITCTL_START     0x01
 177         NvRegTransmitterStatus = 0x088,
 178 #define NVREG_XMITSTAT_BUSY     0x01
 179
 180         NvRegPacketFilterFlags = 0x8c,
 181 #define NVREG_PFF_ALWAYS        0x7F0008
 182 #define NVREG_PFF_PROMISC       0x80
 183 #define NVREG_PFF_MYADDR        0x20
 184
 185         NvRegOffloadConfig = 0x90,
 186 #define NVREG_OFFLOAD_HOMEPHY   0x601
 187 #define NVREG_OFFLOAD_NORMAL    RX_NIC_BUFSIZE
 188         NvRegReceiverControl = 0x094,
 189 #define NVREG_RCVCTL_START      0x01
 190         NvRegReceiverStatus = 0x98,
 191 #define NVREG_RCVSTAT_BUSY      0x01
 192
 193         NvRegRandomSeed = 0x9c,
 194 #define NVREG_RNDSEED_MASK      0x00ff
 195 #define NVREG_RNDSEED_FORCE     0x7f00
 196 #define NVREG_RNDSEED_FORCE2    0x2d00
 197 #define NVREG_RNDSEED_FORCE3    0x7400
 198
 199         NvRegUnknownSetupReg1 = 0xA0,
 200 #define NVREG_UNKSETUP1_VAL     0x16070f
 201         NvRegUnknownSetupReg2 = 0xA4,
 202 #define NVREG_UNKSETUP2_VAL     0x16
 203         NvRegMacAddrA = 0xA8,
 204         NvRegMacAddrB = 0xAC,
 205         NvRegMulticastAddrA = 0xB0,
 206 #define NVREG_MCASTADDRA_FORCE  0x01
 207         NvRegMulticastAddrB = 0xB4,
 208         NvRegMulticastMaskA = 0xB8,
 209         NvRegMulticastMaskB = 0xBC,
 210
 211         NvRegPhyInterface = 0xC0,
 212 #define PHY_RGMII               0x10000000
 213
 214         NvRegTxRingPhysAddr = 0x100,
 215         NvRegRxRingPhysAddr = 0x104,
 216         NvRegRingSizes = 0x108,
 217 #define NVREG_RINGSZ_TXSHIFT 0
 218 #define NVREG_RINGSZ_RXSHIFT 16
 219         NvRegUnknownTransmitterReg = 0x10c,
 220         NvRegLinkSpeed = 0x110,
 221 #define NVREG_LINKSPEED_FORCE 0x10000
 222 #define NVREG_LINKSPEED_10      1000
 223 #define NVREG_LINKSPEED_100     100
 224 #define NVREG_LINKSPEED_1000    50
 225 #define NVREG_LINKSPEED_MASK    (0xFFF)
 226         NvRegUnknownSetupReg5 = 0x130,
 227 #define NVREG_UNKSETUP5_BIT31   (1<<31)
 228         NvRegUnknownSetupReg3 = 0x13c,
 229 #define NVREG_UNKSETUP3_VAL1    0x200010
 230         NvRegTxRxControl = 0x144,
 231 #define NVREG_TXRXCTL_KICK      0x0001
 232 #define NVREG_TXRXCTL_BIT1      0x0002
 233 #define NVREG_TXRXCTL_BIT2      0x0004
 234 #define NVREG_TXRXCTL_IDLE      0x0008
 235 #define NVREG_TXRXCTL_RESET     0x0010
 236 #define NVREG_TXRXCTL_RXCHECK   0x0400
 237         NvRegMIIStatus = 0x180,
 238 #define NVREG_MIISTAT_ERROR             0x0001
 239 #define NVREG_MIISTAT_LINKCHANGE        0x0008
 240 #define NVREG_MIISTAT_MASK              0x000f
 241 #define NVREG_MIISTAT_MASK2             0x000f
 242         NvRegUnknownSetupReg4 = 0x184,
 243 #define NVREG_UNKSETUP4_VAL     8
 244
 245         NvRegAdapterControl = 0x188,
 246 #define NVREG_ADAPTCTL_START    0x02
 247 #define NVREG_ADAPTCTL_LINKUP   0x04
 248 #define NVREG_ADAPTCTL_PHYVALID 0x40000
 249 #define NVREG_ADAPTCTL_RUNNING  0x100000
 250 #define NVREG_ADAPTCTL_PHYSHIFT 24
 251         NvRegMIISpeed = 0x18c,
 252 #define NVREG_MIISPEED_BIT8     (1<<8)
 253 #define NVREG_MIIDELAY  5
 254         NvRegMIIControl = 0x190,
 255 #define NVREG_MIICTL_INUSE      0x08000
 256 #define NVREG_MIICTL_WRITE      0x00400
 257 #define NVREG_MIICTL_ADDRSHIFT  5
 258         NvRegMIIData = 0x194,
 259         NvRegWakeUpFlags = 0x200,
 260 #define NVREG_WAKEUPFLAGS_VAL           0x7770
 261 #define NVREG_WAKEUPFLAGS_BUSYSHIFT     24
 262 #define NVREG_WAKEUPFLAGS_ENABLESHIFT   16
 263 #define NVREG_WAKEUPFLAGS_D3SHIFT       12
 264 #define NVREG_WAKEUPFLAGS_D2SHIFT       8
 265 #define NVREG_WAKEUPFLAGS_D1SHIFT       4
 266 #define NVREG_WAKEUPFLAGS_D0SHIFT       0
 267 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT         0x01
 268 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT      0x02
 269 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE     0x04
 270 #define NVREG_WAKEUPFLAGS_ENABLE        0x1111
 271
 272         NvRegPatternCRC = 0x204,
 273         NvRegPatternMask = 0x208,
 274         NvRegPowerCap = 0x268,
 275 #define NVREG_POWERCAP_D3SUPP   (1<<30)
 276 #define NVREG_POWERCAP_D2SUPP   (1<<26)
 277 #define NVREG_POWERCAP_D1SUPP   (1<<25)
 278         NvRegPowerState = 0x26c,
 279 #define NVREG_POWERSTATE_POWEREDUP      0x8000
 280 #define NVREG_POWERSTATE_VALID          0x0100
 281 #define NVREG_POWERSTATE_MASK           0x0003
 282 #define NVREG_POWERSTATE_D0             0x0000
 283 #define NVREG_POWERSTATE_D1             0x0001
 284 #define NVREG_POWERSTATE_D2             0x0002
 285 #define NVREG_POWERSTATE_D3             0x0003
 286 };
 287
 288 /* Big endian: should work, but is untested */
 289 struct ring_desc {
 290         u32 PacketBuffer;
 291         u32 FlagLen;
 292 };
 293
 294 #define FLAG_MASK_V1 0xffff0000
 295 #define FLAG_MASK_V2 0xffffc000
 296 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
 297 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
 298
 299 #define NV_TX_LASTPACKET        (1<<16)
 300 #define NV_TX_RETRYERROR        (1<<19)
 301 #define NV_TX_FORCED_INTERRUPT  (1<<24)
 302 #define NV_TX_DEFERRED          (1<<26)
 303 #define NV_TX_CARRIERLOST       (1<<27)
 304 #define NV_TX_LATECOLLISION     (1<<28)
 305 #define NV_TX_UNDERFLOW         (1<<29)
 306 #define NV_TX_ERROR             (1<<30)
 307 #define NV_TX_VALID             (1<<31)
 308
 309 #define NV_TX2_LASTPACKET       (1<<29)
 310 #define NV_TX2_RETRYERROR       (1<<18)
 311 #define NV_TX2_FORCED_INTERRUPT (1<<30)
 312 #define NV_TX2_DEFERRED         (1<<25)
 313 #define NV_TX2_CARRIERLOST      (1<<26)
 314 #define NV_TX2_LATECOLLISION    (1<<27)
 315 #define NV_TX2_UNDERFLOW        (1<<28)
 316 /* error and valid are the same for both */
 317 #define NV_TX2_ERROR            (1<<30)
 318 #define NV_TX2_VALID            (1<<31)
 319
 320 #define NV_RX_DESCRIPTORVALID   (1<<16)
 321 #define NV_RX_MISSEDFRAME       (1<<17)
 322 #define NV_RX_SUBSTRACT1        (1<<18)
 323 #define NV_RX_ERROR1            (1<<23)
 324 #define NV_RX_ERROR2            (1<<24)
 325 #define NV_RX_ERROR3            (1<<25)
 326 #define NV_RX_ERROR4            (1<<26)
 327 #define NV_RX_CRCERR            (1<<27)
 328 #define NV_RX_OVERFLOW          (1<<28)
 329 #define NV_RX_FRAMINGERR        (1<<29)
 330 #define NV_RX_ERROR             (1<<30)
 331 #define NV_RX_AVAIL             (1<<31)
 332
 333 #define NV_RX2_CHECKSUMMASK     (0x1C000000)
 334 #define NV_RX2_CHECKSUMOK1      (0x10000000)
 335 #define NV_RX2_CHECKSUMOK2      (0x14000000)
 336 #define NV_RX2_CHECKSUMOK3      (0x18000000)
 337 #define NV_RX2_DESCRIPTORVALID  (1<<29)
 338 #define NV_RX2_SUBSTRACT1       (1<<25)
 339 #define NV_RX2_ERROR1           (1<<18)
 340 #define NV_RX2_ERROR2           (1<<19)
 341 #define NV_RX2_ERROR3           (1<<20)
 342 #define NV_RX2_ERROR4           (1<<21)
 343 #define NV_RX2_CRCERR           (1<<22)
 344 #define NV_RX2_OVERFLOW         (1<<23)
 345 #define NV_RX2_FRAMINGERR       (1<<24)
 346 /* error and avail are the same for both */
 347 #define NV_RX2_ERROR            (1<<30)
 348 #define NV_RX2_AVAIL            (1<<31)
 349
 350 /* Miscelaneous hardware related defines: */
 351 #define NV_PCI_REGSZ            0x270
 352
 353 /* various timeout delays: all in usec */
 354 #define NV_TXRX_RESET_DELAY     4
 355 #define NV_TXSTOP_DELAY1        10
 356 #define NV_TXSTOP_DELAY1MAX     500000
 357 #define NV_TXSTOP_DELAY2        100
 358 #define NV_RXSTOP_DELAY1        10
 359 #define NV_RXSTOP_DELAY1MAX     500000
 360 #define NV_RXSTOP_DELAY2        100
 361 #define NV_SETUP5_DELAY         5
 362 #define NV_SETUP5_DELAYMAX      50000
 363 #define NV_POWERUP_DELAY        5
 364 #define NV_POWERUP_DELAYMAX     5000
 365 #define NV_MIIBUSY_DELAY        50
 366 #define NV_MIIPHY_DELAY 10
 367 #define NV_MIIPHY_DELAYMAX      10000
 368
 369 #define NV_WAKEUPPATTERNS       5
 370 #define NV_WAKEUPMASKENTRIES    4
 371
 372 /* General driver defaults */
 373 #define NV_WATCHDOG_TIMEO       (5*HZ)
 374
 375 #define RX_RING         128
 376 #define TX_RING         64
 377 /*
 378  * If your nic mysteriously hangs then try to reduce the limits
 379  * to 1/0: It might be required to set NV_TX_LASTPACKET in the
 380  * last valid ring entry. But this would be impossible to
 381  * implement - probably a disassembly error.
 382  */
 383 #define TX_LIMIT_STOP   63
 384 #define TX_LIMIT_START  62
 385
 386 /* rx/tx mac addr + type + vlan + align + slack*/
 387 #define NV_RX_HEADERS           (64)
 388 /* even more slack. */
 389 #define NV_RX_ALLOC_PAD         (64)
 390
 391 /* maximum mtu size */
 392 #define NV_PKTLIMIT_1   ETH_DATA_LEN    /* hard limit not known */
 393 #define NV_PKTLIMIT_2   9100    /* Actual limit according to NVidia: 9202 */
 394
 395 #define OOM_REFILL      (1+HZ/20)
 396 #define POLL_WAIT       (1+HZ/100)
 397 #define LINK_TIMEOUT    (3*HZ)
 398
 399 /*
 400  * desc_ver values:
 401  * This field has two purposes:
 402  * - Newer nics uses a different ring layout. The layout is selected by
 403  *   comparing np->desc_ver with DESC_VER_xy.
 404  * - It contains bits that are forced on when writing to NvRegTxRxControl.
 405  */
 406 #define DESC_VER_1      0x0
 407 #define DESC_VER_2      (0x02100|NVREG_TXRXCTL_RXCHECK)
 408
 409 /* PHY defines */
 410 #define PHY_OUI_MARVELL 0x5043
 411 #define PHY_OUI_CICADA  0x03f1
 412 #define PHYID1_OUI_MASK 0x03ff
 413 #define PHYID1_OUI_SHFT 6
 414 #define PHYID2_OUI_MASK 0xfc00
 415 #define PHYID2_OUI_SHFT 10
 416 #define PHY_INIT1       0x0f000
 417 #define PHY_INIT2       0x0e00
 418 #define PHY_INIT3       0x01000
 419 #define PHY_INIT4       0x0200
 420 #define PHY_INIT5       0x0004
 421 #define PHY_INIT6       0x02000
 422 #define PHY_GIGABIT     0x0100
 423
 424 #define PHY_TIMEOUT     0x1
 425 #define PHY_ERROR       0x2
 426
 427 #define PHY_100 0x1
 428 #define PHY_1000        0x2
 429 #define PHY_HALF        0x100
 430
 431 /* FIXME: MII defines that should be added to <linux/mii.h> */
 432 #define MII_1000BT_CR   0x09
 433 #define MII_1000BT_SR   0x0a
 434 #define ADVERTISE_1000FULL      0x0200
 435 #define ADVERTISE_1000HALF      0x0100
 436 #define LPA_1000FULL    0x0800
 437 #define LPA_1000HALF    0x0400
 438
 439
 440 /*
 441  * SMP locking:
 442  * All hardware access under dev->priv->lock, except the performance
 443  * critical parts:
 444  * - rx is (pseudo-) lockless: it relies on the single-threading provided
 445  *      by the arch code for interrupts.
 446  * - tx setup is lockless: it relies on dev->xmit_lock. Actual submission
 447  *      needs dev->priv->lock :-(
 448  * - set_multicast_list: preparation lockless, relies on dev->xmit_lock.
 449  */
 450
 451 /* in dev: base, irq */
 452 struct fe_priv {
 453         spinlock_t lock;
 454
 455         /* General data:
 456          * Locking: spin_lock(&np->lock); */
 457         struct net_device_stats stats;
 458         int in_shutdown;
 459         u32 linkspeed;
 460         int duplex;
 461         int autoneg;
 462         int fixed_mode;
 463         int phyaddr;
 464         int wolenabled;
 465         unsigned int phy_oui;
 466         u16 gigabit;
 467
 468         /* General data: RO fields */
 469         dma_addr_t ring_addr;
 470         struct pci_dev *pci_dev;
 471         u32 orig_mac[2];
 472         u32 irqmask;
 473         u32 desc_ver;
 474
 475         void __iomem *base;
 476
 477         /* rx specific fields.
 478          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 479          */
 480         struct ring_desc *rx_ring;
 481         unsigned int cur_rx, refill_rx;
 482         struct sk_buff *rx_skbuff[RX_RING];
 483         dma_addr_t rx_dma[RX_RING];
 484         unsigned int rx_buf_sz;
 485         unsigned int pkt_limit;
 486         struct timer_list oom_kick;
 487         struct timer_list nic_poll;
 488
 489         /* media detection workaround.
 490          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 491          */
 492         int need_linktimer;
 493         unsigned long link_timeout;
 494         /*
 495          * tx specific fields.
 496          */
 497         struct ring_desc *tx_ring;
 498         unsigned int next_tx, nic_tx;
 499         struct sk_buff *tx_skbuff[TX_RING];
 500         dma_addr_t tx_dma[TX_RING];
 501         u32 tx_flags;
 502 };
 503
 504 /*
 505  * Maximum number of loops until we assume that a bit in the irq mask
 506  * is stuck. Overridable with module param.
 507  */
 508 static int max_interrupt_work = 5;
 509
 510 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
 511 {
 512         return netdev_priv(dev);
 513 }
 514
 515 static inline u8 __iomem *get_hwbase(struct net_device *dev)
 516 {
 517         return get_nvpriv(dev)->base;
 518 }
 519
 520 static inline void pci_push(u8 __iomem *base)
 521 {
 522         /* force out pending posted writes */
 523         readl(base);
 524 }
 525
 526 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
 527 {
 528         return le32_to_cpu(prd->FlagLen)
 529                 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
 530 }
 531
 532 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
 533                                 int delay, int delaymax, const char *msg)
 534 {
 535         u8 __iomem *base = get_hwbase(dev);
 536
 537         pci_push(base);
 538         do {
 539                 udelay(delay);
 540                 delaymax -= delay;
 541                 if (delaymax < 0) {
 542                         if (msg)
 543                                 printk(msg);
 544                         return 1;
 545                 }
 546         } while ((readl(base + offset) & mask) != target);
 547         return 0;
 548 }
 549
 550 #define MII_READ        (-1)
 551 /* mii_rw: read/write a register on the PHY.
 552  *
 553  * Caller must guarantee serialization
 554  */
 555 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
 556 {
 557         u8 __iomem *base = get_hwbase(dev);
 558         u32 reg;
 559         int retval;
 560
 561         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
 562
 563         reg = readl(base + NvRegMIIControl);
 564         if (reg & NVREG_MIICTL_INUSE) {
 565                 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
 566                 udelay(NV_MIIBUSY_DELAY);
 567         }
 568
 569         reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
 570         if (value != MII_READ) {
 571                 writel(value, base + NvRegMIIData);
 572                 reg |= NVREG_MIICTL_WRITE;
 573         }
 574         writel(reg, base + NvRegMIIControl);
 575
 576         if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
 577                         NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
 578                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
 579                                 dev->name, miireg, addr);
 580                 retval = -1;
 581         } else if (value != MII_READ) {
 582                 /* it was a write operation - fewer failures are detectable */
 583                 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
 584                                 dev->name, value, miireg, addr);
 585                 retval = 0;
 586         } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
 587                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
 588                                 dev->name, miireg, addr);
 589                 retval = -1;
 590         } else {
 591                 retval = readl(base + NvRegMIIData);
 592                 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
 593                                 dev->name, miireg, addr, retval);
 594         }
 595
 596         return retval;
 597 }
 598
 599 static int phy_reset(struct net_device *dev)
 600 {
 601         struct fe_priv *np = get_nvpriv(dev);
 602         u32 miicontrol;
 603         unsigned int tries = 0;
 604
 605         miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
 606         miicontrol |= BMCR_RESET;
 607         if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
 608                 return -1;
 609         }
 610
 611         /* wait for 500ms */
 612         msleep(500);
 613
 614         /* must wait till reset is deasserted */
 615         while (miicontrol & BMCR_RESET) {
 616                 msleep(10);
 617                 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
 618                 /* FIXME: 100 tries seem excessive */
 619                 if (tries++ > 100)
 620                         return -1;
 621         }
 622         return 0;
 623 }
 624
 625 static int phy_init(struct net_device *dev)
 626 {
 627         struct fe_priv *np = get_nvpriv(dev);
 628         u8 __iomem *base = get_hwbase(dev);
 629         u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
 630
 631         /* set advertise register */
 632         reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
 633         reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|0x800|0x400);
 634         if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
 635                 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
 636                 return PHY_ERROR;
 637         }
 638
 639         /* get phy interface type */
 640         phyinterface = readl(base + NvRegPhyInterface);
 641
 642         /* see if gigabit phy */
 643         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
 644         if (mii_status & PHY_GIGABIT) {
 645                 np->gigabit = PHY_GIGABIT;
 646                 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
 647                 mii_control_1000 &= ~ADVERTISE_1000HALF;
 648                 if (phyinterface & PHY_RGMII)
 649                         mii_control_1000 |= ADVERTISE_1000FULL;
 650                 else
 651                         mii_control_1000 &= ~ADVERTISE_1000FULL;
 652
 653                 if (mii_rw(dev, np->phyaddr, MII_1000BT_CR, mii_control_1000)) {
 654                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
 655                         return PHY_ERROR;
 656                 }
 657         }
 658         else
 659                 np->gigabit = 0;
 660
 661         /* reset the phy */
 662         if (phy_reset(dev)) {
 663                 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
 664                 return PHY_ERROR;
 665         }
 666
 667         /* phy vendor specific configuration */
 668         if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
 669                 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
 670                 phy_reserved &= ~(PHY_INIT1 | PHY_INIT2);
 671                 phy_reserved |= (PHY_INIT3 | PHY_INIT4);
 672                 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
 673                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
 674                         return PHY_ERROR;
 675                 }
 676                 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
 677                 phy_reserved |= PHY_INIT5;
 678                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
 679                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
 680                         return PHY_ERROR;
 681                 }
 682         }
 683         if (np->phy_oui == PHY_OUI_CICADA) {
 684                 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
 685                 phy_reserved |= PHY_INIT6;
 686                 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
 687                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
 688                         return PHY_ERROR;
 689                 }
 690         }
 691
 692         /* restart auto negotiation */
 693         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
 694         mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
 695         if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
 696                 return PHY_ERROR;
 697         }
 698
 699         return 0;
 700 }
 701
 702 static void nv_start_rx(struct net_device *dev)
 703 {
 704         struct fe_priv *np = get_nvpriv(dev);
 705         u8 __iomem *base = get_hwbase(dev);
 706
 707         dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
 708         /* Already running? Stop it. */
 709         if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
 710                 writel(0, base + NvRegReceiverControl);
 711                 pci_push(base);
 712         }
 713         writel(np->linkspeed, base + NvRegLinkSpeed);
 714         pci_push(base);
 715         writel(NVREG_RCVCTL_START, base + NvRegReceiverControl);
 716         dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
 717                                 dev->name, np->duplex, np->linkspeed);
 718         pci_push(base);
 719 }
 720
 721 static void nv_stop_rx(struct net_device *dev)
 722 {
 723         u8 __iomem *base = get_hwbase(dev);
 724
 725         dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
 726         writel(0, base + NvRegReceiverControl);
 727         reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
 728                         NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
 729                         KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
 730
 731         udelay(NV_RXSTOP_DELAY2);
 732         writel(0, base + NvRegLinkSpeed);
 733 }
 734
 735 static void nv_start_tx(struct net_device *dev)
 736 {
 737         u8 __iomem *base = get_hwbase(dev);
 738
 739         dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
 740         writel(NVREG_XMITCTL_START, base + NvRegTransmitterControl);
 741         pci_push(base);
 742 }
 743
 744 static void nv_stop_tx(struct net_device *dev)
 745 {
 746         u8 __iomem *base = get_hwbase(dev);
 747
 748         dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
 749         writel(0, base + NvRegTransmitterControl);
 750         reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
 751                         NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
 752                         KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
 753
 754         udelay(NV_TXSTOP_DELAY2);
 755         writel(0, base + NvRegUnknownTransmitterReg);
 756 }
 757
 758 static void nv_txrx_reset(struct net_device *dev)
 759 {
 760         struct fe_priv *np = get_nvpriv(dev);
 761         u8 __iomem *base = get_hwbase(dev);
 762
 763         dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
 764         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->desc_ver, base + NvRegTxRxControl);
 765         pci_push(base);
 766         udelay(NV_TXRX_RESET_DELAY);
 767         writel(NVREG_TXRXCTL_BIT2 | np->desc_ver, base + NvRegTxRxControl);
 768         pci_push(base);
 769 }
 770
 771 /*
 772  * nv_get_stats: dev->get_stats function
 773  * Get latest stats value from the nic.
 774  * Called with read_lock(&dev_base_lock) held for read -
 775  * only synchronized against unregister_netdevice.
 776  */
 777 static struct net_device_stats *nv_get_stats(struct net_device *dev)
 778 {
 779         struct fe_priv *np = get_nvpriv(dev);
 780
 781         /* It seems that the nic always generates interrupts and doesn't
 782          * accumulate errors internally. Thus the current values in np->stats
 783          * are already up to date.
 784          */
 785         return &np->stats;
 786 }
 787
 788 /*
 789  * nv_alloc_rx: fill rx ring entries.
 790  * Return 1 if the allocations for the skbs failed and the
 791  * rx engine is without Available descriptors
 792  */
 793 static int nv_alloc_rx(struct net_device *dev)
 794 {
 795         struct fe_priv *np = get_nvpriv(dev);
 796         unsigned int refill_rx = np->refill_rx;
 797         int nr;
 798
 799         while (np->cur_rx != refill_rx) {
 800                 struct sk_buff *skb;
 801
 802                 nr = refill_rx % RX_RING;
 803                 if (np->rx_skbuff[nr] == NULL) {
 804
 805                         skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
 806                         if (!skb)
 807                                 break;
 808
 809                         skb->dev = dev;
 810                         np->rx_skbuff[nr] = skb;
 811                 } else {
 812                         skb = np->rx_skbuff[nr];
 813                 }
 814                 np->rx_dma[nr] = pci_map_single(np->pci_dev, skb->data, skb->len,
 815                                                 PCI_DMA_FROMDEVICE);
 816                 np->rx_ring[nr].PacketBuffer = cpu_to_le32(np->rx_dma[nr]);
 817                 wmb();
 818                 np->rx_ring[nr].FlagLen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
 819                 dprintk(KERN_DEBUG "%s: nv_alloc_rx: Packet %d marked as Available\n",
 820                                         dev->name, refill_rx);
 821                 refill_rx++;
 822         }
 823         np->refill_rx = refill_rx;
 824         if (np->cur_rx - refill_rx == RX_RING)
 825                 return 1;
 826         return 0;
 827 }
 828
 829 static void nv_do_rx_refill(unsigned long data)
 830 {
 831         struct net_device *dev = (struct net_device *) data;
 832         struct fe_priv *np = get_nvpriv(dev);
 833
 834         disable_irq(dev->irq);
 835         if (nv_alloc_rx(dev)) {
 836                 spin_lock(&np->lock);
 837                 if (!np->in_shutdown)
 838                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
 839                 spin_unlock(&np->lock);
 840         }
 841         enable_irq(dev->irq);
 842 }
 843
 844 static void nv_init_rx(struct net_device *dev)
 845 {
 846         struct fe_priv *np = get_nvpriv(dev);
 847         int i;
 848
 849         np->cur_rx = RX_RING;
 850         np->refill_rx = 0;
 851         for (i = 0; i < RX_RING; i++)
 852                 np->rx_ring[i].FlagLen = 0;
 853 }
 854
 855 static void nv_init_tx(struct net_device *dev)
 856 {
 857         struct fe_priv *np = get_nvpriv(dev);
 858         int i;
 859
 860         np->next_tx = np->nic_tx = 0;
 861         for (i = 0; i < TX_RING; i++)
 862                 np->tx_ring[i].FlagLen = 0;
 863 }
 864
 865 static int nv_init_ring(struct net_device *dev)
 866 {
 867         nv_init_tx(dev);
 868         nv_init_rx(dev);
 869         return nv_alloc_rx(dev);
 870 }
 871
 872 static void nv_drain_tx(struct net_device *dev)
 873 {
 874         struct fe_priv *np = get_nvpriv(dev);
 875         int i;
 876         for (i = 0; i < TX_RING; i++) {
 877                 np->tx_ring[i].FlagLen = 0;
 878                 if (np->tx_skbuff[i]) {
 879                         pci_unmap_single(np->pci_dev, np->tx_dma[i],
 880                                                 np->tx_skbuff[i]->len,
 881                                                 PCI_DMA_TODEVICE);
 882                         dev_kfree_skb(np->tx_skbuff[i]);
 883                         np->tx_skbuff[i] = NULL;
 884                         np->stats.tx_dropped++;
 885                 }
 886         }
 887 }
 888
 889 static void nv_drain_rx(struct net_device *dev)
 890 {
 891         struct fe_priv *np = get_nvpriv(dev);
 892         int i;
 893         for (i = 0; i < RX_RING; i++) {
 894                 np->rx_ring[i].FlagLen = 0;
 895                 wmb();
 896                 if (np->rx_skbuff[i]) {
 897                         pci_unmap_single(np->pci_dev, np->rx_dma[i],
 898                                                 np->rx_skbuff[i]->len,
 899                                                 PCI_DMA_FROMDEVICE);
 900                         dev_kfree_skb(np->rx_skbuff[i]);
 901                         np->rx_skbuff[i] = NULL;
 902                 }
 903         }
 904 }
 905
 906 static void drain_ring(struct net_device *dev)
 907 {
 908         nv_drain_tx(dev);
 909         nv_drain_rx(dev);
 910 }
 911
 912 /*
 913  * nv_start_xmit: dev->hard_start_xmit function
 914  * Called with dev->xmit_lock held.
 915  */
 916 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
 917 {
 918         struct fe_priv *np = get_nvpriv(dev);
 919         int nr = np->next_tx % TX_RING;
 920
 921         np->tx_skbuff[nr] = skb;
 922         np->tx_dma[nr] = pci_map_single(np->pci_dev, skb->data,skb->len,
 923                                         PCI_DMA_TODEVICE);
 924
 925         np->tx_ring[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]);
 926
 927         spin_lock_irq(&np->lock);
 928         wmb();
 929         np->tx_ring[nr].FlagLen = cpu_to_le32( (skb->len-1) | np->tx_flags );
 930         dprintk(KERN_DEBUG "%s: nv_start_xmit: packet packet %d queued for transmission.\n",
 931                                 dev->name, np->next_tx);
 932         {
 933                 int j;
 934                 for (j=0; j<64; j++) {
 935                         if ((j%16) == 0)
 936                                 dprintk("\n%03x:", j);
 937                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
 938                 }
 939                 dprintk("\n");
 940         }
 941
 942         np->next_tx++;
 943
 944         dev->trans_start = jiffies;
 945         if (np->next_tx - np->nic_tx >= TX_LIMIT_STOP)
 946                 netif_stop_queue(dev);
 947         spin_unlock_irq(&np->lock);
 948         writel(NVREG_TXRXCTL_KICK|np->desc_ver, get_hwbase(dev) + NvRegTxRxControl);
 949         pci_push(get_hwbase(dev));
 950         return 0;
 951 }
 952
 953 /*
 954  * nv_tx_done: check for completed packets, release the skbs.
 955  *
 956  * Caller must own np->lock.
 957  */
 958 static void nv_tx_done(struct net_device *dev)
 959 {
 960         struct fe_priv *np = get_nvpriv(dev);
 961         u32 Flags;
 962         int i;
 963
 964         while (np->nic_tx != np->next_tx) {
 965                 i = np->nic_tx % TX_RING;
 966
 967                 Flags = le32_to_cpu(np->tx_ring[i].FlagLen);
 968
 969                 dprintk(KERN_DEBUG "%s: nv_tx_done: looking at packet %d, Flags 0x%x.\n",
 970                                         dev->name, np->nic_tx, Flags);
 971                 if (Flags & NV_TX_VALID)
 972                         break;
 973                 if (np->desc_ver == DESC_VER_1) {
 974                         if (Flags & (NV_TX_RETRYERROR|NV_TX_CARRIERLOST|NV_TX_LATECOLLISION|
 975                                                         NV_TX_UNDERFLOW|NV_TX_ERROR)) {
 976                                 if (Flags & NV_TX_UNDERFLOW)
 977                                         np->stats.tx_fifo_errors++;
 978                                 if (Flags & NV_TX_CARRIERLOST)
 979                                         np->stats.tx_carrier_errors++;
 980                                 np->stats.tx_errors++;
 981                         } else {
 982                                 np->stats.tx_packets++;
 983                                 np->stats.tx_bytes += np->tx_skbuff[i]->len;
 984                         }
 985                 } else {
 986                         if (Flags & (NV_TX2_RETRYERROR|NV_TX2_CARRIERLOST|NV_TX2_LATECOLLISION|
 987                                                         NV_TX2_UNDERFLOW|NV_TX2_ERROR)) {
 988                                 if (Flags & NV_TX2_UNDERFLOW)
 989                                         np->stats.tx_fifo_errors++;
 990                                 if (Flags & NV_TX2_CARRIERLOST)
 991                                         np->stats.tx_carrier_errors++;
 992                                 np->stats.tx_errors++;
 993                         } else {
 994                                 np->stats.tx_packets++;
 995                                 np->stats.tx_bytes += np->tx_skbuff[i]->len;
 996                         }
 997                 }
 998                 pci_unmap_single(np->pci_dev, np->tx_dma[i],
 999                                         np->tx_skbuff[i]->len,
1000                                         PCI_DMA_TODEVICE);
1001                 dev_kfree_skb_irq(np->tx_skbuff[i]);
1002                 np->tx_skbuff[i] = NULL;
1003                 np->nic_tx++;
1004         }
1005         if (np->next_tx - np->nic_tx < TX_LIMIT_START)
1006                 netif_wake_queue(dev);
1007 }
1008
1009 /*
1010  * nv_tx_timeout: dev->tx_timeout function
1011  * Called with dev->xmit_lock held.
1012  */
1013 static void nv_tx_timeout(struct net_device *dev)
1014 {
1015         struct fe_priv *np = get_nvpriv(dev);
1016         u8 __iomem *base = get_hwbase(dev);
1017
1018         printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name,
1019                         readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK);
1020
1021         {
1022                 int i;
1023
1024                 printk(KERN_INFO "%s: Ring at %lx: next %d nic %d\n",
1025                                 dev->name, (unsigned long)np->ring_addr,
1026                                 np->next_tx, np->nic_tx);
1027                 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
1028                 for (i=0;i<0x400;i+= 32) {
1029                         printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1030                                         i,
1031                                         readl(base + i + 0), readl(base + i + 4),
1032                                         readl(base + i + 8), readl(base + i + 12),
1033                                         readl(base + i + 16), readl(base + i + 20),
1034                                         readl(base + i + 24), readl(base + i + 28));
1035                 }
1036                 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
1037                 for (i=0;i<TX_RING;i+= 4) {
1038                         printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
1039                                         i,
1040                                         le32_to_cpu(np->tx_ring[i].PacketBuffer),
1041                                         le32_to_cpu(np->tx_ring[i].FlagLen),
1042                                         le32_to_cpu(np->tx_ring[i+1].PacketBuffer),
1043                                         le32_to_cpu(np->tx_ring[i+1].FlagLen),
1044                                         le32_to_cpu(np->tx_ring[i+2].PacketBuffer),
1045                                         le32_to_cpu(np->tx_ring[i+2].FlagLen),
1046                                         le32_to_cpu(np->tx_ring[i+3].PacketBuffer),
1047                                         le32_to_cpu(np->tx_ring[i+3].FlagLen));
1048                 }
1049         }
1050
1051         spin_lock_irq(&np->lock);
1052
1053         /* 1) stop tx engine */
1054         nv_stop_tx(dev);
1055
1056         /* 2) check that the packets were not sent already: */
1057         nv_tx_done(dev);
1058
1059         /* 3) if there are dead entries: clear everything */
1060         if (np->next_tx != np->nic_tx) {
1061                 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
1062                 nv_drain_tx(dev);
1063                 np->next_tx = np->nic_tx = 0;
1064                 writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
1065                 netif_wake_queue(dev);
1066         }
1067
1068         /* 4) restart tx engine */
1069         nv_start_tx(dev);
1070         spin_unlock_irq(&np->lock);
1071 }
1072
1073 /*
1074  * Called when the nic notices a mismatch between the actual data len on the
1075  * wire and the len indicated in the 802 header
1076  */
1077 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
1078 {
1079         int hdrlen;     /* length of the 802 header */
1080         int protolen;   /* length as stored in the proto field */
1081
1082         /* 1) calculate len according to header */
1083         if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == __constant_htons(ETH_P_8021Q)) {
1084                 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
1085                 hdrlen = VLAN_HLEN;
1086         } else {
1087                 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
1088                 hdrlen = ETH_HLEN;
1089         }
1090         dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
1091                                 dev->name, datalen, protolen, hdrlen);
1092         if (protolen > ETH_DATA_LEN)
1093                 return datalen; /* Value in proto field not a len, no checks possible */
1094
1095         protolen += hdrlen;
1096         /* consistency checks: */
1097         if (datalen > ETH_ZLEN) {
1098                 if (datalen >= protolen) {
1099                         /* more data on wire than in 802 header, trim of
1100                          * additional data.
1101                          */
1102                         dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1103                                         dev->name, protolen);
1104                         return protolen;
1105                 } else {
1106                         /* less data on wire than mentioned in header.
1107                          * Discard the packet.
1108                          */
1109                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
1110                                         dev->name);
1111                         return -1;
1112                 }
1113         } else {
1114                 /* short packet. Accept only if 802 values are also short */
1115                 if (protolen > ETH_ZLEN) {
1116                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
1117                                         dev->name);
1118                         return -1;
1119                 }
1120                 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1121                                 dev->name, datalen);
1122                 return datalen;
1123         }
1124 }
1125
1126 static void nv_rx_process(struct net_device *dev)
1127 {
1128         struct fe_priv *np = get_nvpriv(dev);
1129         u32 Flags;
1130
1131         for (;;) {
1132                 struct sk_buff *skb;
1133                 int len;
1134                 int i;
1135                 if (np->cur_rx - np->refill_rx >= RX_RING)
1136                         break;  /* we scanned the whole ring - do not continue */
1137
1138                 i = np->cur_rx % RX_RING;
1139                 Flags = le32_to_cpu(np->rx_ring[i].FlagLen);
1140                 len = nv_descr_getlength(&np->rx_ring[i], np->desc_ver);
1141
1142                 dprintk(KERN_DEBUG "%s: nv_rx_process: looking at packet %d, Flags 0x%x.\n",
1143                                         dev->name, np->cur_rx, Flags);
1144
1145                 if (Flags & NV_RX_AVAIL)
1146                         break;  /* still owned by hardware, */
1147
1148                 /*
1149                  * the packet is for us - immediately tear down the pci mapping.
1150                  * TODO: check if a prefetch of the first cacheline improves
1151                  * the performance.
1152                  */
1153                 pci_unmap_single(np->pci_dev, np->rx_dma[i],
1154                                 np->rx_skbuff[i]->len,
1155                                 PCI_DMA_FROMDEVICE);
1156
1157                 {
1158                         int j;
1159                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",Flags);
1160                         for (j=0; j<64; j++) {
1161                                 if ((j%16) == 0)
1162                                         dprintk("\n%03x:", j);
1163                                 dprintk(" %02x", ((unsigned char*)np->rx_skbuff[i]->data)[j]);
1164                         }
1165                         dprintk("\n");
1166                 }
1167                 /* look at what we actually got: */
1168                 if (np->desc_ver == DESC_VER_1) {
1169                         if (!(Flags & NV_RX_DESCRIPTORVALID))
1170                                 goto next_pkt;
1171
1172                         if (Flags & NV_RX_MISSEDFRAME) {
1173                                 np->stats.rx_missed_errors++;
1174                                 np->stats.rx_errors++;
1175                                 goto next_pkt;
1176                         }
1177                         if (Flags & (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3)) {
1178                                 np->stats.rx_errors++;
1179                                 goto next_pkt;
1180                         }
1181                         if (Flags & NV_RX_CRCERR) {
1182                                 np->stats.rx_crc_errors++;
1183                                 np->stats.rx_errors++;
1184                                 goto next_pkt;
1185                         }
1186                         if (Flags & NV_RX_OVERFLOW) {
1187                                 np->stats.rx_over_errors++;
1188                                 np->stats.rx_errors++;
1189                                 goto next_pkt;
1190                         }
1191                         if (Flags & NV_RX_ERROR4) {
1192                                 len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1193                                 if (len < 0) {
1194                                         np->stats.rx_errors++;
1195                                         goto next_pkt;
1196                                 }
1197                         }
1198                         /* framing errors are soft errors. */
1199                         if (Flags & NV_RX_FRAMINGERR) {
1200                                 if (Flags & NV_RX_SUBSTRACT1) {
1201                                         len--;
1202                                 }
1203                         }
1204                 } else {
1205                         if (!(Flags & NV_RX2_DESCRIPTORVALID))
1206                                 goto next_pkt;
1207
1208                         if (Flags & (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3)) {
1209                                 np->stats.rx_errors++;
1210                                 goto next_pkt;
1211                         }
1212                         if (Flags & NV_RX2_CRCERR) {
1213                                 np->stats.rx_crc_errors++;
1214                                 np->stats.rx_errors++;
1215                                 goto next_pkt;
1216                         }
1217                         if (Flags & NV_RX2_OVERFLOW) {
1218                                 np->stats.rx_over_errors++;
1219                                 np->stats.rx_errors++;
1220                                 goto next_pkt;
1221                         }
1222                         if (Flags & NV_RX2_ERROR4) {
1223                                 len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1224                                 if (len < 0) {
1225                                         np->stats.rx_errors++;
1226                                         goto next_pkt;
1227                                 }
1228                         }
1229                         /* framing errors are soft errors */
1230                         if (Flags & NV_RX2_FRAMINGERR) {
1231                                 if (Flags & NV_RX2_SUBSTRACT1) {
1232                                         len--;
1233                                 }
1234                         }
1235                         Flags &= NV_RX2_CHECKSUMMASK;
1236                         if (Flags == NV_RX2_CHECKSUMOK1 ||
1237                                         Flags == NV_RX2_CHECKSUMOK2 ||
1238                                         Flags == NV_RX2_CHECKSUMOK3) {
1239                                 dprintk(KERN_DEBUG "%s: hw checksum hit!.\n", dev->name);
1240                                 np->rx_skbuff[i]->ip_summed = CHECKSUM_UNNECESSARY;
1241                         } else {
1242                                 dprintk(KERN_DEBUG "%s: hwchecksum miss!.\n", dev->name);
1243                         }
1244                 }
1245                 /* got a valid packet - forward it to the network core */
1246                 skb = np->rx_skbuff[i];
1247                 np->rx_skbuff[i] = NULL;
1248
1249                 skb_put(skb, len);
1250                 skb->protocol = eth_type_trans(skb, dev);
1251                 dprintk(KERN_DEBUG "%s: nv_rx_process: packet %d with %d bytes, proto %d accepted.\n",
1252                                         dev->name, np->cur_rx, len, skb->protocol);
1253                 netif_rx(skb);
1254                 dev->last_rx = jiffies;
1255                 np->stats.rx_packets++;
1256                 np->stats.rx_bytes += len;
1257 next_pkt:
1258                 np->cur_rx++;
1259         }
1260 }
1261
1262 static void set_bufsize(struct net_device *dev)
1263 {
1264         struct fe_priv *np = netdev_priv(dev);
1265
1266         if (dev->mtu <= ETH_DATA_LEN)
1267                 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
1268         else
1269                 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
1270 }
1271
1272 /*
1273  * nv_change_mtu: dev->change_mtu function
1274  * Called with dev_base_lock held for read.
1275  */
1276 static int nv_change_mtu(struct net_device *dev, int new_mtu)
1277 {
1278         struct fe_priv *np = get_nvpriv(dev);
1279         int old_mtu;
1280
1281         if (new_mtu < 64 || new_mtu > np->pkt_limit)
1282                 return -EINVAL;
1283
1284         old_mtu = dev->mtu;
1285         dev->mtu = new_mtu;
1286
1287         /* return early if the buffer sizes will not change */
1288         if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
1289                 return 0;
1290         if (old_mtu == new_mtu)
1291                 return 0;
1292
1293         /* synchronized against open : rtnl_lock() held by caller */
1294         if (netif_running(dev)) {
1295                 u8 *base = get_hwbase(dev);
1296                 /*
1297                  * It seems that the nic preloads valid ring entries into an
1298                  * internal buffer. The procedure for flushing everything is
1299                  * guessed, there is probably a simpler approach.
1300                  * Changing the MTU is a rare event, it shouldn't matter.
1301                  */
1302                 disable_irq(dev->irq);
1303                 spin_lock_bh(&dev->xmit_lock);
1304                 spin_lock(&np->lock);
1305                 /* stop engines */
1306                 nv_stop_rx(dev);
1307                 nv_stop_tx(dev);
1308                 nv_txrx_reset(dev);
1309                 /* drain rx queue */
1310                 nv_drain_rx(dev);
1311                 nv_drain_tx(dev);
1312                 /* reinit driver view of the rx queue */
1313                 nv_init_rx(dev);
1314                 nv_init_tx(dev);
1315                 /* alloc new rx buffers */
1316                 set_bufsize(dev);
1317                 if (nv_alloc_rx(dev)) {
1318                         if (!np->in_shutdown)
1319                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1320                 }
1321                 /* reinit nic view of the rx queue */
1322                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
1323                 writel((u32) np->ring_addr, base + NvRegRxRingPhysAddr);
1324                 writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
1325                 writel( ((RX_RING-1) << NVREG_RINGSZ_RXSHIFT) + ((TX_RING-1) << NVREG_RINGSZ_TXSHIFT),
1326                         base + NvRegRingSizes);
1327                 pci_push(base);
1328                 writel(NVREG_TXRXCTL_KICK|np->desc_ver, get_hwbase(dev) + NvRegTxRxControl);
1329                 pci_push(base);
1330
1331                 /* restart rx engine */
1332                 nv_start_rx(dev);
1333                 nv_start_tx(dev);
1334                 spin_unlock(&np->lock);
1335                 spin_unlock_bh(&dev->xmit_lock);
1336                 enable_irq(dev->irq);
1337         }
1338         return 0;
1339 }
1340
1341 /*
1342  * nv_set_multicast: dev->set_multicast function
1343  * Called with dev->xmit_lock held.
1344  */
1345 static void nv_set_multicast(struct net_device *dev)
1346 {
1347         struct fe_priv *np = get_nvpriv(dev);
1348         u8 __iomem *base = get_hwbase(dev);
1349         u32 addr[2];
1350         u32 mask[2];
1351         u32 pff;
1352
1353         memset(addr, 0, sizeof(addr));
1354         memset(mask, 0, sizeof(mask));
1355
1356         if (dev->flags & IFF_PROMISC) {
1357                 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", dev->name);
1358                 pff = NVREG_PFF_PROMISC;
1359         } else {
1360                 pff = NVREG_PFF_MYADDR;
1361
1362                 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
1363                         u32 alwaysOff[2];
1364                         u32 alwaysOn[2];
1365
1366                         alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
1367                         if (dev->flags & IFF_ALLMULTI) {
1368                                 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
1369                         } else {
1370                                 struct dev_mc_list *walk;
1371
1372                                 walk = dev->mc_list;
1373                                 while (walk != NULL) {
1374                                         u32 a, b;
1375                                         a = le32_to_cpu(*(u32 *) walk->dmi_addr);
1376                                         b = le16_to_cpu(*(u16 *) (&walk->dmi_addr[4]));
1377                                         alwaysOn[0] &= a;
1378                                         alwaysOff[0] &= ~a;
1379                                         alwaysOn[1] &= b;
1380                                         alwaysOff[1] &= ~b;
1381                                         walk = walk->next;
1382                                 }
1383                         }
1384                         addr[0] = alwaysOn[0];
1385                         addr[1] = alwaysOn[1];
1386                         mask[0] = alwaysOn[0] | alwaysOff[0];
1387                         mask[1] = alwaysOn[1] | alwaysOff[1];
1388                 }
1389         }
1390         addr[0] |= NVREG_MCASTADDRA_FORCE;
1391         pff |= NVREG_PFF_ALWAYS;
1392         spin_lock_irq(&np->lock);
1393         nv_stop_rx(dev);
1394         writel(addr[0], base + NvRegMulticastAddrA);
1395         writel(addr[1], base + NvRegMulticastAddrB);
1396         writel(mask[0], base + NvRegMulticastMaskA);
1397         writel(mask[1], base + NvRegMulticastMaskB);
1398         writel(pff, base + NvRegPacketFilterFlags);
1399         dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
1400                 dev->name);
1401         nv_start_rx(dev);
1402         spin_unlock_irq(&np->lock);
1403 }
1404
1405 static int nv_update_linkspeed(struct net_device *dev)
1406 {
1407         struct fe_priv *np = get_nvpriv(dev);
1408         u8 __iomem *base = get_hwbase(dev);
1409         int adv, lpa;
1410         int newls = np->linkspeed;
1411         int newdup = np->duplex;
1412         int mii_status;
1413         int retval = 0;
1414         u32 control_1000, status_1000, phyreg;
1415
1416         /* BMSR_LSTATUS is latched, read it twice:
1417          * we want the current value.
1418          */
1419         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1420         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1421
1422         if (!(mii_status & BMSR_LSTATUS)) {
1423                 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
1424                                 dev->name);
1425                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1426                 newdup = 0;
1427                 retval = 0;
1428                 goto set_speed;
1429         }
1430
1431         if (np->autoneg == 0) {
1432                 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
1433                                 dev->name, np->fixed_mode);
1434                 if (np->fixed_mode & LPA_100FULL) {
1435                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1436                         newdup = 1;
1437                 } else if (np->fixed_mode & LPA_100HALF) {
1438                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1439                         newdup = 0;
1440                 } else if (np->fixed_mode & LPA_10FULL) {
1441                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1442                         newdup = 1;
1443                 } else {
1444                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1445                         newdup = 0;
1446                 }
1447                 retval = 1;
1448                 goto set_speed;
1449         }
1450         /* check auto negotiation is complete */
1451         if (!(mii_status & BMSR_ANEGCOMPLETE)) {
1452                 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
1453                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1454                 newdup = 0;
1455                 retval = 0;
1456                 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
1457                 goto set_speed;
1458         }
1459
1460         retval = 1;
1461         if (np->gigabit == PHY_GIGABIT) {
1462                 control_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
1463                 status_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_SR, MII_READ);
1464
1465                 if ((control_1000 & ADVERTISE_1000FULL) &&
1466                         (status_1000 & LPA_1000FULL)) {
1467                         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
1468                                 dev->name);
1469                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
1470                         newdup = 1;
1471                         goto set_speed;
1472                 }
1473         }
1474
1475         adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1476         lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
1477         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
1478                                 dev->name, adv, lpa);
1479
1480         /* FIXME: handle parallel detection properly */
1481         lpa = lpa & adv;
1482         if (lpa & LPA_100FULL) {
1483                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1484                 newdup = 1;
1485         } else if (lpa & LPA_100HALF) {
1486                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1487                 newdup = 0;
1488         } else if (lpa & LPA_10FULL) {
1489                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1490                 newdup = 1;
1491         } else if (lpa & LPA_10HALF) {
1492                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1493                 newdup = 0;
1494         } else {
1495                 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, lpa);
1496                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1497                 newdup = 0;
1498         }
1499
1500 set_speed:
1501         if (np->duplex == newdup && np->linkspeed == newls)
1502                 return retval;
1503
1504         dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
1505                         dev->name, np->linkspeed, np->duplex, newls, newdup);
1506
1507         np->duplex = newdup;
1508         np->linkspeed = newls;
1509
1510         if (np->gigabit == PHY_GIGABIT) {
1511                 phyreg = readl(base + NvRegRandomSeed);
1512                 phyreg &= ~(0x3FF00);
1513                 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
1514                         phyreg |= NVREG_RNDSEED_FORCE3;
1515                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
1516                         phyreg |= NVREG_RNDSEED_FORCE2;
1517                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
1518                         phyreg |= NVREG_RNDSEED_FORCE;
1519                 writel(phyreg, base + NvRegRandomSeed);
1520         }
1521
1522         phyreg = readl(base + NvRegPhyInterface);
1523         phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
1524         if (np->duplex == 0)
1525                 phyreg |= PHY_HALF;
1526         if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
1527                 phyreg |= PHY_100;
1528         else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
1529                 phyreg |= PHY_1000;
1530         writel(phyreg, base + NvRegPhyInterface);
1531
1532         writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
1533                 base + NvRegMisc1);
1534         pci_push(base);
1535         writel(np->linkspeed, base + NvRegLinkSpeed);
1536         pci_push(base);
1537
1538         return retval;
1539 }
1540
1541 static void nv_linkchange(struct net_device *dev)
1542 {
1543         if (nv_update_linkspeed(dev)) {
1544                 if (netif_carrier_ok(dev)) {
1545                         nv_stop_rx(dev);
1546                 } else {
1547                         netif_carrier_on(dev);
1548                         printk(KERN_INFO "%s: link up.\n", dev->name);
1549                 }
1550                 nv_start_rx(dev);
1551         } else {
1552                 if (netif_carrier_ok(dev)) {
1553                         netif_carrier_off(dev);
1554                         printk(KERN_INFO "%s: link down.\n", dev->name);
1555                         nv_stop_rx(dev);
1556                 }
1557         }
1558 }
1559
1560 static void nv_link_irq(struct net_device *dev)
1561 {
1562         u8 __iomem *base = get_hwbase(dev);
1563         u32 miistat;
1564
1565         miistat = readl(base + NvRegMIIStatus);
1566         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
1567         dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
1568
1569         if (miistat & (NVREG_MIISTAT_LINKCHANGE))
1570                 nv_linkchange(dev);
1571         dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
1572 }
1573
1574 static irqreturn_t nv_nic_irq(int foo, void *data, struct pt_regs *regs)
1575 {
1576         struct net_device *dev = (struct net_device *) data;
1577         struct fe_priv *np = get_nvpriv(dev);
1578         u8 __iomem *base = get_hwbase(dev);
1579         u32 events;
1580         int i;
1581
1582         dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
1583
1584         for (i=0; ; i++) {
1585                 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
1586                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
1587                 pci_push(base);
1588                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
1589                 if (!(events & np->irqmask))
1590                         break;
1591
1592                 if (events & (NVREG_IRQ_TX1|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_ERROR|NVREG_IRQ_TX_ERR)) {
1593                         spin_lock(&np->lock);
1594                         nv_tx_done(dev);
1595                         spin_unlock(&np->lock);
1596                 }
1597
1598                 if (events & (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF)) {
1599                         nv_rx_process(dev);
1600                         if (nv_alloc_rx(dev)) {
1601                                 spin_lock(&np->lock);
1602                                 if (!np->in_shutdown)
1603                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1604                                 spin_unlock(&np->lock);
1605                         }
1606                 }
1607
1608                 if (events & NVREG_IRQ_LINK) {
1609                         spin_lock(&np->lock);
1610                         nv_link_irq(dev);
1611                         spin_unlock(&np->lock);
1612                 }
1613                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
1614                         spin_lock(&np->lock);
1615                         nv_linkchange(dev);
1616                         spin_unlock(&np->lock);
1617                         np->link_timeout = jiffies + LINK_TIMEOUT;
1618                 }
1619                 if (events & (NVREG_IRQ_TX_ERR)) {
1620                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
1621                                                 dev->name, events);
1622                 }
1623                 if (events & (NVREG_IRQ_UNKNOWN)) {
1624                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
1625                                                 dev->name, events);
1626                 }
1627                 if (i > max_interrupt_work) {
1628                         spin_lock(&np->lock);
1629                         /* disable interrupts on the nic */
1630                         writel(0, base + NvRegIrqMask);
1631                         pci_push(base);
1632
1633                         if (!np->in_shutdown)
1634                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
1635                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
1636                         spin_unlock(&np->lock);
1637                         break;
1638                 }
1639
1640         }
1641         dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
1642
1643         return IRQ_RETVAL(i);
1644 }
1645
1646 static void nv_do_nic_poll(unsigned long data)
1647 {
1648         struct net_device *dev = (struct net_device *) data;
1649         struct fe_priv *np = get_nvpriv(dev);
1650         u8 __iomem *base = get_hwbase(dev);
1651
1652         disable_irq(dev->irq);
1653         /* FIXME: Do we need synchronize_irq(dev->irq) here? */
1654         /*
1655          * reenable interrupts on the nic, we have to do this before calling
1656          * nv_nic_irq because that may decide to do otherwise
1657          */
1658         writel(np->irqmask, base + NvRegIrqMask);
1659         pci_push(base);
1660         nv_nic_irq((int) 0, (void *) data, (struct pt_regs *) NULL);
1661         enable_irq(dev->irq);
1662 }
1663
1664 #ifdef CONFIG_NET_POLL_CONTROLLER
1665 static void nv_poll_controller(struct net_device *dev)
1666 {
1667         nv_do_nic_poll((unsigned long) dev);
1668 }
1669 #endif
1670
1671 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1672 {
1673         struct fe_priv *np = get_nvpriv(dev);
1674         strcpy(info->driver, "forcedeth");
1675         strcpy(info->version, FORCEDETH_VERSION);
1676         strcpy(info->bus_info, pci_name(np->pci_dev));
1677 }
1678
1679 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
1680 {
1681         struct fe_priv *np = get_nvpriv(dev);
1682         wolinfo->supported = WAKE_MAGIC;
1683
1684         spin_lock_irq(&np->lock);
1685         if (np->wolenabled)
1686                 wolinfo->wolopts = WAKE_MAGIC;
1687         spin_unlock_irq(&np->lock);
1688 }
1689
1690 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
1691 {
1692         struct fe_priv *np = get_nvpriv(dev);
1693         u8 __iomem *base = get_hwbase(dev);
1694
1695         spin_lock_irq(&np->lock);
1696         if (wolinfo->wolopts == 0) {
1697                 writel(0, base + NvRegWakeUpFlags);
1698                 np->wolenabled = 0;
1699         }
1700         if (wolinfo->wolopts & WAKE_MAGIC) {
1701                 writel(NVREG_WAKEUPFLAGS_ENABLE, base + NvRegWakeUpFlags);
1702                 np->wolenabled = 1;
1703         }
1704         spin_unlock_irq(&np->lock);
1705         return 0;
1706 }
1707
1708 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1709 {
1710         struct fe_priv *np = netdev_priv(dev);
1711         int adv;
1712
1713         spin_lock_irq(&np->lock);
1714         ecmd->port = PORT_MII;
1715         if (!netif_running(dev)) {
1716                 /* We do not track link speed / duplex setting if the
1717                  * interface is disabled. Force a link check */
1718                 nv_update_linkspeed(dev);
1719         }
1720         switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
1721                 case NVREG_LINKSPEED_10:
1722                         ecmd->speed = SPEED_10;
1723                         break;
1724                 case NVREG_LINKSPEED_100:
1725                         ecmd->speed = SPEED_100;
1726                         break;
1727                 case NVREG_LINKSPEED_1000:
1728                         ecmd->speed = SPEED_1000;
1729                         break;
1730         }
1731         ecmd->duplex = DUPLEX_HALF;
1732         if (np->duplex)
1733                 ecmd->duplex = DUPLEX_FULL;
1734
1735         ecmd->autoneg = np->autoneg;
1736
1737         ecmd->advertising = ADVERTISED_MII;
1738         if (np->autoneg) {
1739                 ecmd->advertising |= ADVERTISED_Autoneg;
1740                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1741         } else {
1742                 adv = np->fixed_mode;
1743         }
1744         if (adv & ADVERTISE_10HALF)
1745                 ecmd->advertising |= ADVERTISED_10baseT_Half;
1746         if (adv & ADVERTISE_10FULL)
1747                 ecmd->advertising |= ADVERTISED_10baseT_Full;
1748         if (adv & ADVERTISE_100HALF)
1749                 ecmd->advertising |= ADVERTISED_100baseT_Half;
1750         if (adv & ADVERTISE_100FULL)
1751                 ecmd->advertising |= ADVERTISED_100baseT_Full;
1752         if (np->autoneg && np->gigabit == PHY_GIGABIT) {
1753                 adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
1754                 if (adv & ADVERTISE_1000FULL)
1755                         ecmd->advertising |= ADVERTISED_1000baseT_Full;
1756         }
1757
1758         ecmd->supported = (SUPPORTED_Autoneg |
1759                 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
1760                 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
1761                 SUPPORTED_MII);
1762         if (np->gigabit == PHY_GIGABIT)
1763                 ecmd->supported |= SUPPORTED_1000baseT_Full;
1764
1765         ecmd->phy_address = np->phyaddr;
1766         ecmd->transceiver = XCVR_EXTERNAL;
1767
1768         /* ignore maxtxpkt, maxrxpkt for now */
1769         spin_unlock_irq(&np->lock);
1770         return 0;
1771 }
1772
1773 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1774 {
1775         struct fe_priv *np = netdev_priv(dev);
1776
1777         if (ecmd->port != PORT_MII)
1778                 return -EINVAL;
1779         if (ecmd->transceiver != XCVR_EXTERNAL)
1780                 return -EINVAL;
1781         if (ecmd->phy_address != np->phyaddr) {
1782                 /* TODO: support switching between multiple phys. Should be
1783                  * trivial, but not enabled due to lack of test hardware. */
1784                 return -EINVAL;
1785         }
1786         if (ecmd->autoneg == AUTONEG_ENABLE) {
1787                 u32 mask;
1788
1789                 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
1790                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
1791                 if (np->gigabit == PHY_GIGABIT)
1792                         mask |= ADVERTISED_1000baseT_Full;
1793
1794                 if ((ecmd->advertising & mask) == 0)
1795                         return -EINVAL;
1796
1797         } else if (ecmd->autoneg == AUTONEG_DISABLE) {
1798                 /* Note: autonegotiation disable, speed 1000 intentionally
1799                  * forbidden - noone should need that. */
1800
1801                 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
1802                         return -EINVAL;
1803                 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
1804                         return -EINVAL;
1805         } else {
1806                 return -EINVAL;
1807         }
1808
1809         spin_lock_irq(&np->lock);
1810         if (ecmd->autoneg == AUTONEG_ENABLE) {
1811                 int adv, bmcr;
1812
1813                 np->autoneg = 1;
1814
1815                 /* advertise only what has been requested */
1816                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1817                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
1818                 if (ecmd->advertising & ADVERTISED_10baseT_Half)
1819                         adv |= ADVERTISE_10HALF;
1820                 if (ecmd->advertising & ADVERTISED_10baseT_Full)
1821                         adv |= ADVERTISE_10FULL;
1822                 if (ecmd->advertising & ADVERTISED_100baseT_Half)
1823                         adv |= ADVERTISE_100HALF;
1824                 if (ecmd->advertising & ADVERTISED_100baseT_Full)
1825                         adv |= ADVERTISE_100FULL;
1826                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
1827
1828                 if (np->gigabit == PHY_GIGABIT) {
1829                         adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
1830                         adv &= ~ADVERTISE_1000FULL;
1831                         if (ecmd->advertising & ADVERTISED_1000baseT_Full)
1832                                 adv |= ADVERTISE_1000FULL;
1833                         mii_rw(dev, np->phyaddr, MII_1000BT_CR, adv);
1834                 }
1835
1836                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1837                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1838                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
1839
1840         } else {
1841                 int adv, bmcr;
1842
1843                 np->autoneg = 0;
1844
1845                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1846                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
1847                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
1848                         adv |= ADVERTISE_10HALF;
1849                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
1850                         adv |= ADVERTISE_10FULL;
1851                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
1852                         adv |= ADVERTISE_100HALF;
1853                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
1854                         adv |= ADVERTISE_100FULL;
1855                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
1856                 np->fixed_mode = adv;
1857
1858                 if (np->gigabit == PHY_GIGABIT) {
1859                         adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
1860                         adv &= ~ADVERTISE_1000FULL;
1861                         mii_rw(dev, np->phyaddr, MII_1000BT_CR, adv);
1862                 }
1863
1864                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1865                 bmcr |= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_FULLDPLX);
1866                 if (adv & (ADVERTISE_10FULL|ADVERTISE_100FULL))
1867                         bmcr |= BMCR_FULLDPLX;
1868                 if (adv & (ADVERTISE_100HALF|ADVERTISE_100FULL))
1869                         bmcr |= BMCR_SPEED100;
1870                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
1871
1872                 if (netif_running(dev)) {
1873                         /* Wait a bit and then reconfigure the nic. */
1874                         udelay(10);
1875                         nv_linkchange(dev);
1876                 }
1877         }
1878         spin_unlock_irq(&np->lock);
1879
1880         return 0;
1881 }
1882
1883 #define FORCEDETH_REGS_VER      1
1884 #define FORCEDETH_REGS_SIZE     0x400 /* 256 32-bit registers */
1885
1886 static int nv_get_regs_len(struct net_device *dev)
1887 {
1888         return FORCEDETH_REGS_SIZE;
1889 }
1890
1891 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
1892 {
1893         struct fe_priv *np = get_nvpriv(dev);
1894         u8 __iomem *base = get_hwbase(dev);
1895         u32 *rbuf = buf;
1896         int i;
1897
1898         regs->version = FORCEDETH_REGS_VER;
1899         spin_lock_irq(&np->lock);
1900         for (i=0;i<FORCEDETH_REGS_SIZE/sizeof(u32);i++)
1901                 rbuf[i] = readl(base + i*sizeof(u32));
1902         spin_unlock_irq(&np->lock);
1903 }
1904
1905 static int nv_nway_reset(struct net_device *dev)
1906 {
1907         struct fe_priv *np = get_nvpriv(dev);
1908         int ret;
1909
1910         spin_lock_irq(&np->lock);
1911         if (np->autoneg) {
1912                 int bmcr;
1913
1914                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1915                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1916                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
1917
1918                 ret = 0;
1919         } else {
1920                 ret = -EINVAL;
1921         }
1922         spin_unlock_irq(&np->lock);
1923
1924         return ret;
1925 }
1926
1927 static struct ethtool_ops ops = {
1928         .get_drvinfo = nv_get_drvinfo,
1929         .get_link = ethtool_op_get_link,
1930         .get_wol = nv_get_wol,
1931         .set_wol = nv_set_wol,
1932         .get_settings = nv_get_settings,
1933         .set_settings = nv_set_settings,
1934         .get_regs_len = nv_get_regs_len,
1935         .get_regs = nv_get_regs,
1936         .nway_reset = nv_nway_reset,
1937 };
1938
1939 static int nv_open(struct net_device *dev)
1940 {
1941         struct fe_priv *np = get_nvpriv(dev);
1942         u8 __iomem *base = get_hwbase(dev);
1943         int ret, oom, i;
1944
1945         dprintk(KERN_DEBUG "nv_open: begin\n");
1946
1947         /* 1) erase previous misconfiguration */
1948         /* 4.1-1: stop adapter: ignored, 4.3 seems to be overkill */
1949         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
1950         writel(0, base + NvRegMulticastAddrB);
1951         writel(0, base + NvRegMulticastMaskA);
1952         writel(0, base + NvRegMulticastMaskB);
1953         writel(0, base + NvRegPacketFilterFlags);
1954
1955         writel(0, base + NvRegTransmitterControl);
1956         writel(0, base + NvRegReceiverControl);
1957
1958         writel(0, base + NvRegAdapterControl);
1959
1960         /* 2) initialize descriptor rings */
1961         set_bufsize(dev);
1962         oom = nv_init_ring(dev);
1963
1964         writel(0, base + NvRegLinkSpeed);
1965         writel(0, base + NvRegUnknownTransmitterReg);
1966         nv_txrx_reset(dev);
1967         writel(0, base + NvRegUnknownSetupReg6);
1968
1969         np->in_shutdown = 0;
1970
1971         /* 3) set mac address */
1972         {
1973                 u32 mac[2];
1974
1975                 mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
1976                                 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
1977                 mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
1978
1979                 writel(mac[0], base + NvRegMacAddrA);
1980                 writel(mac[1], base + NvRegMacAddrB);
1981         }
1982
1983         /* 4) give hw rings */
1984         writel((u32) np->ring_addr, base + NvRegRxRingPhysAddr);
1985         writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
1986         writel( ((RX_RING-1) << NVREG_RINGSZ_RXSHIFT) + ((TX_RING-1) << NVREG_RINGSZ_TXSHIFT),
1987                 base + NvRegRingSizes);
1988
1989         /* 5) continue setup */
1990         writel(np->linkspeed, base + NvRegLinkSpeed);
1991         writel(NVREG_UNKSETUP3_VAL1, base + NvRegUnknownSetupReg3);
1992         writel(np->desc_ver, base + NvRegTxRxControl);
1993         pci_push(base);
1994         writel(NVREG_TXRXCTL_BIT1|np->desc_ver, base + NvRegTxRxControl);
1995         reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
1996                         NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
1997                         KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
1998
1999         writel(0, base + NvRegUnknownSetupReg4);
2000         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2001         writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
2002
2003         /* 6) continue setup */
2004         writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
2005         writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
2006         writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
2007         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2008
2009         writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
2010         get_random_bytes(&i, sizeof(i));
2011         writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed);
2012         writel(NVREG_UNKSETUP1_VAL, base + NvRegUnknownSetupReg1);
2013         writel(NVREG_UNKSETUP2_VAL, base + NvRegUnknownSetupReg2);
2014         writel(NVREG_POLL_DEFAULT, base + NvRegPollingInterval);
2015         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
2016         writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
2017                         base + NvRegAdapterControl);
2018         writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
2019         writel(NVREG_UNKSETUP4_VAL, base + NvRegUnknownSetupReg4);
2020         writel(NVREG_WAKEUPFLAGS_VAL, base + NvRegWakeUpFlags);
2021
2022         i = readl(base + NvRegPowerState);
2023         if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
2024                 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
2025
2026         pci_push(base);
2027         udelay(10);
2028         writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
2029
2030         writel(0, base + NvRegIrqMask);
2031         pci_push(base);
2032         writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
2033         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2034         pci_push(base);
2035
2036         ret = request_irq(dev->irq, &nv_nic_irq, SA_SHIRQ, dev->name, dev);
2037         if (ret)
2038                 goto out_drain;
2039
2040         /* ask for interrupts */
2041         writel(np->irqmask, base + NvRegIrqMask);
2042
2043         spin_lock_irq(&np->lock);
2044         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
2045         writel(0, base + NvRegMulticastAddrB);
2046         writel(0, base + NvRegMulticastMaskA);
2047         writel(0, base + NvRegMulticastMaskB);
2048         writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
2049         /* One manual link speed update: Interrupts are enabled, future link
2050          * speed changes cause interrupts and are handled by nv_link_irq().
2051          */
2052         {
2053                 u32 miistat;
2054                 miistat = readl(base + NvRegMIIStatus);
2055                 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
2056                 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
2057         }
2058         ret = nv_update_linkspeed(dev);
2059         nv_start_rx(dev);
2060         nv_start_tx(dev);
2061         netif_start_queue(dev);
2062         if (ret) {
2063                 netif_carrier_on(dev);
2064         } else {
2065                 printk("%s: no link during initialization.\n", dev->name);
2066                 netif_carrier_off(dev);
2067         }
2068         if (oom)
2069                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2070         spin_unlock_irq(&np->lock);
2071
2072         return 0;
2073 out_drain:
2074         drain_ring(dev);
2075         return ret;
2076 }
2077
2078 static int nv_close(struct net_device *dev)
2079 {
2080         struct fe_priv *np = get_nvpriv(dev);
2081         u8 __iomem *base;
2082
2083         spin_lock_irq(&np->lock);
2084         np->in_shutdown = 1;
2085         spin_unlock_irq(&np->lock);
2086         synchronize_irq(dev->irq);
2087
2088         del_timer_sync(&np->oom_kick);
2089         del_timer_sync(&np->nic_poll);
2090
2091         netif_stop_queue(dev);
2092         spin_lock_irq(&np->lock);
2093         nv_stop_tx(dev);
2094         nv_stop_rx(dev);
2095         nv_txrx_reset(dev);
2096
2097         /* disable interrupts on the nic or we will lock up */
2098         base = get_hwbase(dev);
2099         writel(0, base + NvRegIrqMask);
2100         pci_push(base);
2101         dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
2102
2103         spin_unlock_irq(&np->lock);
2104
2105         free_irq(dev->irq, dev);
2106
2107         drain_ring(dev);
2108
2109         if (np->wolenabled)
2110                 nv_start_rx(dev);
2111
2112         /* FIXME: power down nic */
2113
2114         return 0;
2115 }
2116
2117 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
2118 {
2119         struct net_device *dev;
2120         struct fe_priv *np;
2121         unsigned long addr;
2122         u8 __iomem *base;
2123         int err, i;
2124
2125         dev = alloc_etherdev(sizeof(struct fe_priv));
2126         err = -ENOMEM;
2127         if (!dev)
2128                 goto out;
2129
2130         np = get_nvpriv(dev);
2131         np->pci_dev = pci_dev;
2132         spin_lock_init(&np->lock);
2133         SET_MODULE_OWNER(dev);
2134         SET_NETDEV_DEV(dev, &pci_dev->dev);
2135
2136         init_timer(&np->oom_kick);
2137         np->oom_kick.data = (unsigned long) dev;
2138         np->oom_kick.function = &nv_do_rx_refill;       /* timer handler */
2139         init_timer(&np->nic_poll);
2140         np->nic_poll.data = (unsigned long) dev;
2141         np->nic_poll.function = &nv_do_nic_poll;        /* timer handler */
2142
2143         err = pci_enable_device(pci_dev);
2144         if (err) {
2145                 printk(KERN_INFO "forcedeth: pci_enable_dev failed (%d) for device %s\n",
2146                                 err, pci_name(pci_dev));
2147                 goto out_free;
2148         }
2149
2150         pci_set_master(pci_dev);
2151
2152         err = pci_request_regions(pci_dev, DRV_NAME);
2153         if (err < 0)
2154                 goto out_disable;
2155
2156         err = -EINVAL;
2157         addr = 0;
2158         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
2159                 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
2160                                 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
2161                                 pci_resource_len(pci_dev, i),
2162                                 pci_resource_flags(pci_dev, i));
2163                 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
2164                                 pci_resource_len(pci_dev, i) >= NV_PCI_REGSZ) {
2165                         addr = pci_resource_start(pci_dev, i);
2166                         break;
2167                 }
2168         }
2169         if (i == DEVICE_COUNT_RESOURCE) {
2170                 printk(KERN_INFO "forcedeth: Couldn't find register window for device %s.\n",
2171                                         pci_name(pci_dev));
2172                 goto out_relreg;
2173         }
2174
2175         /* handle different descriptor versions */
2176         np->desc_ver = DESC_VER_1;
2177         np->pkt_limit = NV_PKTLIMIT_1;
2178         if (id->driver_data & DEV_HAS_LARGEDESC) {
2179                 np->desc_ver = DESC_VER_2;
2180                 np->pkt_limit = NV_PKTLIMIT_2;
2181         }
2182
2183         err = -ENOMEM;
2184         np->base = ioremap(addr, NV_PCI_REGSZ);
2185         if (!np->base)
2186                 goto out_relreg;
2187         dev->base_addr = (unsigned long)np->base;
2188         dev->irq = pci_dev->irq;
2189         np->rx_ring = pci_alloc_consistent(pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING),
2190                                                 &np->ring_addr);
2191         if (!np->rx_ring)
2192                 goto out_unmap;
2193         np->tx_ring = &np->rx_ring[RX_RING];
2194
2195         dev->open = nv_open;
2196         dev->stop = nv_close;
2197         dev->hard_start_xmit = nv_start_xmit;
2198         dev->get_stats = nv_get_stats;
2199         dev->change_mtu = nv_change_mtu;
2200         dev->set_multicast_list = nv_set_multicast;
2201 #ifdef CONFIG_NET_POLL_CONTROLLER
2202         dev->poll_controller = nv_poll_controller;
2203 #endif
2204         SET_ETHTOOL_OPS(dev, &ops);
2205         dev->tx_timeout = nv_tx_timeout;
2206         dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
2207
2208         pci_set_drvdata(pci_dev, dev);
2209
2210         /* read the mac address */
2211         base = get_hwbase(dev);
2212         np->orig_mac[0] = readl(base + NvRegMacAddrA);
2213         np->orig_mac[1] = readl(base + NvRegMacAddrB);
2214
2215         dev->dev_addr[0] = (np->orig_mac[1] >>  8) & 0xff;
2216         dev->dev_addr[1] = (np->orig_mac[1] >>  0) & 0xff;
2217         dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
2218         dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
2219         dev->dev_addr[4] = (np->orig_mac[0] >>  8) & 0xff;
2220         dev->dev_addr[5] = (np->orig_mac[0] >>  0) & 0xff;
2221
2222         if (!is_valid_ether_addr(dev->dev_addr)) {
2223                 /*
2224                  * Bad mac address. At least one bios sets the mac address
2225                  * to 01:23:45:67:89:ab
2226                  */
2227                 printk(KERN_ERR "%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
2228                         pci_name(pci_dev),
2229                         dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
2230                         dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
2231                 printk(KERN_ERR "Please complain to your hardware vendor. Switching to a random MAC.\n");
2232                 dev->dev_addr[0] = 0x00;
2233                 dev->dev_addr[1] = 0x00;
2234                 dev->dev_addr[2] = 0x6c;
2235                 get_random_bytes(&dev->dev_addr[3], 3);
2236         }
2237
2238         dprintk(KERN_DEBUG "%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev),
2239                         dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
2240                         dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
2241
2242         /* disable WOL */
2243         writel(0, base + NvRegWakeUpFlags);
2244         np->wolenabled = 0;
2245
2246         if (np->desc_ver == DESC_VER_1) {
2247                 np->tx_flags = NV_TX_LASTPACKET|NV_TX_VALID;
2248         } else {
2249                 np->tx_flags = NV_TX2_LASTPACKET|NV_TX2_VALID;
2250         }
2251         np->irqmask = NVREG_IRQMASK_WANTED;
2252         if (id->driver_data & DEV_NEED_TIMERIRQ)
2253                 np->irqmask |= NVREG_IRQ_TIMER;
2254         if (id->driver_data & DEV_NEED_LINKTIMER) {
2255                 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
2256                 np->need_linktimer = 1;
2257                 np->link_timeout = jiffies + LINK_TIMEOUT;
2258         } else {
2259                 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
2260                 np->need_linktimer = 0;
2261         }
2262
2263         /* find a suitable phy */
2264         for (i = 1; i < 32; i++) {
2265                 int id1, id2;
2266
2267                 spin_lock_irq(&np->lock);
2268                 id1 = mii_rw(dev, i, MII_PHYSID1, MII_READ);
2269                 spin_unlock_irq(&np->lock);
2270                 if (id1 < 0 || id1 == 0xffff)
2271                         continue;
2272                 spin_lock_irq(&np->lock);
2273                 id2 = mii_rw(dev, i, MII_PHYSID2, MII_READ);
2274                 spin_unlock_irq(&np->lock);
2275                 if (id2 < 0 || id2 == 0xffff)
2276                         continue;
2277
2278                 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
2279                 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
2280                 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
2281                                 pci_name(pci_dev), id1, id2, i);
2282                 np->phyaddr = i;
2283                 np->phy_oui = id1 | id2;
2284                 break;
2285         }
2286         if (i == 32) {
2287                 /* PHY in isolate mode? No phy attached and user wants to
2288                  * test loopback? Very odd, but can be correct.
2289                  */
2290                 printk(KERN_INFO "%s: open: Could not find a valid PHY.\n",
2291                                 pci_name(pci_dev));
2292         }
2293
2294         if (i != 32) {
2295                 /* reset it */
2296                 phy_init(dev);
2297         }
2298
2299         /* set default link speed settings */
2300         np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2301         np->duplex = 0;
2302         np->autoneg = 1;
2303
2304         err = register_netdev(dev);
2305         if (err) {
2306                 printk(KERN_INFO "forcedeth: unable to register netdev: %d\n", err);
2307                 goto out_freering;
2308         }
2309         printk(KERN_INFO "%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n",
2310                         dev->name, pci_dev->subsystem_vendor, pci_dev->subsystem_device,
2311                         pci_name(pci_dev));
2312
2313         return 0;
2314
2315 out_freering:
2316         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING),
2317                                 np->rx_ring, np->ring_addr);
2318         pci_set_drvdata(pci_dev, NULL);
2319 out_unmap:
2320         iounmap(get_hwbase(dev));
2321 out_relreg:
2322         pci_release_regions(pci_dev);
2323 out_disable:
2324         pci_disable_device(pci_dev);
2325 out_free:
2326         free_netdev(dev);
2327 out:
2328         return err;
2329 }
2330
2331 static void __devexit nv_remove(struct pci_dev *pci_dev)
2332 {
2333         struct net_device *dev = pci_get_drvdata(pci_dev);
2334         struct fe_priv *np = get_nvpriv(dev);
2335         u8 __iomem *base = get_hwbase(dev);
2336
2337         unregister_netdev(dev);
2338
2339         /* special op: write back the misordered MAC address - otherwise
2340          * the next nv_probe would see a wrong address.
2341          */
2342         writel(np->orig_mac[0], base + NvRegMacAddrA);
2343         writel(np->orig_mac[1], base + NvRegMacAddrB);
2344
2345         /* free all structures */
2346         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING), np->rx_ring, np->ring_addr);
2347         iounmap(get_hwbase(dev));
2348         pci_release_regions(pci_dev);
2349         pci_disable_device(pci_dev);
2350         free_netdev(dev);
2351         pci_set_drvdata(pci_dev, NULL);
2352 }
2353
2354 static struct pci_device_id pci_tbl[] = {
2355         {       /* nForce Ethernet Controller */
2356                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1),
2357                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2358         },
2359         {       /* nForce2 Ethernet Controller */
2360                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2),
2361                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2362         },
2363         {       /* nForce3 Ethernet Controller */
2364                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3),
2365                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2366         },
2367         {       /* nForce3 Ethernet Controller */
2368                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4),
2369                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
2370         },
2371         {       /* nForce3 Ethernet Controller */
2372                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5),
2373                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
2374         },
2375         {       /* nForce3 Ethernet Controller */
2376                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6),
2377                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
2378         },
2379         {       /* nForce3 Ethernet Controller */
2380                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7),
2381                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
2382         },
2383         {       /* CK804 Ethernet Controller */
2384                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
2385                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
2386         },
2387         {       /* CK804 Ethernet Controller */
2388                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
2389                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
2390         },
2391         {       /* MCP04 Ethernet Controller */
2392                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
2393                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
2394         },
2395         {       /* MCP04 Ethernet Controller */
2396                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
2397                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
2398         },
2399         {       /* MCP51 Ethernet Controller */
2400                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
2401                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2402         },
2403         {       /* MCP51 Ethernet Controller */
2404                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
2405                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2406         },
2407         {       /* MCP55 Ethernet Controller */
2408                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
2409                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
2410         },
2411         {       /* MCP55 Ethernet Controller */
2412                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
2413                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
2414         },
2415         {0,},
2416 };
2417
2418 static struct pci_driver driver = {
2419         .name = "forcedeth",
2420         .id_table = pci_tbl,
2421         .probe = nv_probe,
2422         .remove = __devexit_p(nv_remove),
2423 };
2424
2425
2426 static int __init init_nic(void)
2427 {
2428         printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION);
2429         return pci_module_init(&driver);
2430 }
2431
2432 static void __exit exit_nic(void)
2433 {
2434         pci_unregister_driver(&driver);
2435 }
2436
2437 module_param(max_interrupt_work, int, 0);
2438 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
2439
2440 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
2441 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
2442 MODULE_LICENSE("GPL");
2443
2444 MODULE_DEVICE_TABLE(pci, pci_tbl);
2445
2446 module_init(init_nic);
2447 module_exit(exit_nic);