drivers/net/gianfar.c

   1 /*
   2  * drivers/net/gianfar.c
   3  *
   4  * Gianfar Ethernet Driver
   5  * This driver is designed for the non-CPM ethernet controllers
   6  * on the 85xx and 83xx family of integrated processors
   7  * Based on 8260_io/fcc_enet.c
   8  *
   9  * Author: Andy Fleming
  10  * Maintainer: Kumar Gala
  11  *
  12  * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
  13  * Copyright (c) 2007 MontaVista Software, Inc.
  14  *
  15  * This program is free software; you can redistribute  it and/or modify it
  16  * under  the terms of  the GNU General  Public License as published by the
  17  * Free Software Foundation;  either version 2 of the  License, or (at your
  18  * option) any later version.
  19  *
  20  *  Gianfar:  AKA Lambda Draconis, "Dragon"
  21  *  RA 11 31 24.2
  22  *  Dec +69 19 52
  23  *  V 3.84
  24  *  B-V +1.62
  25  *
  26  *  Theory of operation
  27  *
  28  *  The driver is initialized through platform_device.  Structures which
  29  *  define the configuration needed by the board are defined in a
  30  *  board structure in arch/ppc/platforms (though I do not
  31  *  discount the possibility that other architectures could one
  32  *  day be supported.
  33  *
  34  *  The Gianfar Ethernet Controller uses a ring of buffer
  35  *  descriptors.  The beginning is indicated by a register
  36  *  pointing to the physical address of the start of the ring.
  37  *  The end is determined by a "wrap" bit being set in the
  38  *  last descriptor of the ring.
  39  *
  40  *  When a packet is received, the RXF bit in the
  41  *  IEVENT register is set, triggering an interrupt when the
  42  *  corresponding bit in the IMASK register is also set (if
  43  *  interrupt coalescing is active, then the interrupt may not
  44  *  happen immediately, but will wait until either a set number
  45  *  of frames or amount of time have passed).  In NAPI, the
  46  *  interrupt handler will signal there is work to be done, and
  47  *  exit.  Without NAPI, the packet(s) will be handled
  48  *  immediately.  Both methods will start at the last known empty
  49  *  descriptor, and process every subsequent descriptor until there
  50  *  are none left with data (NAPI will stop after a set number of
  51  *  packets to give time to other tasks, but will eventually
  52  *  process all the packets).  The data arrives inside a
  53  *  pre-allocated skb, and so after the skb is passed up to the
  54  *  stack, a new skb must be allocated, and the address field in
  55  *  the buffer descriptor must be updated to indicate this new
  56  *  skb.
  57  *
  58  *  When the kernel requests that a packet be transmitted, the
  59  *  driver starts where it left off last time, and points the
  60  *  descriptor at the buffer which was passed in.  The driver
  61  *  then informs the DMA engine that there are packets ready to
  62  *  be transmitted.  Once the controller is finished transmitting
  63  *  the packet, an interrupt may be triggered (under the same
  64  *  conditions as for reception, but depending on the TXF bit).
  65  *  The driver then cleans up the buffer.
  66  */
  67
  68 #include <linux/kernel.h>
  69 #include <linux/string.h>
  70 #include <linux/errno.h>
  71 #include <linux/unistd.h>
  72 #include <linux/slab.h>
  73 #include <linux/interrupt.h>
  74 #include <linux/init.h>
  75 #include <linux/delay.h>
  76 #include <linux/netdevice.h>
  77 #include <linux/etherdevice.h>
  78 #include <linux/skbuff.h>
  79 #include <linux/if_vlan.h>
  80 #include <linux/spinlock.h>
  81 #include <linux/mm.h>
  82 #include <linux/platform_device.h>
  83 #include <linux/ip.h>
  84 #include <linux/tcp.h>
  85 #include <linux/udp.h>
  86 #include <linux/in.h>
  87
  88 #include <asm/io.h>
  89 #include <asm/irq.h>
  90 #include <asm/uaccess.h>
  91 #include <linux/module.h>
  92 #include <linux/dma-mapping.h>
  93 #include <linux/crc32.h>
  94 #include <linux/mii.h>
  95 #include <linux/phy.h>
  96
  97 #include "gianfar.h"
  98 #include "gianfar_mii.h"
  99
 100 #define TX_TIMEOUT      (1*HZ)
 101 #define SKB_ALLOC_TIMEOUT 1000000
 102 #undef BRIEF_GFAR_ERRORS
 103 #undef VERBOSE_GFAR_ERRORS
 104
 105 #ifdef CONFIG_GFAR_NAPI
 106 #define RECEIVE(x) netif_receive_skb(x)
 107 #else
 108 #define RECEIVE(x) netif_rx(x)
 109 #endif
 110
 111 const char gfar_driver_name[] = "Gianfar Ethernet";
 112 const char gfar_driver_version[] = "1.3";
 113
 114 static int gfar_enet_open(struct net_device *dev);
 115 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
 116 static void gfar_timeout(struct net_device *dev);
 117 static int gfar_close(struct net_device *dev);
 118 struct sk_buff *gfar_new_skb(struct net_device *dev, struct rxbd8 *bdp);
 119 static struct net_device_stats *gfar_get_stats(struct net_device *dev);
 120 static int gfar_set_mac_address(struct net_device *dev);
 121 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
 122 static irqreturn_t gfar_error(int irq, void *dev_id);
 123 static irqreturn_t gfar_transmit(int irq, void *dev_id);
 124 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
 125 static void adjust_link(struct net_device *dev);
 126 static void init_registers(struct net_device *dev);
 127 static int init_phy(struct net_device *dev);
 128 static int gfar_probe(struct platform_device *pdev);
 129 static int gfar_remove(struct platform_device *pdev);
 130 static void free_skb_resources(struct gfar_private *priv);
 131 static void gfar_set_multi(struct net_device *dev);
 132 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
 133 static void gfar_configure_serdes(struct net_device *dev);
 134 extern int gfar_local_mdio_write(struct gfar_mii *regs, int mii_id, int regnum, u16 value);
 135 extern int gfar_local_mdio_read(struct gfar_mii *regs, int mii_id, int regnum);
 136 #ifdef CONFIG_GFAR_NAPI
 137 static int gfar_poll(struct napi_struct *napi, int budget);
 138 #endif
 139 #ifdef CONFIG_NET_POLL_CONTROLLER
 140 static void gfar_netpoll(struct net_device *dev);
 141 #endif
 142 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit);
 143 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, int length);
 144 static void gfar_vlan_rx_register(struct net_device *netdev,
 145                                 struct vlan_group *grp);
 146 void gfar_halt(struct net_device *dev);
 147 void gfar_start(struct net_device *dev);
 148 static void gfar_clear_exact_match(struct net_device *dev);
 149 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
 150
 151 extern const struct ethtool_ops gfar_ethtool_ops;
 152
 153 MODULE_AUTHOR("Freescale Semiconductor, Inc");
 154 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
 155 MODULE_LICENSE("GPL");
 156
 157 /* Returns 1 if incoming frames use an FCB */
 158 static inline int gfar_uses_fcb(struct gfar_private *priv)
 159 {
 160         return (priv->vlan_enable || priv->rx_csum_enable);
 161 }
 162
 163 /* Set up the ethernet device structure, private data,
 164  * and anything else we need before we start */
 165 static int gfar_probe(struct platform_device *pdev)
 166 {
 167         u32 tempval;
 168         struct net_device *dev = NULL;
 169         struct gfar_private *priv = NULL;
 170         struct gianfar_platform_data *einfo;
 171         struct resource *r;
 172         int idx;
 173         int err = 0;
 174
 175         einfo = (struct gianfar_platform_data *) pdev->dev.platform_data;
 176
 177         if (NULL == einfo) {
 178                 printk(KERN_ERR "gfar %d: Missing additional data!\n",
 179                        pdev->id);
 180
 181                 return -ENODEV;
 182         }
 183
 184         /* Create an ethernet device instance */
 185         dev = alloc_etherdev(sizeof (*priv));
 186
 187         if (NULL == dev)
 188                 return -ENOMEM;
 189
 190         priv = netdev_priv(dev);
 191         priv->dev = dev;
 192
 193         /* Set the info in the priv to the current info */
 194         priv->einfo = einfo;
 195
 196         /* fill out IRQ fields */
 197         if (einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
 198                 priv->interruptTransmit = platform_get_irq_byname(pdev, "tx");
 199                 priv->interruptReceive = platform_get_irq_byname(pdev, "rx");
 200                 priv->interruptError = platform_get_irq_byname(pdev, "error");
 201                 if (priv->interruptTransmit < 0 || priv->interruptReceive < 0 || priv->interruptError < 0)
 202                         goto regs_fail;
 203         } else {
 204                 priv->interruptTransmit = platform_get_irq(pdev, 0);
 205                 if (priv->interruptTransmit < 0)
 206                         goto regs_fail;
 207         }
 208
 209         /* get a pointer to the register memory */
 210         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 211         priv->regs = ioremap(r->start, sizeof (struct gfar));
 212
 213         if (NULL == priv->regs) {
 214                 err = -ENOMEM;
 215                 goto regs_fail;
 216         }
 217
 218         spin_lock_init(&priv->txlock);
 219         spin_lock_init(&priv->rxlock);
 220
 221         platform_set_drvdata(pdev, dev);
 222
 223         /* Stop the DMA engine now, in case it was running before */
 224         /* (The firmware could have used it, and left it running). */
 225         /* To do this, we write Graceful Receive Stop and Graceful */
 226         /* Transmit Stop, and then wait until the corresponding bits */
 227         /* in IEVENT indicate the stops have completed. */
 228         tempval = gfar_read(&priv->regs->dmactrl);
 229         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
 230         gfar_write(&priv->regs->dmactrl, tempval);
 231
 232         tempval = gfar_read(&priv->regs->dmactrl);
 233         tempval |= (DMACTRL_GRS | DMACTRL_GTS);
 234         gfar_write(&priv->regs->dmactrl, tempval);
 235
 236         while (!(gfar_read(&priv->regs->ievent) & (IEVENT_GRSC | IEVENT_GTSC)))
 237                 cpu_relax();
 238
 239         /* Reset MAC layer */
 240         gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
 241
 242         tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
 243         gfar_write(&priv->regs->maccfg1, tempval);
 244
 245         /* Initialize MACCFG2. */
 246         gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS);
 247
 248         /* Initialize ECNTRL */
 249         gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS);
 250
 251         /* Copy the station address into the dev structure, */
 252         memcpy(dev->dev_addr, einfo->mac_addr, MAC_ADDR_LEN);
 253
 254         /* Set the dev->base_addr to the gfar reg region */
 255         dev->base_addr = (unsigned long) (priv->regs);
 256
 257         SET_NETDEV_DEV(dev, &pdev->dev);
 258
 259         /* Fill in the dev structure */
 260         dev->open = gfar_enet_open;
 261         dev->hard_start_xmit = gfar_start_xmit;
 262         dev->tx_timeout = gfar_timeout;
 263         dev->watchdog_timeo = TX_TIMEOUT;
 264         netif_napi_add(dev, &priv->napi, gfar_poll, GFAR_DEV_WEIGHT);
 265 #ifdef CONFIG_NET_POLL_CONTROLLER
 266         dev->poll_controller = gfar_netpoll;
 267 #endif
 268         dev->stop = gfar_close;
 269         dev->get_stats = gfar_get_stats;
 270         dev->change_mtu = gfar_change_mtu;
 271         dev->mtu = 1500;
 272         dev->set_multicast_list = gfar_set_multi;
 273
 274         dev->ethtool_ops = &gfar_ethtool_ops;
 275
 276         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
 277                 priv->rx_csum_enable = 1;
 278                 dev->features |= NETIF_F_IP_CSUM;
 279         } else
 280                 priv->rx_csum_enable = 0;
 281
 282         priv->vlgrp = NULL;
 283
 284         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
 285                 dev->vlan_rx_register = gfar_vlan_rx_register;
 286
 287                 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
 288
 289                 priv->vlan_enable = 1;
 290         }
 291
 292         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
 293                 priv->extended_hash = 1;
 294                 priv->hash_width = 9;
 295
 296                 priv->hash_regs[0] = &priv->regs->igaddr0;
 297                 priv->hash_regs[1] = &priv->regs->igaddr1;
 298                 priv->hash_regs[2] = &priv->regs->igaddr2;
 299                 priv->hash_regs[3] = &priv->regs->igaddr3;
 300                 priv->hash_regs[4] = &priv->regs->igaddr4;
 301                 priv->hash_regs[5] = &priv->regs->igaddr5;
 302                 priv->hash_regs[6] = &priv->regs->igaddr6;
 303                 priv->hash_regs[7] = &priv->regs->igaddr7;
 304                 priv->hash_regs[8] = &priv->regs->gaddr0;
 305                 priv->hash_regs[9] = &priv->regs->gaddr1;
 306                 priv->hash_regs[10] = &priv->regs->gaddr2;
 307                 priv->hash_regs[11] = &priv->regs->gaddr3;
 308                 priv->hash_regs[12] = &priv->regs->gaddr4;
 309                 priv->hash_regs[13] = &priv->regs->gaddr5;
 310                 priv->hash_regs[14] = &priv->regs->gaddr6;
 311                 priv->hash_regs[15] = &priv->regs->gaddr7;
 312
 313         } else {
 314                 priv->extended_hash = 0;
 315                 priv->hash_width = 8;
 316
 317                 priv->hash_regs[0] = &priv->regs->gaddr0;
 318                 priv->hash_regs[1] = &priv->regs->gaddr1;
 319                 priv->hash_regs[2] = &priv->regs->gaddr2;
 320                 priv->hash_regs[3] = &priv->regs->gaddr3;
 321                 priv->hash_regs[4] = &priv->regs->gaddr4;
 322                 priv->hash_regs[5] = &priv->regs->gaddr5;
 323                 priv->hash_regs[6] = &priv->regs->gaddr6;
 324                 priv->hash_regs[7] = &priv->regs->gaddr7;
 325         }
 326
 327         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
 328                 priv->padding = DEFAULT_PADDING;
 329         else
 330                 priv->padding = 0;
 331
 332         if (dev->features & NETIF_F_IP_CSUM)
 333                 dev->hard_header_len += GMAC_FCB_LEN;
 334
 335         priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
 336         priv->tx_ring_size = DEFAULT_TX_RING_SIZE;
 337         priv->rx_ring_size = DEFAULT_RX_RING_SIZE;
 338
 339         priv->txcoalescing = DEFAULT_TX_COALESCE;
 340         priv->txcount = DEFAULT_TXCOUNT;
 341         priv->txtime = DEFAULT_TXTIME;
 342         priv->rxcoalescing = DEFAULT_RX_COALESCE;
 343         priv->rxcount = DEFAULT_RXCOUNT;
 344         priv->rxtime = DEFAULT_RXTIME;
 345
 346         /* Enable most messages by default */
 347         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
 348
 349         err = register_netdev(dev);
 350
 351         if (err) {
 352                 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
 353                                 dev->name);
 354                 goto register_fail;
 355         }
 356
 357         /* Create all the sysfs files */
 358         gfar_init_sysfs(dev);
 359
 360         /* Print out the device info */
 361         printk(KERN_INFO DEVICE_NAME, dev->name);
 362         for (idx = 0; idx < 6; idx++)
 363                 printk("%2.2x%c", dev->dev_addr[idx], idx == 5 ? ' ' : ':');
 364         printk("\n");
 365
 366         /* Even more device info helps when determining which kernel */
 367         /* provided which set of benchmarks. */
 368 #ifdef CONFIG_GFAR_NAPI
 369         printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
 370 #else
 371         printk(KERN_INFO "%s: Running with NAPI disabled\n", dev->name);
 372 #endif
 373         printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n",
 374                dev->name, priv->rx_ring_size, priv->tx_ring_size);
 375
 376         return 0;
 377
 378 register_fail:
 379         iounmap(priv->regs);
 380 regs_fail:
 381         free_netdev(dev);
 382         return err;
 383 }
 384
 385 static int gfar_remove(struct platform_device *pdev)
 386 {
 387         struct net_device *dev = platform_get_drvdata(pdev);
 388         struct gfar_private *priv = netdev_priv(dev);
 389
 390         platform_set_drvdata(pdev, NULL);
 391
 392         iounmap(priv->regs);
 393         free_netdev(dev);
 394
 395         return 0;
 396 }
 397
 398
 399 /* Reads the controller's registers to determine what interface
 400  * connects it to the PHY.
 401  */
 402 static phy_interface_t gfar_get_interface(struct net_device *dev)
 403 {
 404         struct gfar_private *priv = netdev_priv(dev);
 405         u32 ecntrl = gfar_read(&priv->regs->ecntrl);
 406
 407         if (ecntrl & ECNTRL_SGMII_MODE)
 408                 return PHY_INTERFACE_MODE_SGMII;
 409
 410         if (ecntrl & ECNTRL_TBI_MODE) {
 411                 if (ecntrl & ECNTRL_REDUCED_MODE)
 412                         return PHY_INTERFACE_MODE_RTBI;
 413                 else
 414                         return PHY_INTERFACE_MODE_TBI;
 415         }
 416
 417         if (ecntrl & ECNTRL_REDUCED_MODE) {
 418                 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
 419                         return PHY_INTERFACE_MODE_RMII;
 420                 else {
 421                         phy_interface_t interface = priv->einfo->interface;
 422
 423                         /*
 424                          * This isn't autodetected right now, so it must
 425                          * be set by the device tree or platform code.
 426                          */
 427                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
 428                                 return PHY_INTERFACE_MODE_RGMII_ID;
 429
 430                         return PHY_INTERFACE_MODE_RGMII;
 431                 }
 432         }
 433
 434         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
 435                 return PHY_INTERFACE_MODE_GMII;
 436
 437         return PHY_INTERFACE_MODE_MII;
 438 }
 439
 440
 441 /* Initializes driver's PHY state, and attaches to the PHY.
 442  * Returns 0 on success.
 443  */
 444 static int init_phy(struct net_device *dev)
 445 {
 446         struct gfar_private *priv = netdev_priv(dev);
 447         uint gigabit_support =
 448                 priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
 449                 SUPPORTED_1000baseT_Full : 0;
 450         struct phy_device *phydev;
 451         char phy_id[BUS_ID_SIZE];
 452         phy_interface_t interface;
 453
 454         priv->oldlink = 0;
 455         priv->oldspeed = 0;
 456         priv->oldduplex = -1;
 457
 458         snprintf(phy_id, BUS_ID_SIZE, PHY_ID_FMT, priv->einfo->bus_id, priv->einfo->phy_id);
 459
 460         interface = gfar_get_interface(dev);
 461
 462         phydev = phy_connect(dev, phy_id, &adjust_link, 0, interface);
 463
 464         if (interface == PHY_INTERFACE_MODE_SGMII)
 465                 gfar_configure_serdes(dev);
 466
 467         if (IS_ERR(phydev)) {
 468                 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
 469                 return PTR_ERR(phydev);
 470         }
 471
 472         /* Remove any features not supported by the controller */
 473         phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
 474         phydev->advertising = phydev->supported;
 475
 476         priv->phydev = phydev;
 477
 478         return 0;
 479 }
 480
 481 static void gfar_configure_serdes(struct net_device *dev)
 482 {
 483         struct gfar_private *priv = netdev_priv(dev);
 484         struct gfar_mii __iomem *regs =
 485                         (void __iomem *)&priv->regs->gfar_mii_regs;
 486
 487         /* Initialise TBI i/f to communicate with serdes (lynx phy) */
 488
 489         /* Single clk mode, mii mode off(for aerdes communication) */
 490         gfar_local_mdio_write(regs, TBIPA_VALUE, MII_TBICON, TBICON_CLK_SELECT);
 491
 492         /* Supported pause and full-duplex, no half-duplex */
 493         gfar_local_mdio_write(regs, TBIPA_VALUE, MII_ADVERTISE,
 494                         ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
 495                         ADVERTISE_1000XPSE_ASYM);
 496
 497         /* ANEG enable, restart ANEG, full duplex mode, speed[1] set */
 498         gfar_local_mdio_write(regs, TBIPA_VALUE, MII_BMCR, BMCR_ANENABLE |
 499                         BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
 500 }
 501
 502 static void init_registers(struct net_device *dev)
 503 {
 504         struct gfar_private *priv = netdev_priv(dev);
 505
 506         /* Clear IEVENT */
 507         gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR);
 508
 509         /* Initialize IMASK */
 510         gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR);
 511
 512         /* Init hash registers to zero */
 513         gfar_write(&priv->regs->igaddr0, 0);
 514         gfar_write(&priv->regs->igaddr1, 0);
 515         gfar_write(&priv->regs->igaddr2, 0);
 516         gfar_write(&priv->regs->igaddr3, 0);
 517         gfar_write(&priv->regs->igaddr4, 0);
 518         gfar_write(&priv->regs->igaddr5, 0);
 519         gfar_write(&priv->regs->igaddr6, 0);
 520         gfar_write(&priv->regs->igaddr7, 0);
 521
 522         gfar_write(&priv->regs->gaddr0, 0);
 523         gfar_write(&priv->regs->gaddr1, 0);
 524         gfar_write(&priv->regs->gaddr2, 0);
 525         gfar_write(&priv->regs->gaddr3, 0);
 526         gfar_write(&priv->regs->gaddr4, 0);
 527         gfar_write(&priv->regs->gaddr5, 0);
 528         gfar_write(&priv->regs->gaddr6, 0);
 529         gfar_write(&priv->regs->gaddr7, 0);
 530
 531         /* Zero out the rmon mib registers if it has them */
 532         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
 533                 memset_io(&(priv->regs->rmon), 0, sizeof (struct rmon_mib));
 534
 535                 /* Mask off the CAM interrupts */
 536                 gfar_write(&priv->regs->rmon.cam1, 0xffffffff);
 537                 gfar_write(&priv->regs->rmon.cam2, 0xffffffff);
 538         }
 539
 540         /* Initialize the max receive buffer length */
 541         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
 542
 543         /* Initialize the Minimum Frame Length Register */
 544         gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS);
 545
 546         /* Assign the TBI an address which won't conflict with the PHYs */
 547         gfar_write(&priv->regs->tbipa, TBIPA_VALUE);
 548 }
 549
 550
 551 /* Halt the receive and transmit queues */
 552 void gfar_halt(struct net_device *dev)
 553 {
 554         struct gfar_private *priv = netdev_priv(dev);
 555         struct gfar __iomem *regs = priv->regs;
 556         u32 tempval;
 557
 558         /* Mask all interrupts */
 559         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
 560
 561         /* Clear all interrupts */
 562         gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
 563
 564         /* Stop the DMA, and wait for it to stop */
 565         tempval = gfar_read(&priv->regs->dmactrl);
 566         if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
 567             != (DMACTRL_GRS | DMACTRL_GTS)) {
 568                 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
 569                 gfar_write(&priv->regs->dmactrl, tempval);
 570
 571                 while (!(gfar_read(&priv->regs->ievent) &
 572                          (IEVENT_GRSC | IEVENT_GTSC)))
 573                         cpu_relax();
 574         }
 575
 576         /* Disable Rx and Tx */
 577         tempval = gfar_read(&regs->maccfg1);
 578         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
 579         gfar_write(&regs->maccfg1, tempval);
 580 }
 581
 582 void stop_gfar(struct net_device *dev)
 583 {
 584         struct gfar_private *priv = netdev_priv(dev);
 585         struct gfar __iomem *regs = priv->regs;
 586         unsigned long flags;
 587
 588         phy_stop(priv->phydev);
 589
 590         /* Lock it down */
 591         spin_lock_irqsave(&priv->txlock, flags);
 592         spin_lock(&priv->rxlock);
 593
 594         gfar_halt(dev);
 595
 596         spin_unlock(&priv->rxlock);
 597         spin_unlock_irqrestore(&priv->txlock, flags);
 598
 599         /* Free the IRQs */
 600         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
 601                 free_irq(priv->interruptError, dev);
 602                 free_irq(priv->interruptTransmit, dev);
 603                 free_irq(priv->interruptReceive, dev);
 604         } else {
 605                 free_irq(priv->interruptTransmit, dev);
 606         }
 607
 608         free_skb_resources(priv);
 609
 610         dma_free_coherent(NULL,
 611                         sizeof(struct txbd8)*priv->tx_ring_size
 612                         + sizeof(struct rxbd8)*priv->rx_ring_size,
 613                         priv->tx_bd_base,
 614                         gfar_read(&regs->tbase0));
 615 }
 616
 617 /* If there are any tx skbs or rx skbs still around, free them.
 618  * Then free tx_skbuff and rx_skbuff */
 619 static void free_skb_resources(struct gfar_private *priv)
 620 {
 621         struct rxbd8 *rxbdp;
 622         struct txbd8 *txbdp;
 623         int i;
 624
 625         /* Go through all the buffer descriptors and free their data buffers */
 626         txbdp = priv->tx_bd_base;
 627
 628         for (i = 0; i < priv->tx_ring_size; i++) {
 629
 630                 if (priv->tx_skbuff[i]) {
 631                         dma_unmap_single(NULL, txbdp->bufPtr,
 632                                         txbdp->length,
 633                                         DMA_TO_DEVICE);
 634                         dev_kfree_skb_any(priv->tx_skbuff[i]);
 635                         priv->tx_skbuff[i] = NULL;
 636                 }
 637         }
 638
 639         kfree(priv->tx_skbuff);
 640
 641         rxbdp = priv->rx_bd_base;
 642
 643         /* rx_skbuff is not guaranteed to be allocated, so only
 644          * free it and its contents if it is allocated */
 645         if(priv->rx_skbuff != NULL) {
 646                 for (i = 0; i < priv->rx_ring_size; i++) {
 647                         if (priv->rx_skbuff[i]) {
 648                                 dma_unmap_single(NULL, rxbdp->bufPtr,
 649                                                 priv->rx_buffer_size,
 650                                                 DMA_FROM_DEVICE);
 651
 652                                 dev_kfree_skb_any(priv->rx_skbuff[i]);
 653                                 priv->rx_skbuff[i] = NULL;
 654                         }
 655
 656                         rxbdp->status = 0;
 657                         rxbdp->length = 0;
 658                         rxbdp->bufPtr = 0;
 659
 660                         rxbdp++;
 661                 }
 662
 663                 kfree(priv->rx_skbuff);
 664         }
 665 }
 666
 667 void gfar_start(struct net_device *dev)
 668 {
 669         struct gfar_private *priv = netdev_priv(dev);
 670         struct gfar __iomem *regs = priv->regs;
 671         u32 tempval;
 672
 673         /* Enable Rx and Tx in MACCFG1 */
 674         tempval = gfar_read(&regs->maccfg1);
 675         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
 676         gfar_write(&regs->maccfg1, tempval);
 677
 678         /* Initialize DMACTRL to have WWR and WOP */
 679         tempval = gfar_read(&priv->regs->dmactrl);
 680         tempval |= DMACTRL_INIT_SETTINGS;
 681         gfar_write(&priv->regs->dmactrl, tempval);
 682
 683         /* Make sure we aren't stopped */
 684         tempval = gfar_read(&priv->regs->dmactrl);
 685         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
 686         gfar_write(&priv->regs->dmactrl, tempval);
 687
 688         /* Clear THLT/RHLT, so that the DMA starts polling now */
 689         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT);
 690         gfar_write(&regs->rstat, RSTAT_CLEAR_RHALT);
 691
 692         /* Unmask the interrupts we look for */
 693         gfar_write(&regs->imask, IMASK_DEFAULT);
 694 }
 695
 696 /* Bring the controller up and running */
 697 int startup_gfar(struct net_device *dev)
 698 {
 699         struct txbd8 *txbdp;
 700         struct rxbd8 *rxbdp;
 701         dma_addr_t addr;
 702         unsigned long vaddr;
 703         int i;
 704         struct gfar_private *priv = netdev_priv(dev);
 705         struct gfar __iomem *regs = priv->regs;
 706         int err = 0;
 707         u32 rctrl = 0;
 708         u32 attrs = 0;
 709
 710         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
 711
 712         /* Allocate memory for the buffer descriptors */
 713         vaddr = (unsigned long) dma_alloc_coherent(NULL,
 714                         sizeof (struct txbd8) * priv->tx_ring_size +
 715                         sizeof (struct rxbd8) * priv->rx_ring_size,
 716                         &addr, GFP_KERNEL);
 717
 718         if (vaddr == 0) {
 719                 if (netif_msg_ifup(priv))
 720                         printk(KERN_ERR "%s: Could not allocate buffer descriptors!\n",
 721                                         dev->name);
 722                 return -ENOMEM;
 723         }
 724
 725         priv->tx_bd_base = (struct txbd8 *) vaddr;
 726
 727         /* enet DMA only understands physical addresses */
 728         gfar_write(&regs->tbase0, addr);
 729
 730         /* Start the rx descriptor ring where the tx ring leaves off */
 731         addr = addr + sizeof (struct txbd8) * priv->tx_ring_size;
 732         vaddr = vaddr + sizeof (struct txbd8) * priv->tx_ring_size;
 733         priv->rx_bd_base = (struct rxbd8 *) vaddr;
 734         gfar_write(&regs->rbase0, addr);
 735
 736         /* Setup the skbuff rings */
 737         priv->tx_skbuff =
 738             (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
 739                                         priv->tx_ring_size, GFP_KERNEL);
 740
 741         if (NULL == priv->tx_skbuff) {
 742                 if (netif_msg_ifup(priv))
 743                         printk(KERN_ERR "%s: Could not allocate tx_skbuff\n",
 744                                         dev->name);
 745                 err = -ENOMEM;
 746                 goto tx_skb_fail;
 747         }
 748
 749         for (i = 0; i < priv->tx_ring_size; i++)
 750                 priv->tx_skbuff[i] = NULL;
 751
 752         priv->rx_skbuff =
 753             (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
 754                                         priv->rx_ring_size, GFP_KERNEL);
 755
 756         if (NULL == priv->rx_skbuff) {
 757                 if (netif_msg_ifup(priv))
 758                         printk(KERN_ERR "%s: Could not allocate rx_skbuff\n",
 759                                         dev->name);
 760                 err = -ENOMEM;
 761                 goto rx_skb_fail;
 762         }
 763
 764         for (i = 0; i < priv->rx_ring_size; i++)
 765                 priv->rx_skbuff[i] = NULL;
 766
 767         /* Initialize some variables in our dev structure */
 768         priv->dirty_tx = priv->cur_tx = priv->tx_bd_base;
 769         priv->cur_rx = priv->rx_bd_base;
 770         priv->skb_curtx = priv->skb_dirtytx = 0;
 771         priv->skb_currx = 0;
 772
 773         /* Initialize Transmit Descriptor Ring */
 774         txbdp = priv->tx_bd_base;
 775         for (i = 0; i < priv->tx_ring_size; i++) {
 776                 txbdp->status = 0;
 777                 txbdp->length = 0;
 778                 txbdp->bufPtr = 0;
 779                 txbdp++;
 780         }
 781
 782         /* Set the last descriptor in the ring to indicate wrap */
 783         txbdp--;
 784         txbdp->status |= TXBD_WRAP;
 785
 786         rxbdp = priv->rx_bd_base;
 787         for (i = 0; i < priv->rx_ring_size; i++) {
 788                 struct sk_buff *skb = NULL;
 789
 790                 rxbdp->status = 0;
 791
 792                 skb = gfar_new_skb(dev, rxbdp);
 793
 794                 priv->rx_skbuff[i] = skb;
 795
 796                 rxbdp++;
 797         }
 798
 799         /* Set the last descriptor in the ring to wrap */
 800         rxbdp--;
 801         rxbdp->status |= RXBD_WRAP;
 802
 803         /* If the device has multiple interrupts, register for
 804          * them.  Otherwise, only register for the one */
 805         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
 806                 /* Install our interrupt handlers for Error,
 807                  * Transmit, and Receive */
 808                 if (request_irq(priv->interruptError, gfar_error,
 809                                 0, "enet_error", dev) < 0) {
 810                         if (netif_msg_intr(priv))
 811                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
 812                                         dev->name, priv->interruptError);
 813
 814                         err = -1;
 815                         goto err_irq_fail;
 816                 }
 817
 818                 if (request_irq(priv->interruptTransmit, gfar_transmit,
 819                                 0, "enet_tx", dev) < 0) {
 820                         if (netif_msg_intr(priv))
 821                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
 822                                         dev->name, priv->interruptTransmit);
 823
 824                         err = -1;
 825
 826                         goto tx_irq_fail;
 827                 }
 828
 829                 if (request_irq(priv->interruptReceive, gfar_receive,
 830                                 0, "enet_rx", dev) < 0) {
 831                         if (netif_msg_intr(priv))
 832                                 printk(KERN_ERR "%s: Can't get IRQ %d (receive0)\n",
 833                                                 dev->name, priv->interruptReceive);
 834
 835                         err = -1;
 836                         goto rx_irq_fail;
 837                 }
 838         } else {
 839                 if (request_irq(priv->interruptTransmit, gfar_interrupt,
 840                                 0, "gfar_interrupt", dev) < 0) {
 841                         if (netif_msg_intr(priv))
 842                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
 843                                         dev->name, priv->interruptError);
 844
 845                         err = -1;
 846                         goto err_irq_fail;
 847                 }
 848         }
 849
 850         phy_start(priv->phydev);
 851
 852         /* Configure the coalescing support */
 853         if (priv->txcoalescing)
 854                 gfar_write(&regs->txic,
 855                            mk_ic_value(priv->txcount, priv->txtime));
 856         else
 857                 gfar_write(&regs->txic, 0);
 858
 859         if (priv->rxcoalescing)
 860                 gfar_write(&regs->rxic,
 861                            mk_ic_value(priv->rxcount, priv->rxtime));
 862         else
 863                 gfar_write(&regs->rxic, 0);
 864
 865         if (priv->rx_csum_enable)
 866                 rctrl |= RCTRL_CHECKSUMMING;
 867
 868         if (priv->extended_hash) {
 869                 rctrl |= RCTRL_EXTHASH;
 870
 871                 gfar_clear_exact_match(dev);
 872                 rctrl |= RCTRL_EMEN;
 873         }
 874
 875         if (priv->vlan_enable)
 876                 rctrl |= RCTRL_VLAN;
 877
 878         if (priv->padding) {
 879                 rctrl &= ~RCTRL_PAL_MASK;
 880                 rctrl |= RCTRL_PADDING(priv->padding);
 881         }
 882
 883         /* Init rctrl based on our settings */
 884         gfar_write(&priv->regs->rctrl, rctrl);
 885
 886         if (dev->features & NETIF_F_IP_CSUM)
 887                 gfar_write(&priv->regs->tctrl, TCTRL_INIT_CSUM);
 888
 889         /* Set the extraction length and index */
 890         attrs = ATTRELI_EL(priv->rx_stash_size) |
 891                 ATTRELI_EI(priv->rx_stash_index);
 892
 893         gfar_write(&priv->regs->attreli, attrs);
 894
 895         /* Start with defaults, and add stashing or locking
 896          * depending on the approprate variables */
 897         attrs = ATTR_INIT_SETTINGS;
 898
 899         if (priv->bd_stash_en)
 900                 attrs |= ATTR_BDSTASH;
 901
 902         if (priv->rx_stash_size != 0)
 903                 attrs |= ATTR_BUFSTASH;
 904
 905         gfar_write(&priv->regs->attr, attrs);
 906
 907         gfar_write(&priv->regs->fifo_tx_thr, priv->fifo_threshold);
 908         gfar_write(&priv->regs->fifo_tx_starve, priv->fifo_starve);
 909         gfar_write(&priv->regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
 910
 911         /* Start the controller */
 912         gfar_start(dev);
 913
 914         return 0;
 915
 916 rx_irq_fail:
 917         free_irq(priv->interruptTransmit, dev);
 918 tx_irq_fail:
 919         free_irq(priv->interruptError, dev);
 920 err_irq_fail:
 921 rx_skb_fail:
 922         free_skb_resources(priv);
 923 tx_skb_fail:
 924         dma_free_coherent(NULL,
 925                         sizeof(struct txbd8)*priv->tx_ring_size
 926                         + sizeof(struct rxbd8)*priv->rx_ring_size,
 927                         priv->tx_bd_base,
 928                         gfar_read(&regs->tbase0));
 929
 930         return err;
 931 }
 932
 933 /* Called when something needs to use the ethernet device */
 934 /* Returns 0 for success. */
 935 static int gfar_enet_open(struct net_device *dev)
 936 {
 937         int err;
 938
 939         napi_enable(&priv->napi);
 940
 941         /* Initialize a bunch of registers */
 942         init_registers(dev);
 943
 944         gfar_set_mac_address(dev);
 945
 946         err = init_phy(dev);
 947
 948         if(err) {
 949                 napi_disable(&priv->napi);
 950                 return err;
 951         }
 952
 953         err = startup_gfar(dev);
 954         if (err)
 955                 napi_disable(&priv->napi);
 956
 957         netif_start_queue(dev);
 958
 959         return err;
 960 }
 961
 962 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb, struct txbd8 *bdp)
 963 {
 964         struct txfcb *fcb = (struct txfcb *)skb_push (skb, GMAC_FCB_LEN);
 965
 966         memset(fcb, 0, GMAC_FCB_LEN);
 967
 968         return fcb;
 969 }
 970
 971 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
 972 {
 973         u8 flags = 0;
 974
 975         /* If we're here, it's a IP packet with a TCP or UDP
 976          * payload.  We set it to checksum, using a pseudo-header
 977          * we provide
 978          */
 979         flags = TXFCB_DEFAULT;
 980
 981         /* Tell the controller what the protocol is */
 982         /* And provide the already calculated phcs */
 983         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
 984                 flags |= TXFCB_UDP;
 985                 fcb->phcs = udp_hdr(skb)->check;
 986         } else
 987                 fcb->phcs = tcp_hdr(skb)->check;
 988
 989         /* l3os is the distance between the start of the
 990          * frame (skb->data) and the start of the IP hdr.
 991          * l4os is the distance between the start of the
 992          * l3 hdr and the l4 hdr */
 993         fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
 994         fcb->l4os = skb_network_header_len(skb);
 995
 996         fcb->flags = flags;
 997 }
 998
 999 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
1000 {
1001         fcb->flags |= TXFCB_VLN;
1002         fcb->vlctl = vlan_tx_tag_get(skb);
1003 }
1004
1005 /* This is called by the kernel when a frame is ready for transmission. */
1006 /* It is pointed to by the dev->hard_start_xmit function pointer */
1007 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1008 {
1009         struct gfar_private *priv = netdev_priv(dev);
1010         struct txfcb *fcb = NULL;
1011         struct txbd8 *txbdp;
1012         u16 status;
1013         unsigned long flags;
1014
1015         /* Update transmit stats */
1016         priv->stats.tx_bytes += skb->len;
1017
1018         /* Lock priv now */
1019         spin_lock_irqsave(&priv->txlock, flags);
1020
1021         /* Point at the first free tx descriptor */
1022         txbdp = priv->cur_tx;
1023
1024         /* Clear all but the WRAP status flags */
1025         status = txbdp->status & TXBD_WRAP;
1026
1027         /* Set up checksumming */
1028         if (likely((dev->features & NETIF_F_IP_CSUM)
1029                         && (CHECKSUM_PARTIAL == skb->ip_summed))) {
1030                 fcb = gfar_add_fcb(skb, txbdp);
1031                 status |= TXBD_TOE;
1032                 gfar_tx_checksum(skb, fcb);
1033         }
1034
1035         if (priv->vlan_enable &&
1036                         unlikely(priv->vlgrp && vlan_tx_tag_present(skb))) {
1037                 if (unlikely(NULL == fcb)) {
1038                         fcb = gfar_add_fcb(skb, txbdp);
1039                         status |= TXBD_TOE;
1040                 }
1041
1042                 gfar_tx_vlan(skb, fcb);
1043         }
1044
1045         /* Set buffer length and pointer */
1046         txbdp->length = skb->len;
1047         txbdp->bufPtr = dma_map_single(NULL, skb->data,
1048                         skb->len, DMA_TO_DEVICE);
1049
1050         /* Save the skb pointer so we can free it later */
1051         priv->tx_skbuff[priv->skb_curtx] = skb;
1052
1053         /* Update the current skb pointer (wrapping if this was the last) */
1054         priv->skb_curtx =
1055             (priv->skb_curtx + 1) & TX_RING_MOD_MASK(priv->tx_ring_size);
1056
1057         /* Flag the BD as interrupt-causing */
1058         status |= TXBD_INTERRUPT;
1059
1060         /* Flag the BD as ready to go, last in frame, and  */
1061         /* in need of CRC */
1062         status |= (TXBD_READY | TXBD_LAST | TXBD_CRC);
1063
1064         dev->trans_start = jiffies;
1065
1066         /* The powerpc-specific eieio() is used, as wmb() has too strong
1067          * semantics (it requires synchronization between cacheable and
1068          * uncacheable mappings, which eieio doesn't provide and which we
1069          * don't need), thus requiring a more expensive sync instruction.  At
1070          * some point, the set of architecture-independent barrier functions
1071          * should be expanded to include weaker barriers.
1072          */
1073
1074         eieio();
1075         txbdp->status = status;
1076
1077         /* If this was the last BD in the ring, the next one */
1078         /* is at the beginning of the ring */
1079         if (txbdp->status & TXBD_WRAP)
1080                 txbdp = priv->tx_bd_base;
1081         else
1082                 txbdp++;
1083
1084         /* If the next BD still needs to be cleaned up, then the bds
1085            are full.  We need to tell the kernel to stop sending us stuff. */
1086         if (txbdp == priv->dirty_tx) {
1087                 netif_stop_queue(dev);
1088
1089                 priv->stats.tx_fifo_errors++;
1090         }
1091
1092         /* Update the current txbd to the next one */
1093         priv->cur_tx = txbdp;
1094
1095         /* Tell the DMA to go go go */
1096         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1097
1098         /* Unlock priv */
1099         spin_unlock_irqrestore(&priv->txlock, flags);
1100
1101         return 0;
1102 }
1103
1104 /* Stops the kernel queue, and halts the controller */
1105 static int gfar_close(struct net_device *dev)
1106 {
1107         struct gfar_private *priv = netdev_priv(dev);
1108
1109         napi_disable(&priv->napi);
1110
1111         stop_gfar(dev);
1112
1113         /* Disconnect from the PHY */
1114         phy_disconnect(priv->phydev);
1115         priv->phydev = NULL;
1116
1117         netif_stop_queue(dev);
1118
1119         return 0;
1120 }
1121
1122 /* returns a net_device_stats structure pointer */
1123 static struct net_device_stats * gfar_get_stats(struct net_device *dev)
1124 {
1125         struct gfar_private *priv = netdev_priv(dev);
1126
1127         return &(priv->stats);
1128 }
1129
1130 /* Changes the mac address if the controller is not running. */
1131 int gfar_set_mac_address(struct net_device *dev)
1132 {
1133         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1134
1135         return 0;
1136 }
1137
1138
1139 /* Enables and disables VLAN insertion/extraction */
1140 static void gfar_vlan_rx_register(struct net_device *dev,
1141                 struct vlan_group *grp)
1142 {
1143         struct gfar_private *priv = netdev_priv(dev);
1144         unsigned long flags;
1145         u32 tempval;
1146
1147         spin_lock_irqsave(&priv->rxlock, flags);
1148
1149         priv->vlgrp = grp;
1150
1151         if (grp) {
1152                 /* Enable VLAN tag insertion */
1153                 tempval = gfar_read(&priv->regs->tctrl);
1154                 tempval |= TCTRL_VLINS;
1155
1156                 gfar_write(&priv->regs->tctrl, tempval);
1157
1158                 /* Enable VLAN tag extraction */
1159                 tempval = gfar_read(&priv->regs->rctrl);
1160                 tempval |= RCTRL_VLEX;
1161                 gfar_write(&priv->regs->rctrl, tempval);
1162         } else {
1163                 /* Disable VLAN tag insertion */
1164                 tempval = gfar_read(&priv->regs->tctrl);
1165                 tempval &= ~TCTRL_VLINS;
1166                 gfar_write(&priv->regs->tctrl, tempval);
1167
1168                 /* Disable VLAN tag extraction */
1169                 tempval = gfar_read(&priv->regs->rctrl);
1170                 tempval &= ~RCTRL_VLEX;
1171                 gfar_write(&priv->regs->rctrl, tempval);
1172         }
1173
1174         spin_unlock_irqrestore(&priv->rxlock, flags);
1175 }
1176
1177 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
1178 {
1179         int tempsize, tempval;
1180         struct gfar_private *priv = netdev_priv(dev);
1181         int oldsize = priv->rx_buffer_size;
1182         int frame_size = new_mtu + ETH_HLEN;
1183
1184         if (priv->vlan_enable)
1185                 frame_size += VLAN_ETH_HLEN;
1186
1187         if (gfar_uses_fcb(priv))
1188                 frame_size += GMAC_FCB_LEN;
1189
1190         frame_size += priv->padding;
1191
1192         if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
1193                 if (netif_msg_drv(priv))
1194                         printk(KERN_ERR "%s: Invalid MTU setting\n",
1195                                         dev->name);
1196                 return -EINVAL;
1197         }
1198
1199         tempsize =
1200             (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
1201             INCREMENTAL_BUFFER_SIZE;
1202
1203         /* Only stop and start the controller if it isn't already
1204          * stopped, and we changed something */
1205         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1206                 stop_gfar(dev);
1207
1208         priv->rx_buffer_size = tempsize;
1209
1210         dev->mtu = new_mtu;
1211
1212         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
1213         gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size);
1214
1215         /* If the mtu is larger than the max size for standard
1216          * ethernet frames (ie, a jumbo frame), then set maccfg2
1217          * to allow huge frames, and to check the length */
1218         tempval = gfar_read(&priv->regs->maccfg2);
1219
1220         if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
1221                 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1222         else
1223                 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1224
1225         gfar_write(&priv->regs->maccfg2, tempval);
1226
1227         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1228                 startup_gfar(dev);
1229
1230         return 0;
1231 }
1232
1233 /* gfar_timeout gets called when a packet has not been
1234  * transmitted after a set amount of time.
1235  * For now, assume that clearing out all the structures, and
1236  * starting over will fix the problem. */
1237 static void gfar_timeout(struct net_device *dev)
1238 {
1239         struct gfar_private *priv = netdev_priv(dev);
1240
1241         priv->stats.tx_errors++;
1242
1243         if (dev->flags & IFF_UP) {
1244                 stop_gfar(dev);
1245                 startup_gfar(dev);
1246         }
1247
1248         netif_schedule(dev);
1249 }
1250
1251 /* Interrupt Handler for Transmit complete */
1252 static irqreturn_t gfar_transmit(int irq, void *dev_id)
1253 {
1254         struct net_device *dev = (struct net_device *) dev_id;
1255         struct gfar_private *priv = netdev_priv(dev);
1256         struct txbd8 *bdp;
1257
1258         /* Clear IEVENT */
1259         gfar_write(&priv->regs->ievent, IEVENT_TX_MASK);
1260
1261         /* Lock priv */
1262         spin_lock(&priv->txlock);
1263         bdp = priv->dirty_tx;
1264         while ((bdp->status & TXBD_READY) == 0) {
1265                 /* If dirty_tx and cur_tx are the same, then either the */
1266                 /* ring is empty or full now (it could only be full in the beginning, */
1267                 /* obviously).  If it is empty, we are done. */
1268                 if ((bdp == priv->cur_tx) && (netif_queue_stopped(dev) == 0))
1269                         break;
1270
1271                 priv->stats.tx_packets++;
1272
1273                 /* Deferred means some collisions occurred during transmit, */
1274                 /* but we eventually sent the packet. */
1275                 if (bdp->status & TXBD_DEF)
1276                         priv->stats.collisions++;
1277
1278                 /* Free the sk buffer associated with this TxBD */
1279                 dev_kfree_skb_irq(priv->tx_skbuff[priv->skb_dirtytx]);
1280                 priv->tx_skbuff[priv->skb_dirtytx] = NULL;
1281                 priv->skb_dirtytx =
1282                     (priv->skb_dirtytx +
1283                      1) & TX_RING_MOD_MASK(priv->tx_ring_size);
1284
1285                 /* update bdp to point at next bd in the ring (wrapping if necessary) */
1286                 if (bdp->status & TXBD_WRAP)
1287                         bdp = priv->tx_bd_base;
1288                 else
1289                         bdp++;
1290
1291                 /* Move dirty_tx to be the next bd */
1292                 priv->dirty_tx = bdp;
1293
1294                 /* We freed a buffer, so now we can restart transmission */
1295                 if (netif_queue_stopped(dev))
1296                         netif_wake_queue(dev);
1297         } /* while ((bdp->status & TXBD_READY) == 0) */
1298
1299         /* If we are coalescing the interrupts, reset the timer */
1300         /* Otherwise, clear it */
1301         if (priv->txcoalescing)
1302                 gfar_write(&priv->regs->txic,
1303                            mk_ic_value(priv->txcount, priv->txtime));
1304         else
1305                 gfar_write(&priv->regs->txic, 0);
1306
1307         spin_unlock(&priv->txlock);
1308
1309         return IRQ_HANDLED;
1310 }
1311
1312 struct sk_buff * gfar_new_skb(struct net_device *dev, struct rxbd8 *bdp)
1313 {
1314         unsigned int alignamount;
1315         struct gfar_private *priv = netdev_priv(dev);
1316         struct sk_buff *skb = NULL;
1317         unsigned int timeout = SKB_ALLOC_TIMEOUT;
1318
1319         /* We have to allocate the skb, so keep trying till we succeed */
1320         while ((!skb) && timeout--)
1321                 skb = dev_alloc_skb(priv->rx_buffer_size + RXBUF_ALIGNMENT);
1322
1323         if (NULL == skb)
1324                 return NULL;
1325
1326         alignamount = RXBUF_ALIGNMENT -
1327                 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1));
1328
1329         /* We need the data buffer to be aligned properly.  We will reserve
1330          * as many bytes as needed to align the data properly
1331          */
1332         skb_reserve(skb, alignamount);
1333
1334         bdp->bufPtr = dma_map_single(NULL, skb->data,
1335                         priv->rx_buffer_size, DMA_FROM_DEVICE);
1336
1337         bdp->length = 0;
1338
1339         /* Mark the buffer empty */
1340         eieio();
1341         bdp->status |= (RXBD_EMPTY | RXBD_INTERRUPT);
1342
1343         return skb;
1344 }
1345
1346 static inline void count_errors(unsigned short status, struct gfar_private *priv)
1347 {
1348         struct net_device_stats *stats = &priv->stats;
1349         struct gfar_extra_stats *estats = &priv->extra_stats;
1350
1351         /* If the packet was truncated, none of the other errors
1352          * matter */
1353         if (status & RXBD_TRUNCATED) {
1354                 stats->rx_length_errors++;
1355
1356                 estats->rx_trunc++;
1357
1358                 return;
1359         }
1360         /* Count the errors, if there were any */
1361         if (status & (RXBD_LARGE | RXBD_SHORT)) {
1362                 stats->rx_length_errors++;
1363
1364                 if (status & RXBD_LARGE)
1365                         estats->rx_large++;
1366                 else
1367                         estats->rx_short++;
1368         }
1369         if (status & RXBD_NONOCTET) {
1370                 stats->rx_frame_errors++;
1371                 estats->rx_nonoctet++;
1372         }
1373         if (status & RXBD_CRCERR) {
1374                 estats->rx_crcerr++;
1375                 stats->rx_crc_errors++;
1376         }
1377         if (status & RXBD_OVERRUN) {
1378                 estats->rx_overrun++;
1379                 stats->rx_crc_errors++;
1380         }
1381 }
1382
1383 irqreturn_t gfar_receive(int irq, void *dev_id)
1384 {
1385         struct net_device *dev = (struct net_device *) dev_id;
1386         struct gfar_private *priv = netdev_priv(dev);
1387 #ifdef CONFIG_GFAR_NAPI
1388         u32 tempval;
1389 #else
1390         unsigned long flags;
1391 #endif
1392
1393         /* Clear IEVENT, so rx interrupt isn't called again
1394          * because of this interrupt */
1395         gfar_write(&priv->regs->ievent, IEVENT_RX_MASK);
1396
1397         /* support NAPI */
1398 #ifdef CONFIG_GFAR_NAPI
1399         if (netif_rx_schedule_prep(dev, &priv->napi)) {
1400                 tempval = gfar_read(&priv->regs->imask);
1401                 tempval &= IMASK_RX_DISABLED;
1402                 gfar_write(&priv->regs->imask, tempval);
1403
1404                 __netif_rx_schedule(dev, &priv->napi);
1405         } else {
1406                 if (netif_msg_rx_err(priv))
1407                         printk(KERN_DEBUG "%s: receive called twice (%x)[%x]\n",
1408                                 dev->name, gfar_read(&priv->regs->ievent),
1409                                 gfar_read(&priv->regs->imask));
1410         }
1411 #else
1412
1413         spin_lock_irqsave(&priv->rxlock, flags);
1414         gfar_clean_rx_ring(dev, priv->rx_ring_size);
1415
1416         /* If we are coalescing interrupts, update the timer */
1417         /* Otherwise, clear it */
1418         if (priv->rxcoalescing)
1419                 gfar_write(&priv->regs->rxic,
1420                            mk_ic_value(priv->rxcount, priv->rxtime));
1421         else
1422                 gfar_write(&priv->regs->rxic, 0);
1423
1424         spin_unlock_irqrestore(&priv->rxlock, flags);
1425 #endif
1426
1427         return IRQ_HANDLED;
1428 }
1429
1430 static inline int gfar_rx_vlan(struct sk_buff *skb,
1431                 struct vlan_group *vlgrp, unsigned short vlctl)
1432 {
1433 #ifdef CONFIG_GFAR_NAPI
1434         return vlan_hwaccel_receive_skb(skb, vlgrp, vlctl);
1435 #else
1436         return vlan_hwaccel_rx(skb, vlgrp, vlctl);
1437 #endif
1438 }
1439
1440 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
1441 {
1442         /* If valid headers were found, and valid sums
1443          * were verified, then we tell the kernel that no
1444          * checksumming is necessary.  Otherwise, it is */
1445         if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
1446                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1447         else
1448                 skb->ip_summed = CHECKSUM_NONE;
1449 }
1450
1451
1452 static inline struct rxfcb *gfar_get_fcb(struct sk_buff *skb)
1453 {
1454         struct rxfcb *fcb = (struct rxfcb *)skb->data;
1455
1456         /* Remove the FCB from the skb */
1457         skb_pull(skb, GMAC_FCB_LEN);
1458
1459         return fcb;
1460 }
1461
1462 /* gfar_process_frame() -- handle one incoming packet if skb
1463  * isn't NULL.  */
1464 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
1465                 int length)
1466 {
1467         struct gfar_private *priv = netdev_priv(dev);
1468         struct rxfcb *fcb = NULL;
1469
1470         if (NULL == skb) {
1471                 if (netif_msg_rx_err(priv))
1472                         printk(KERN_WARNING "%s: Missing skb!!.\n", dev->name);
1473                 priv->stats.rx_dropped++;
1474                 priv->extra_stats.rx_skbmissing++;
1475         } else {
1476                 int ret;
1477
1478                 /* Prep the skb for the packet */
1479                 skb_put(skb, length);
1480
1481                 /* Grab the FCB if there is one */
1482                 if (gfar_uses_fcb(priv))
1483                         fcb = gfar_get_fcb(skb);
1484
1485                 /* Remove the padded bytes, if there are any */
1486                 if (priv->padding)
1487                         skb_pull(skb, priv->padding);
1488
1489                 if (priv->rx_csum_enable)
1490                         gfar_rx_checksum(skb, fcb);
1491
1492                 /* Tell the skb what kind of packet this is */
1493                 skb->protocol = eth_type_trans(skb, dev);
1494
1495                 /* Send the packet up the stack */
1496                 if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
1497                         ret = gfar_rx_vlan(skb, priv->vlgrp, fcb->vlctl);
1498                 else
1499                         ret = RECEIVE(skb);
1500
1501                 if (NET_RX_DROP == ret)
1502                         priv->extra_stats.kernel_dropped++;
1503         }
1504
1505         return 0;
1506 }
1507
1508 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1509  *   until the budget/quota has been reached. Returns the number
1510  *   of frames handled
1511  */
1512 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit)
1513 {
1514         struct rxbd8 *bdp;
1515         struct sk_buff *skb;
1516         u16 pkt_len;
1517         int howmany = 0;
1518         struct gfar_private *priv = netdev_priv(dev);
1519
1520         /* Get the first full descriptor */
1521         bdp = priv->cur_rx;
1522
1523         while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
1524                 rmb();
1525                 skb = priv->rx_skbuff[priv->skb_currx];
1526
1527                 if (!(bdp->status &
1528                       (RXBD_LARGE | RXBD_SHORT | RXBD_NONOCTET
1529                        | RXBD_CRCERR | RXBD_OVERRUN | RXBD_TRUNCATED))) {
1530                         /* Increment the number of packets */
1531                         priv->stats.rx_packets++;
1532                         howmany++;
1533
1534                         /* Remove the FCS from the packet length */
1535                         pkt_len = bdp->length - 4;
1536
1537                         gfar_process_frame(dev, skb, pkt_len);
1538
1539                         priv->stats.rx_bytes += pkt_len;
1540                 } else {
1541                         count_errors(bdp->status, priv);
1542
1543                         if (skb)
1544                                 dev_kfree_skb_any(skb);
1545
1546                         priv->rx_skbuff[priv->skb_currx] = NULL;
1547                 }
1548
1549                 dev->last_rx = jiffies;
1550
1551                 /* Clear the status flags for this buffer */
1552                 bdp->status &= ~RXBD_STATS;
1553
1554                 /* Add another skb for the future */
1555                 skb = gfar_new_skb(dev, bdp);
1556                 priv->rx_skbuff[priv->skb_currx] = skb;
1557
1558                 /* Update to the next pointer */
1559                 if (bdp->status & RXBD_WRAP)
1560                         bdp = priv->rx_bd_base;
1561                 else
1562                         bdp++;
1563
1564                 /* update to point at the next skb */
1565                 priv->skb_currx =
1566                     (priv->skb_currx +
1567                      1) & RX_RING_MOD_MASK(priv->rx_ring_size);
1568
1569         }
1570
1571         /* Update the current rxbd pointer to be the next one */
1572         priv->cur_rx = bdp;
1573
1574         return howmany;
1575 }
1576
1577 #ifdef CONFIG_GFAR_NAPI
1578 static int gfar_poll(struct napi_struct *napi, int budget)
1579 {
1580         struct gfar_private *priv = container_of(napi, struct gfar_private, napi);
1581         struct net_device *dev = priv->dev;
1582         int howmany;
1583
1584         howmany = gfar_clean_rx_ring(dev, budget);
1585
1586         if (howmany < budget) {
1587                 netif_rx_complete(dev, napi);
1588
1589                 /* Clear the halt bit in RSTAT */
1590                 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1591
1592                 gfar_write(&priv->regs->imask, IMASK_DEFAULT);
1593
1594                 /* If we are coalescing interrupts, update the timer */
1595                 /* Otherwise, clear it */
1596                 if (priv->rxcoalescing)
1597                         gfar_write(&priv->regs->rxic,
1598                                    mk_ic_value(priv->rxcount, priv->rxtime));
1599                 else
1600                         gfar_write(&priv->regs->rxic, 0);
1601         }
1602
1603         return howmany;
1604 }
1605 #endif
1606
1607 #ifdef CONFIG_NET_POLL_CONTROLLER
1608 /*
1609  * Polling 'interrupt' - used by things like netconsole to send skbs
1610  * without having to re-enable interrupts. It's not called while
1611  * the interrupt routine is executing.
1612  */
1613 static void gfar_netpoll(struct net_device *dev)
1614 {
1615         struct gfar_private *priv = netdev_priv(dev);
1616
1617         /* If the device has multiple interrupts, run tx/rx */
1618         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1619                 disable_irq(priv->interruptTransmit);
1620                 disable_irq(priv->interruptReceive);
1621                 disable_irq(priv->interruptError);
1622                 gfar_interrupt(priv->interruptTransmit, dev);
1623                 enable_irq(priv->interruptError);
1624                 enable_irq(priv->interruptReceive);
1625                 enable_irq(priv->interruptTransmit);
1626         } else {
1627                 disable_irq(priv->interruptTransmit);
1628                 gfar_interrupt(priv->interruptTransmit, dev);
1629                 enable_irq(priv->interruptTransmit);
1630         }
1631 }
1632 #endif
1633
1634 /* The interrupt handler for devices with one interrupt */
1635 static irqreturn_t gfar_interrupt(int irq, void *dev_id)
1636 {
1637         struct net_device *dev = dev_id;
1638         struct gfar_private *priv = netdev_priv(dev);
1639
1640         /* Save ievent for future reference */
1641         u32 events = gfar_read(&priv->regs->ievent);
1642
1643         /* Check for reception */
1644         if (events & IEVENT_RX_MASK)
1645                 gfar_receive(irq, dev_id);
1646
1647         /* Check for transmit completion */
1648         if (events & IEVENT_TX_MASK)
1649                 gfar_transmit(irq, dev_id);
1650
1651         /* Check for errors */
1652         if (events & IEVENT_ERR_MASK)
1653                 gfar_error(irq, dev_id);
1654
1655         return IRQ_HANDLED;
1656 }
1657
1658 /* Called every time the controller might need to be made
1659  * aware of new link state.  The PHY code conveys this
1660  * information through variables in the phydev structure, and this
1661  * function converts those variables into the appropriate
1662  * register values, and can bring down the device if needed.
1663  */
1664 static void adjust_link(struct net_device *dev)
1665 {
1666         struct gfar_private *priv = netdev_priv(dev);
1667         struct gfar __iomem *regs = priv->regs;
1668         unsigned long flags;
1669         struct phy_device *phydev = priv->phydev;
1670         int new_state = 0;
1671
1672         spin_lock_irqsave(&priv->txlock, flags);
1673         if (phydev->link) {
1674                 u32 tempval = gfar_read(&regs->maccfg2);
1675                 u32 ecntrl = gfar_read(&regs->ecntrl);
1676
1677                 /* Now we make sure that we can be in full duplex mode.
1678                  * If not, we operate in half-duplex mode. */
1679                 if (phydev->duplex != priv->oldduplex) {
1680                         new_state = 1;
1681                         if (!(phydev->duplex))
1682                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
1683                         else
1684                                 tempval |= MACCFG2_FULL_DUPLEX;
1685
1686                         priv->oldduplex = phydev->duplex;
1687                 }
1688
1689                 if (phydev->speed != priv->oldspeed) {
1690                         new_state = 1;
1691                         switch (phydev->speed) {
1692                         case 1000:
1693                                 tempval =
1694                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
1695                                 break;
1696                         case 100:
1697                         case 10:
1698                                 tempval =
1699                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
1700
1701                                 /* Reduced mode distinguishes
1702                                  * between 10 and 100 */
1703                                 if (phydev->speed == SPEED_100)
1704                                         ecntrl |= ECNTRL_R100;
1705                                 else
1706                                         ecntrl &= ~(ECNTRL_R100);
1707                                 break;
1708                         default:
1709                                 if (netif_msg_link(priv))
1710                                         printk(KERN_WARNING
1711                                                 "%s: Ack!  Speed (%d) is not 10/100/1000!\n",
1712                                                 dev->name, phydev->speed);
1713                                 break;
1714                         }
1715
1716                         priv->oldspeed = phydev->speed;
1717                 }
1718
1719                 gfar_write(&regs->maccfg2, tempval);
1720                 gfar_write(&regs->ecntrl, ecntrl);
1721
1722                 if (!priv->oldlink) {
1723                         new_state = 1;
1724                         priv->oldlink = 1;
1725                         netif_schedule(dev);
1726                 }
1727         } else if (priv->oldlink) {
1728                 new_state = 1;
1729                 priv->oldlink = 0;
1730                 priv->oldspeed = 0;
1731                 priv->oldduplex = -1;
1732         }
1733
1734         if (new_state && netif_msg_link(priv))
1735                 phy_print_status(phydev);
1736
1737         spin_unlock_irqrestore(&priv->txlock, flags);
1738 }
1739
1740 /* Update the hash table based on the current list of multicast
1741  * addresses we subscribe to.  Also, change the promiscuity of
1742  * the device based on the flags (this function is called
1743  * whenever dev->flags is changed */
1744 static void gfar_set_multi(struct net_device *dev)
1745 {
1746         struct dev_mc_list *mc_ptr;
1747         struct gfar_private *priv = netdev_priv(dev);
1748         struct gfar __iomem *regs = priv->regs;
1749         u32 tempval;
1750
1751         if(dev->flags & IFF_PROMISC) {
1752                 /* Set RCTRL to PROM */
1753                 tempval = gfar_read(&regs->rctrl);
1754                 tempval |= RCTRL_PROM;
1755                 gfar_write(&regs->rctrl, tempval);
1756         } else {
1757                 /* Set RCTRL to not PROM */
1758                 tempval = gfar_read(&regs->rctrl);
1759                 tempval &= ~(RCTRL_PROM);
1760                 gfar_write(&regs->rctrl, tempval);
1761         }
1762
1763         if(dev->flags & IFF_ALLMULTI) {
1764                 /* Set the hash to rx all multicast frames */
1765                 gfar_write(&regs->igaddr0, 0xffffffff);
1766                 gfar_write(&regs->igaddr1, 0xffffffff);
1767                 gfar_write(&regs->igaddr2, 0xffffffff);
1768                 gfar_write(&regs->igaddr3, 0xffffffff);
1769                 gfar_write(&regs->igaddr4, 0xffffffff);
1770                 gfar_write(&regs->igaddr5, 0xffffffff);
1771                 gfar_write(&regs->igaddr6, 0xffffffff);
1772                 gfar_write(&regs->igaddr7, 0xffffffff);
1773                 gfar_write(&regs->gaddr0, 0xffffffff);
1774                 gfar_write(&regs->gaddr1, 0xffffffff);
1775                 gfar_write(&regs->gaddr2, 0xffffffff);
1776                 gfar_write(&regs->gaddr3, 0xffffffff);
1777                 gfar_write(&regs->gaddr4, 0xffffffff);
1778                 gfar_write(&regs->gaddr5, 0xffffffff);
1779                 gfar_write(&regs->gaddr6, 0xffffffff);
1780                 gfar_write(&regs->gaddr7, 0xffffffff);
1781         } else {
1782                 int em_num;
1783                 int idx;
1784
1785                 /* zero out the hash */
1786                 gfar_write(&regs->igaddr0, 0x0);
1787                 gfar_write(&regs->igaddr1, 0x0);
1788                 gfar_write(&regs->igaddr2, 0x0);
1789                 gfar_write(&regs->igaddr3, 0x0);
1790                 gfar_write(&regs->igaddr4, 0x0);
1791                 gfar_write(&regs->igaddr5, 0x0);
1792                 gfar_write(&regs->igaddr6, 0x0);
1793                 gfar_write(&regs->igaddr7, 0x0);
1794                 gfar_write(&regs->gaddr0, 0x0);
1795                 gfar_write(&regs->gaddr1, 0x0);
1796                 gfar_write(&regs->gaddr2, 0x0);
1797                 gfar_write(&regs->gaddr3, 0x0);
1798                 gfar_write(&regs->gaddr4, 0x0);
1799                 gfar_write(&regs->gaddr5, 0x0);
1800                 gfar_write(&regs->gaddr6, 0x0);
1801                 gfar_write(&regs->gaddr7, 0x0);
1802
1803                 /* If we have extended hash tables, we need to
1804                  * clear the exact match registers to prepare for
1805                  * setting them */
1806                 if (priv->extended_hash) {
1807                         em_num = GFAR_EM_NUM + 1;
1808                         gfar_clear_exact_match(dev);
1809                         idx = 1;
1810                 } else {
1811                         idx = 0;
1812                         em_num = 0;
1813                 }
1814
1815                 if(dev->mc_count == 0)
1816                         return;
1817
1818                 /* Parse the list, and set the appropriate bits */
1819                 for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
1820                         if (idx < em_num) {
1821                                 gfar_set_mac_for_addr(dev, idx,
1822                                                 mc_ptr->dmi_addr);
1823                                 idx++;
1824                         } else
1825                                 gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
1826                 }
1827         }
1828
1829         return;
1830 }
1831
1832
1833 /* Clears each of the exact match registers to zero, so they
1834  * don't interfere with normal reception */
1835 static void gfar_clear_exact_match(struct net_device *dev)
1836 {
1837         int idx;
1838         u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
1839
1840         for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
1841                 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
1842 }
1843
1844 /* Set the appropriate hash bit for the given addr */
1845 /* The algorithm works like so:
1846  * 1) Take the Destination Address (ie the multicast address), and
1847  * do a CRC on it (little endian), and reverse the bits of the
1848  * result.
1849  * 2) Use the 8 most significant bits as a hash into a 256-entry
1850  * table.  The table is controlled through 8 32-bit registers:
1851  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
1852  * gaddr7.  This means that the 3 most significant bits in the
1853  * hash index which gaddr register to use, and the 5 other bits
1854  * indicate which bit (assuming an IBM numbering scheme, which
1855  * for PowerPC (tm) is usually the case) in the register holds
1856  * the entry. */
1857 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
1858 {
1859         u32 tempval;
1860         struct gfar_private *priv = netdev_priv(dev);
1861         u32 result = ether_crc(MAC_ADDR_LEN, addr);
1862         int width = priv->hash_width;
1863         u8 whichbit = (result >> (32 - width)) & 0x1f;
1864         u8 whichreg = result >> (32 - width + 5);
1865         u32 value = (1 << (31-whichbit));
1866
1867         tempval = gfar_read(priv->hash_regs[whichreg]);
1868         tempval |= value;
1869         gfar_write(priv->hash_regs[whichreg], tempval);
1870
1871         return;
1872 }
1873
1874
1875 /* There are multiple MAC Address register pairs on some controllers
1876  * This function sets the numth pair to a given address
1877  */
1878 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
1879 {
1880         struct gfar_private *priv = netdev_priv(dev);
1881         int idx;
1882         char tmpbuf[MAC_ADDR_LEN];
1883         u32 tempval;
1884         u32 __iomem *macptr = &priv->regs->macstnaddr1;
1885
1886         macptr += num*2;
1887
1888         /* Now copy it into the mac registers backwards, cuz */
1889         /* little endian is silly */
1890         for (idx = 0; idx < MAC_ADDR_LEN; idx++)
1891                 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
1892
1893         gfar_write(macptr, *((u32 *) (tmpbuf)));
1894
1895         tempval = *((u32 *) (tmpbuf + 4));
1896
1897         gfar_write(macptr+1, tempval);
1898 }
1899
1900 /* GFAR error interrupt handler */
1901 static irqreturn_t gfar_error(int irq, void *dev_id)
1902 {
1903         struct net_device *dev = dev_id;
1904         struct gfar_private *priv = netdev_priv(dev);
1905
1906         /* Save ievent for future reference */
1907         u32 events = gfar_read(&priv->regs->ievent);
1908
1909         /* Clear IEVENT */
1910         gfar_write(&priv->regs->ievent, IEVENT_ERR_MASK);
1911
1912         /* Hmm... */
1913         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
1914                 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
1915                        dev->name, events, gfar_read(&priv->regs->imask));
1916
1917         /* Update the error counters */
1918         if (events & IEVENT_TXE) {
1919                 priv->stats.tx_errors++;
1920
1921                 if (events & IEVENT_LC)
1922                         priv->stats.tx_window_errors++;
1923                 if (events & IEVENT_CRL)
1924                         priv->stats.tx_aborted_errors++;
1925                 if (events & IEVENT_XFUN) {
1926                         if (netif_msg_tx_err(priv))
1927                                 printk(KERN_DEBUG "%s: TX FIFO underrun, "
1928                                        "packet dropped.\n", dev->name);
1929                         priv->stats.tx_dropped++;
1930                         priv->extra_stats.tx_underrun++;
1931
1932                         /* Reactivate the Tx Queues */
1933                         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1934                 }
1935                 if (netif_msg_tx_err(priv))
1936                         printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
1937         }
1938         if (events & IEVENT_BSY) {
1939                 priv->stats.rx_errors++;
1940                 priv->extra_stats.rx_bsy++;
1941
1942                 gfar_receive(irq, dev_id);
1943
1944 #ifndef CONFIG_GFAR_NAPI
1945                 /* Clear the halt bit in RSTAT */
1946                 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1947 #endif
1948
1949                 if (netif_msg_rx_err(priv))
1950                         printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
1951                                dev->name, gfar_read(&priv->regs->rstat));
1952         }
1953         if (events & IEVENT_BABR) {
1954                 priv->stats.rx_errors++;
1955                 priv->extra_stats.rx_babr++;
1956
1957                 if (netif_msg_rx_err(priv))
1958                         printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
1959         }
1960         if (events & IEVENT_EBERR) {
1961                 priv->extra_stats.eberr++;
1962                 if (netif_msg_rx_err(priv))
1963                         printk(KERN_DEBUG "%s: bus error\n", dev->name);
1964         }
1965         if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
1966                 printk(KERN_DEBUG "%s: control frame\n", dev->name);
1967
1968         if (events & IEVENT_BABT) {
1969                 priv->extra_stats.tx_babt++;
1970                 if (netif_msg_tx_err(priv))
1971                         printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
1972         }
1973         return IRQ_HANDLED;
1974 }
1975
1976 /* Structure for a device driver */
1977 static struct platform_driver gfar_driver = {
1978         .probe = gfar_probe,
1979         .remove = gfar_remove,
1980         .driver = {
1981                 .name = "fsl-gianfar",
1982         },
1983 };
1984
1985 static int __init gfar_init(void)
1986 {
1987         int err = gfar_mdio_init();
1988
1989         if (err)
1990                 return err;
1991
1992         err = platform_driver_register(&gfar_driver);
1993
1994         if (err)
1995                 gfar_mdio_exit();
1996
1997         return err;
1998 }
1999
2000 static void __exit gfar_exit(void)
2001 {
2002         platform_driver_unregister(&gfar_driver);
2003         gfar_mdio_exit();
2004 }
2005
2006 module_init(gfar_init);
2007 module_exit(gfar_exit);
2008