drivers/net/ipg.h

   1 /*
   2  * Include file for Gigabit Ethernet device driver for Network
   3  * Interface Cards (NICs) utilizing the Tamarack Microelectronics
   4  * Inc. IPG Gigabit or Triple Speed Ethernet Media Access
   5  * Controller.
   6  */
   7 #ifndef __LINUX_IPG_H
   8 #define __LINUX_IPG_H
   9
  10 #include <linux/version.h>
  11 #include <linux/module.h>
  12
  13 #include <linux/kernel.h>
  14 #include <linux/pci.h>
  15 #include <linux/ioport.h>
  16 #include <linux/errno.h>
  17 #include <asm/io.h>
  18 #include <linux/delay.h>
  19 #include <linux/types.h>
  20 #include <linux/netdevice.h>
  21 #include <linux/etherdevice.h>
  22 #include <linux/init.h>
  23 #include <linux/skbuff.h>
  24 #include <linux/version.h>
  25 #include <asm/bitops.h>
  26 /*#include <asm/spinlock.h>*/
  27
  28 #define DrvVer "2.09d"
  29
  30 #define IPG_DEV_KFREE_SKB(skb) dev_kfree_skb_irq(skb)
  31
  32 /*
  33  *      Constants
  34  */
  35
  36 /* GMII based PHY IDs */
  37 #define         NS                              0x2000
  38 #define         MARVELL                         0x0141
  39 #define         ICPLUS_PHY              0x243
  40
  41 /* NIC Physical Layer Device MII register fields. */
  42 #define         MII_PHY_SELECTOR_IEEE8023       0x0001
  43 #define         MII_PHY_TECHABILITYFIELD        0x1FE0
  44
  45 /* GMII_PHY_1000 need to set to prefer master */
  46 #define         GMII_PHY_1000BASETCONTROL_PreferMaster 0x0400
  47
  48 /* NIC Physical Layer Device GMII constants. */
  49 #define         GMII_PREAMBLE                    0xFFFFFFFF
  50 #define         GMII_ST                          0x1
  51 #define         GMII_READ                        0x2
  52 #define         GMII_WRITE                       0x1
  53 #define         GMII_TA_READ_MASK                0x1
  54 #define         GMII_TA_WRITE                    0x2
  55
  56 /* I/O register offsets. */
  57 enum ipg_regs {
  58         DMA_CTRL                = 0x00,
  59         RX_DMA_STATUS           = 0x08, // Unused + reserved
  60         TFD_LIST_PTR_0          = 0x10,
  61         TFD_LIST_PTR_1          = 0x14,
  62         TX_DMA_BURST_THRESH     = 0x18,
  63         TX_DMA_URGENT_THRESH    = 0x19,
  64         TX_DMA_POLL_PERIOD      = 0x1a,
  65         RFD_LIST_PTR_0          = 0x1c,
  66         RFD_LIST_PTR_1          = 0x20,
  67         RX_DMA_BURST_THRESH     = 0x24,
  68         RX_DMA_URGENT_THRESH    = 0x25,
  69         RX_DMA_POLL_PERIOD      = 0x26,
  70         DEBUG_CTRL              = 0x2c,
  71         ASIC_CTRL               = 0x30,
  72         FIFO_CTRL               = 0x38, // Unused
  73         FLOW_OFF_THRESH         = 0x3c,
  74         FLOW_ON_THRESH          = 0x3e,
  75         EEPROM_DATA             = 0x48,
  76         EEPROM_CTRL             = 0x4a,
  77         EXPROM_ADDR             = 0x4c, // Unused
  78         EXPROM_DATA             = 0x50, // Unused
  79         WAKE_EVENT              = 0x51, // Unused
  80         COUNTDOWN               = 0x54, // Unused
  81         INT_STATUS_ACK          = 0x5a,
  82         INT_ENABLE              = 0x5c,
  83         INT_STATUS              = 0x5e, // Unused
  84         TX_STATUS               = 0x60,
  85         MAC_CTRL                = 0x6c,
  86         VLAN_TAG                = 0x70, // Unused
  87         PHY_SET                 = 0x75, // JES20040127EEPROM
  88         PHY_CTRL                = 0x76,
  89         STATION_ADDRESS_0       = 0x78,
  90         STATION_ADDRESS_1       = 0x7a,
  91         STATION_ADDRESS_2       = 0x7c,
  92         MAX_FRAME_SIZE          = 0x86,
  93         RECEIVE_MODE            = 0x88,
  94         HASHTABLE_0             = 0x8c,
  95         HASHTABLE_1             = 0x90,
  96         RMON_STATISTICS_MASK    = 0x98,
  97         STATISTICS_MASK         = 0x9c,
  98         RX_JUMBO_FRAMES         = 0xbc, // Unused
  99         TCP_CHECKSUM_ERRORS     = 0xc0, // Unused
 100         IP_CHECKSUM_ERRORS      = 0xc2, // Unused
 101         UDP_CHECKSUM_ERRORS     = 0xc4, // Unused
 102         TX_JUMBO_FRAMES         = 0xf4  // Unused
 103 };
 104
 105 /* Ethernet MIB statistic register offsets. */
 106 #define IPG_OCTETRCVOK          0xA8
 107 #define IPG_MCSTOCTETRCVDOK             0xAC
 108 #define IPG_BCSTOCTETRCVOK              0xB0
 109 #define IPG_FRAMESRCVDOK                0xB4
 110 #define IPG_MCSTFRAMESRCVDOK            0xB8
 111 #define IPG_BCSTFRAMESRCVDOK            0xBE
 112 #define IPG_MACCONTROLFRAMESRCVD        0xC6
 113 #define IPG_FRAMETOOLONGERRRORS 0xC8
 114 #define IPG_INRANGELENGTHERRORS 0xCA
 115 #define IPG_FRAMECHECKSEQERRORS 0xCC
 116 #define IPG_FRAMESLOSTRXERRORS  0xCE
 117 #define IPG_OCTETXMTOK          0xD0
 118 #define IPG_MCSTOCTETXMTOK              0xD4
 119 #define IPG_BCSTOCTETXMTOK              0xD8
 120 #define IPG_FRAMESXMTDOK                0xDC
 121 #define IPG_MCSTFRAMESXMTDOK            0xE0
 122 #define IPG_FRAMESWDEFERREDXMT  0xE4
 123 #define IPG_LATECOLLISIONS              0xE8
 124 #define IPG_MULTICOLFRAMES              0xEC
 125 #define IPG_SINGLECOLFRAMES             0xF0
 126 #define IPG_BCSTFRAMESXMTDOK            0xF6
 127 #define IPG_CARRIERSENSEERRORS  0xF8
 128 #define IPG_MACCONTROLFRAMESXMTDOK      0xFA
 129 #define IPG_FRAMESABORTXSCOLLS  0xFC
 130 #define IPG_FRAMESWEXDEFERRAL   0xFE
 131
 132 /* RMON statistic register offsets. */
 133 #define IPG_ETHERSTATSCOLLISIONS                        0x100
 134 #define IPG_ETHERSTATSOCTETSTRANSMIT                    0x104
 135 #define IPG_ETHERSTATSPKTSTRANSMIT                      0x108
 136 #define IPG_ETHERSTATSPKTS64OCTESTSTRANSMIT             0x10C
 137 #define IPG_ETHERSTATSPKTS65TO127OCTESTSTRANSMIT        0x110
 138 #define IPG_ETHERSTATSPKTS128TO255OCTESTSTRANSMIT       0x114
 139 #define IPG_ETHERSTATSPKTS256TO511OCTESTSTRANSMIT       0x118
 140 #define IPG_ETHERSTATSPKTS512TO1023OCTESTSTRANSMIT      0x11C
 141 #define IPG_ETHERSTATSPKTS1024TO1518OCTESTSTRANSMIT     0x120
 142 #define IPG_ETHERSTATSCRCALIGNERRORS                    0x124
 143 #define IPG_ETHERSTATSUNDERSIZEPKTS                     0x128
 144 #define IPG_ETHERSTATSFRAGMENTS                 0x12C
 145 #define IPG_ETHERSTATSJABBERS                   0x130
 146 #define IPG_ETHERSTATSOCTETS                            0x134
 147 #define IPG_ETHERSTATSPKTS                              0x138
 148 #define IPG_ETHERSTATSPKTS64OCTESTS                     0x13C
 149 #define IPG_ETHERSTATSPKTS65TO127OCTESTS                0x140
 150 #define IPG_ETHERSTATSPKTS128TO255OCTESTS               0x144
 151 #define IPG_ETHERSTATSPKTS256TO511OCTESTS               0x148
 152 #define IPG_ETHERSTATSPKTS512TO1023OCTESTS              0x14C
 153 #define IPG_ETHERSTATSPKTS1024TO1518OCTESTS             0x150
 154
 155 /* RMON statistic register equivalents. */
 156 #define IPG_ETHERSTATSMULTICASTPKTSTRANSMIT             0xE0
 157 #define IPG_ETHERSTATSBROADCASTPKTSTRANSMIT             0xF6
 158 #define IPG_ETHERSTATSMULTICASTPKTS                     0xB8
 159 #define IPG_ETHERSTATSBROADCASTPKTS                     0xBE
 160 #define IPG_ETHERSTATSOVERSIZEPKTS                      0xC8
 161 #define IPG_ETHERSTATSDROPEVENTS                        0xCE
 162
 163 /* Serial EEPROM offsets */
 164 #define IPG_EEPROM_CONFIGPARAM  0x00
 165 #define IPG_EEPROM_ASICCTRL             0x01
 166 #define IPG_EEPROM_SUBSYSTEMVENDORID    0x02
 167 #define IPG_EEPROM_SUBSYSTEMID  0x03
 168 #define IPG_EEPROM_STATIONADDRESS0      0x10
 169 #define IPG_EEPROM_STATIONADDRESS1      0x11
 170 #define IPG_EEPROM_STATIONADDRESS2      0x12
 171
 172 /* Register & data structure bit masks */
 173
 174 /* PCI register masks. */
 175
 176 /* IOBaseAddress */
 177 #define         IPG_PIB_RSVD_MASK               0xFFFFFE01
 178 #define         IPG_PIB_IOBASEADDRESS   0xFFFFFF00
 179 #define         IPG_PIB_IOBASEADDRIND   0x00000001
 180
 181 /* MemBaseAddress */
 182 #define         IPG_PMB_RSVD_MASK               0xFFFFFE07
 183 #define         IPG_PMB_MEMBASEADDRIND  0x00000001
 184 #define         IPG_PMB_MEMMAPTYPE              0x00000006
 185 #define         IPG_PMB_MEMMAPTYPE0             0x00000002
 186 #define         IPG_PMB_MEMMAPTYPE1             0x00000004
 187 #define         IPG_PMB_MEMBASEADDRESS  0xFFFFFE00
 188
 189 /* ConfigStatus */
 190 #define IPG_CS_RSVD_MASK                0xFFB0
 191 #define IPG_CS_CAPABILITIES             0x0010
 192 #define IPG_CS_66MHZCAPABLE             0x0020
 193 #define IPG_CS_FASTBACK2BACK            0x0080
 194 #define IPG_CS_DATAPARITYREPORTED       0x0100
 195 #define IPG_CS_DEVSELTIMING             0x0600
 196 #define IPG_CS_SIGNALEDTARGETABORT      0x0800
 197 #define IPG_CS_RECEIVEDTARGETABORT      0x1000
 198 #define IPG_CS_RECEIVEDMASTERABORT      0x2000
 199 #define IPG_CS_SIGNALEDSYSTEMERROR      0x4000
 200 #define IPG_CS_DETECTEDPARITYERROR      0x8000
 201
 202 /* TFD data structure masks. */
 203
 204 /* TFDList, TFC */
 205 #define IPG_TFC_RSVD_MASK                       0x0000FFFF9FFFFFFF
 206 #define IPG_TFC_FRAMEID                 0x000000000000FFFF
 207 #define IPG_TFC_WORDALIGN                       0x0000000000030000
 208 #define IPG_TFC_WORDALIGNTODWORD                0x0000000000000000
 209 #define IPG_TFC_WORDALIGNTOWORD         0x0000000000020000
 210 #define IPG_TFC_WORDALIGNDISABLED               0x0000000000030000
 211 #define IPG_TFC_TCPCHECKSUMENABLE               0x0000000000040000
 212 #define IPG_TFC_UDPCHECKSUMENABLE               0x0000000000080000
 213 #define IPG_TFC_IPCHECKSUMENABLE                0x0000000000100000
 214 #define IPG_TFC_FCSAPPENDDISABLE                0x0000000000200000
 215 #define IPG_TFC_TXINDICATE                      0x0000000000400000
 216 #define IPG_TFC_TXDMAINDICATE           0x0000000000800000
 217 #define IPG_TFC_FRAGCOUNT                       0x000000000F000000
 218 #define IPG_TFC_VLANTAGINSERT           0x0000000010000000
 219 #define IPG_TFC_TFDDONE                 0x0000000080000000
 220 #define IPG_TFC_VID                             0x00000FFF00000000
 221 #define IPG_TFC_CFI                             0x0000100000000000
 222 #define IPG_TFC_USERPRIORITY                    0x0000E00000000000
 223
 224 /* TFDList, FragInfo */
 225 #define IPG_TFI_RSVD_MASK                       0xFFFF00FFFFFFFFFF
 226 #define IPG_TFI_FRAGADDR                        0x000000FFFFFFFFFF
 227 #define IPG_TFI_FRAGLEN                 0xFFFF000000000000LL
 228
 229 /* RFD data structure masks. */
 230
 231 /* RFDList, RFS */
 232 #define IPG_RFS_RSVD_MASK                       0x0000FFFFFFFFFFFF
 233 #define IPG_RFS_RXFRAMELEN                      0x000000000000FFFF
 234 #define IPG_RFS_RXFIFOOVERRUN           0x0000000000010000
 235 #define IPG_RFS_RXRUNTFRAME                     0x0000000000020000
 236 #define IPG_RFS_RXALIGNMENTERROR                0x0000000000040000
 237 #define IPG_RFS_RXFCSERROR                      0x0000000000080000
 238 #define IPG_RFS_RXOVERSIZEDFRAME                0x0000000000100000
 239 #define IPG_RFS_RXLENGTHERROR           0x0000000000200000
 240 #define IPG_RFS_VLANDETECTED                    0x0000000000400000
 241 #define IPG_RFS_TCPDETECTED                     0x0000000000800000
 242 #define IPG_RFS_TCPERROR                        0x0000000001000000
 243 #define IPG_RFS_UDPDETECTED                     0x0000000002000000
 244 #define IPG_RFS_UDPERROR                        0x0000000004000000
 245 #define IPG_RFS_IPDETECTED                      0x0000000008000000
 246 #define IPG_RFS_IPERROR                 0x0000000010000000
 247 #define IPG_RFS_FRAMESTART                      0x0000000020000000
 248 #define IPG_RFS_FRAMEEND                        0x0000000040000000
 249 #define IPG_RFS_RFDDONE                 0x0000000080000000
 250 #define IPG_RFS_TCI                             0x0000FFFF00000000
 251
 252 /* RFDList, FragInfo */
 253 #define IPG_RFI_RSVD_MASK                       0xFFFF00FFFFFFFFFF
 254 #define IPG_RFI_FRAGADDR                        0x000000FFFFFFFFFF
 255 #define IPG_RFI_FRAGLEN                 0xFFFF000000000000LL
 256
 257 /* I/O Register masks. */
 258
 259 /* RMON Statistics Mask */
 260 #define IPG_RZ_ALL                                      0x0FFFFFFF
 261
 262 /* Statistics Mask */
 263 #define IPG_SM_ALL                                      0x0FFFFFFF
 264 #define IPG_SM_OCTETRCVOK_FRAMESRCVDOK          0x00000001
 265 #define IPG_SM_MCSTOCTETRCVDOK_MCSTFRAMESRCVDOK 0x00000002
 266 #define IPG_SM_BCSTOCTETRCVDOK_BCSTFRAMESRCVDOK 0x00000004
 267 #define IPG_SM_RXJUMBOFRAMES                            0x00000008
 268 #define IPG_SM_TCPCHECKSUMERRORS                        0x00000010
 269 #define IPG_SM_IPCHECKSUMERRORS                 0x00000020
 270 #define IPG_SM_UDPCHECKSUMERRORS                        0x00000040
 271 #define IPG_SM_MACCONTROLFRAMESRCVD                     0x00000080
 272 #define IPG_SM_FRAMESTOOLONGERRORS                      0x00000100
 273 #define IPG_SM_INRANGELENGTHERRORS                      0x00000200
 274 #define IPG_SM_FRAMECHECKSEQERRORS                      0x00000400
 275 #define IPG_SM_FRAMESLOSTRXERRORS                       0x00000800
 276 #define IPG_SM_OCTETXMTOK_FRAMESXMTOK           0x00001000
 277 #define IPG_SM_MCSTOCTETXMTOK_MCSTFRAMESXMTDOK  0x00002000
 278 #define IPG_SM_BCSTOCTETXMTOK_BCSTFRAMESXMTDOK  0x00004000
 279 #define IPG_SM_FRAMESWDEFERREDXMT                       0x00008000
 280 #define IPG_SM_LATECOLLISIONS                   0x00010000
 281 #define IPG_SM_MULTICOLFRAMES                   0x00020000
 282 #define IPG_SM_SINGLECOLFRAMES                  0x00040000
 283 #define IPG_SM_TXJUMBOFRAMES                            0x00080000
 284 #define IPG_SM_CARRIERSENSEERRORS                       0x00100000
 285 #define IPG_SM_MACCONTROLFRAMESXMTD                     0x00200000
 286 #define IPG_SM_FRAMESABORTXSCOLLS                       0x00400000
 287 #define IPG_SM_FRAMESWEXDEFERAL                 0x00800000
 288
 289 /* Countdown */
 290 #define IPG_CD_RSVD_MASK                0x0700FFFF
 291 #define IPG_CD_COUNT                    0x0000FFFF
 292 #define IPG_CD_COUNTDOWNSPEED   0x01000000
 293 #define IPG_CD_COUNTDOWNMODE            0x02000000
 294 #define IPG_CD_COUNTINTENABLED  0x04000000
 295
 296 /* TxDMABurstThresh */
 297 #define IPG_TB_RSVD_MASK                0xFF
 298
 299 /* TxDMAUrgentThresh */
 300 #define IPG_TU_RSVD_MASK                0xFF
 301
 302 /* TxDMAPollPeriod */
 303 #define IPG_TP_RSVD_MASK                0xFF
 304
 305 /* RxDMAUrgentThresh */
 306 #define IPG_RU_RSVD_MASK                0xFF
 307
 308 /* RxDMAPollPeriod */
 309 #define IPG_RP_RSVD_MASK                0xFF
 310
 311 /* ReceiveMode */
 312 #define IPG_RM_RSVD_MASK                0x3F
 313 #define IPG_RM_RECEIVEUNICAST           0x01
 314 #define IPG_RM_RECEIVEMULTICAST         0x02
 315 #define IPG_RM_RECEIVEBROADCAST         0x04
 316 #define IPG_RM_RECEIVEALLFRAMES         0x08
 317 #define IPG_RM_RECEIVEMULTICASTHASH     0x10
 318 #define IPG_RM_RECEIVEIPMULTICAST       0x20
 319
 320 /* PhySet JES20040127EEPROM*/
 321 #define IPG_PS_MEM_LENB9B               0x01
 322 #define IPG_PS_MEM_LEN9                 0x02
 323 #define IPG_PS_NON_COMPDET              0x04
 324
 325 /* PhyCtrl */
 326 #define IPG_PC_RSVD_MASK                0xFF
 327 #define IPG_PC_MGMTCLK_LO               0x00
 328 #define IPG_PC_MGMTCLK_HI               0x01
 329 #define IPG_PC_MGMTCLK                  0x01
 330 #define IPG_PC_MGMTDATA                 0x02
 331 #define IPG_PC_MGMTDIR                  0x04
 332 #define IPG_PC_DUPLEX_POLARITY          0x08
 333 #define IPG_PC_DUPLEX_STATUS            0x10
 334 #define IPG_PC_LINK_POLARITY            0x20
 335 #define IPG_PC_LINK_SPEED               0xC0
 336 #define IPG_PC_LINK_SPEED_10MBPS        0x40
 337 #define IPG_PC_LINK_SPEED_100MBPS       0x80
 338 #define IPG_PC_LINK_SPEED_1000MBPS      0xC0
 339
 340 /* DMACtrl */
 341 #define IPG_DC_RSVD_MASK                0xC07D9818
 342 #define IPG_DC_RX_DMA_COMPLETE          0x00000008
 343 #define IPG_DC_RX_DMA_POLL_NOW          0x00000010
 344 #define IPG_DC_TX_DMA_COMPLETE          0x00000800
 345 #define IPG_DC_TX_DMA_POLL_NOW          0x00001000
 346 #define IPG_DC_TX_DMA_IN_PROG           0x00008000
 347 #define IPG_DC_RX_EARLY_DISABLE         0x00010000
 348 #define IPG_DC_MWI_DISABLE              0x00040000
 349 #define IPG_DC_TX_WRITE_BACK_DISABLE    0x00080000
 350 #define IPG_DC_TX_BURST_LIMIT           0x00700000
 351 #define IPG_DC_TARGET_ABORT             0x40000000
 352 #define IPG_DC_MASTER_ABORT             0x80000000
 353
 354 /* ASICCtrl */
 355 #define IPG_AC_RSVD_MASK                0x07FFEFF2
 356 #define IPG_AC_EXP_ROM_SIZE             0x00000002
 357 #define IPG_AC_PHY_SPEED10              0x00000010
 358 #define IPG_AC_PHY_SPEED100             0x00000020
 359 #define IPG_AC_PHY_SPEED1000            0x00000040
 360 #define IPG_AC_PHY_MEDIA                0x00000080
 361 #define IPG_AC_FORCED_CFG               0x00000700
 362 #define IPG_AC_D3RESETDISABLE           0x00000800
 363 #define IPG_AC_SPEED_UP_MODE            0x00002000
 364 #define IPG_AC_LED_MODE                 0x00004000
 365 #define IPG_AC_RST_OUT_POLARITY         0x00008000
 366 #define IPG_AC_GLOBAL_RESET             0x00010000
 367 #define IPG_AC_RX_RESET                 0x00020000
 368 #define IPG_AC_TX_RESET                 0x00040000
 369 #define IPG_AC_DMA                      0x00080000
 370 #define IPG_AC_FIFO                     0x00100000
 371 #define IPG_AC_NETWORK                  0x00200000
 372 #define IPG_AC_HOST                     0x00400000
 373 #define IPG_AC_AUTO_INIT                0x00800000
 374 #define IPG_AC_RST_OUT                  0x01000000
 375 #define IPG_AC_INT_REQUEST              0x02000000
 376 #define IPG_AC_RESET_BUSY               0x04000000
 377 #define IPG_AC_LED_SPEED                0x08000000      //JES20040127EEPROM
 378 #define IPG_AC_LED_MODE_BIT_1           0x20000000      //JES20040127EEPROM
 379
 380 /* EepromCtrl */
 381 #define IPG_EC_RSVD_MASK                0x83FF
 382 #define IPG_EC_EEPROM_ADDR              0x00FF
 383 #define IPG_EC_EEPROM_OPCODE            0x0300
 384 #define IPG_EC_EEPROM_SUBCOMMAD         0x0000
 385 #define IPG_EC_EEPROM_WRITEOPCODE       0x0100
 386 #define IPG_EC_EEPROM_READOPCODE        0x0200
 387 #define IPG_EC_EEPROM_ERASEOPCODE       0x0300
 388 #define IPG_EC_EEPROM_BUSY              0x8000
 389
 390 /* FIFOCtrl */
 391 #define IPG_FC_RSVD_MASK                0xC001
 392 #define IPG_FC_RAM_TEST_MODE            0x0001
 393 #define IPG_FC_TRANSMITTING             0x4000
 394 #define IPG_FC_RECEIVING                0x8000
 395
 396 /* TxStatus */
 397 #define IPG_TS_RSVD_MASK                0xFFFF00DD
 398 #define IPG_TS_TX_ERROR                 0x00000001
 399 #define IPG_TS_LATE_COLLISION           0x00000004
 400 #define IPG_TS_TX_MAX_COLL              0x00000008
 401 #define IPG_TS_TX_UNDERRUN              0x00000010
 402 #define IPG_TS_TX_IND_REQD              0x00000040
 403 #define IPG_TS_TX_COMPLETE              0x00000080
 404 #define IPG_TS_TX_FRAMEID               0xFFFF0000
 405
 406 /* WakeEvent */
 407 #define IPG_WE_WAKE_PKT_ENABLE          0x01
 408 #define IPG_WE_MAGIC_PKT_ENABLE         0x02
 409 #define IPG_WE_LINK_EVT_ENABLE          0x04
 410 #define IPG_WE_WAKE_POLARITY            0x08
 411 #define IPG_WE_WAKE_PKT_EVT             0x10
 412 #define IPG_WE_MAGIC_PKT_EVT            0x20
 413 #define IPG_WE_LINK_EVT                 0x40
 414 #define IPG_WE_WOL_ENABLE               0x80
 415
 416 /* IntEnable */
 417 #define IPG_IE_RSVD_MASK                0x1FFE
 418 #define IPG_IE_HOST_ERROR               0x0002
 419 #define IPG_IE_TX_COMPLETE              0x0004
 420 #define IPG_IE_MAC_CTRL_FRAME           0x0008
 421 #define IPG_IE_RX_COMPLETE              0x0010
 422 #define IPG_IE_RX_EARLY                 0x0020
 423 #define IPG_IE_INT_REQUESTED            0x0040
 424 #define IPG_IE_UPDATE_STATS             0x0080
 425 #define IPG_IE_LINK_EVENT               0x0100
 426 #define IPG_IE_TX_DMA_COMPLETE          0x0200
 427 #define IPG_IE_RX_DMA_COMPLETE          0x0400
 428 #define IPG_IE_RFD_LIST_END             0x0800
 429 #define IPG_IE_RX_DMA_PRIORITY          0x1000
 430
 431 /* IntStatus */
 432 #define IPG_IS_RSVD_MASK                0x1FFF
 433 #define IPG_IS_INTERRUPT_STATUS         0x0001
 434 #define IPG_IS_HOST_ERROR               0x0002
 435 #define IPG_IS_TX_COMPLETE              0x0004
 436 #define IPG_IS_MAC_CTRL_FRAME           0x0008
 437 #define IPG_IS_RX_COMPLETE              0x0010
 438 #define IPG_IS_RX_EARLY                 0x0020
 439 #define IPG_IS_INT_REQUESTED            0x0040
 440 #define IPG_IS_UPDATE_STATS             0x0080
 441 #define IPG_IS_LINK_EVENT               0x0100
 442 #define IPG_IS_TX_DMA_COMPLETE          0x0200
 443 #define IPG_IS_RX_DMA_COMPLETE          0x0400
 444 #define IPG_IS_RFD_LIST_END             0x0800
 445 #define IPG_IS_RX_DMA_PRIORITY          0x1000
 446
 447 /* MACCtrl */
 448 #define IPG_MC_RSVD_MASK                0x7FE33FA3
 449 #define IPG_MC_IFS_SELECT               0x00000003
 450 #define IPG_MC_IFS_4352BIT              0x00000003
 451 #define IPG_MC_IFS_1792BIT              0x00000002
 452 #define IPG_MC_IFS_1024BIT              0x00000001
 453 #define IPG_MC_IFS_96BIT                0x00000000
 454 #define IPG_MC_DUPLEX_SELECT            0x00000020
 455 #define IPG_MC_DUPLEX_SELECT_FD         0x00000020
 456 #define IPG_MC_DUPLEX_SELECT_HD         0x00000000
 457 #define IPG_MC_TX_FLOW_CONTROL_ENABLE   0x00000080
 458 #define IPG_MC_RX_FLOW_CONTROL_ENABLE   0x00000100
 459 #define IPG_MC_RCV_FCS                  0x00000200
 460 #define IPG_MC_FIFO_LOOPBACK            0x00000400
 461 #define IPG_MC_MAC_LOOPBACK             0x00000800
 462 #define IPG_MC_AUTO_VLAN_TAGGING        0x00001000
 463 #define IPG_MC_AUTO_VLAN_UNTAGGING      0x00002000
 464 #define IPG_MC_COLLISION_DETECT         0x00010000
 465 #define IPG_MC_CARRIER_SENSE            0x00020000
 466 #define IPG_MC_STATISTICS_ENABLE        0x00200000
 467 #define IPG_MC_STATISTICS_DISABLE       0x00400000
 468 #define IPG_MC_STATISTICS_ENABLED       0x00800000
 469 #define IPG_MC_TX_ENABLE                0x01000000
 470 #define IPG_MC_TX_DISABLE               0x02000000
 471 #define IPG_MC_TX_ENABLED               0x04000000
 472 #define IPG_MC_RX_ENABLE                0x08000000
 473 #define IPG_MC_RX_DISABLE               0x10000000
 474 #define IPG_MC_RX_ENABLED               0x20000000
 475 #define IPG_MC_PAUSED                   0x40000000
 476
 477 /*
 478  *      Tune
 479  */
 480
 481 /* Assign IPG_APPEND_FCS_ON_TX > 0 for auto FCS append on TX. */
 482 #define         IPG_APPEND_FCS_ON_TX         1
 483
 484 /* Assign IPG_APPEND_FCS_ON_TX > 0 for auto FCS strip on RX. */
 485 #define         IPG_STRIP_FCS_ON_RX          1
 486
 487 /* Assign IPG_DROP_ON_RX_ETH_ERRORS > 0 to drop RX frames with
 488  * Ethernet errors.
 489  */
 490 #define         IPG_DROP_ON_RX_ETH_ERRORS    1
 491
 492 /* Assign IPG_INSERT_MANUAL_VLAN_TAG > 0 to insert VLAN tags manually
 493  * (via TFC).
 494  */
 495 #define         IPG_INSERT_MANUAL_VLAN_TAG   0
 496
 497 /* Assign IPG_ADD_IPCHECKSUM_ON_TX > 0 for auto IP checksum on TX. */
 498 #define         IPG_ADD_IPCHECKSUM_ON_TX     0
 499
 500 /* Assign IPG_ADD_TCPCHECKSUM_ON_TX > 0 for auto TCP checksum on TX.
 501  * DO NOT USE FOR SILICON REVISIONS B3 AND EARLIER.
 502  */
 503 #define         IPG_ADD_TCPCHECKSUM_ON_TX    0
 504
 505 /* Assign IPG_ADD_UDPCHECKSUM_ON_TX > 0 for auto UDP checksum on TX.
 506  * DO NOT USE FOR SILICON REVISIONS B3 AND EARLIER.
 507  */
 508 #define         IPG_ADD_UDPCHECKSUM_ON_TX    0
 509
 510 /* If inserting VLAN tags manually, assign the IPG_MANUAL_VLAN_xx
 511  * constants as desired.
 512  */
 513 #define         IPG_MANUAL_VLAN_VID             0xABC
 514 #define         IPG_MANUAL_VLAN_CFI             0x1
 515 #define         IPG_MANUAL_VLAN_USERPRIORITY 0x5
 516
 517 #define         IPG_IO_REG_RANGE                0xFF
 518 #define         IPG_MEM_REG_RANGE               0x154
 519 #define         IPG_DRIVER_NAME         "Sundance Technology IPG Triple-Speed Ethernet"
 520 #define         IPG_NIC_PHY_ADDRESS          0x01
 521 #define         IPG_DMALIST_ALIGN_PAD   0x07
 522 #define         IPG_MULTICAST_HASHTABLE_SIZE    0x40
 523
 524 /* Number of miliseconds to wait after issuing a software reset.
 525  * 0x05 <= IPG_AC_RESETWAIT to account for proper 10Mbps operation.
 526  */
 527 #define         IPG_AC_RESETWAIT             0x05
 528
 529 /* Number of IPG_AC_RESETWAIT timeperiods before declaring timeout. */
 530 #define         IPG_AC_RESET_TIMEOUT         0x0A
 531
 532 /* Minimum number of nanoseconds used to toggle MDC clock during
 533  * MII/GMII register access.
 534  */
 535 #define         IPG_PC_PHYCTRLWAIT_NS           200
 536
 537 #define         IPG_TFDLIST_LENGTH              0x100
 538
 539 /* Number of frames between TxDMAComplete interrupt.
 540  * 0 < IPG_FRAMESBETWEENTXDMACOMPLETES <= IPG_TFDLIST_LENGTH
 541  */
 542 #define         IPG_FRAMESBETWEENTXDMACOMPLETES 0x1
 543
 544 #ifdef JUMBO_FRAME
 545
 546 # ifdef JUMBO_FRAME_SIZE_2K
 547 # define JUMBO_FRAME_SIZE 2048
 548 # define __IPG_RXFRAG_SIZE 2048
 549 # else
 550 #  ifdef JUMBO_FRAME_SIZE_3K
 551 #  define JUMBO_FRAME_SIZE 3072
 552 #  define __IPG_RXFRAG_SIZE 3072
 553 #  else
 554 #   ifdef JUMBO_FRAME_SIZE_4K
 555 #   define JUMBO_FRAME_SIZE 4096
 556 #   define __IPG_RXFRAG_SIZE 4088
 557 #   else
 558 #    ifdef JUMBO_FRAME_SIZE_5K
 559 #    define JUMBO_FRAME_SIZE 5120
 560 #    define __IPG_RXFRAG_SIZE 4088
 561 #    else
 562 #     ifdef JUMBO_FRAME_SIZE_6K
 563 #     define JUMBO_FRAME_SIZE 6144
 564 #     define __IPG_RXFRAG_SIZE 4088
 565 #     else
 566 #      ifdef JUMBO_FRAME_SIZE_7K
 567 #      define JUMBO_FRAME_SIZE 7168
 568 #      define __IPG_RXFRAG_SIZE 4088
 569 #      else
 570 #       ifdef JUMBO_FRAME_SIZE_8K
 571 #       define JUMBO_FRAME_SIZE 8192
 572 #       define __IPG_RXFRAG_SIZE 4088
 573 #       else
 574 #        ifdef JUMBO_FRAME_SIZE_9K
 575 #        define JUMBO_FRAME_SIZE 9216
 576 #        define __IPG_RXFRAG_SIZE 4088
 577 #        else
 578 #         ifdef JUMBO_FRAME_SIZE_10K
 579 #         define JUMBO_FRAME_SIZE 10240
 580 #         define __IPG_RXFRAG_SIZE 4088
 581 #         else
 582 #         define JUMBO_FRAME_SIZE 4096
 583 #         endif
 584 #        endif
 585 #       endif
 586 #      endif
 587 #     endif
 588 #    endif
 589 #   endif
 590 #  endif
 591 # endif
 592 #endif
 593
 594 /* Size of allocated received buffers. Nominally 0x0600.
 595  * Define larger if expecting jumbo frames.
 596  */
 597 #ifdef JUMBO_FRAME
 598 //IPG_TXFRAG_SIZE must <= 0x2b00, or TX will crash
 599 #define         IPG_TXFRAG_SIZE         JUMBO_FRAME_SIZE
 600 #endif
 601
 602 /* Size of allocated received buffers. Nominally 0x0600.
 603  * Define larger if expecting jumbo frames.
 604  */
 605 #ifdef JUMBO_FRAME
 606 //4088=4096-8
 607 #define         IPG_RXFRAG_SIZE         __IPG_RXFRAG_SIZE
 608 #define     IPG_RXSUPPORT_SIZE   IPG_MAX_RXFRAME_SIZE
 609 #else
 610 #define         IPG_RXFRAG_SIZE         0x0600
 611 #define     IPG_RXSUPPORT_SIZE   IPG_RXFRAG_SIZE
 612 #endif
 613
 614 /* IPG_MAX_RXFRAME_SIZE <= IPG_RXFRAG_SIZE */
 615 #ifdef JUMBO_FRAME
 616 #define         IPG_MAX_RXFRAME_SIZE            JUMBO_FRAME_SIZE
 617 #else
 618 #define         IPG_MAX_RXFRAME_SIZE            0x0600
 619 #endif
 620
 621 #define         IPG_RFDLIST_LENGTH              0x100
 622
 623 /* Maximum number of RFDs to process per interrupt.
 624  * 1 < IPG_MAXRFDPROCESS_COUNT < IPG_RFDLIST_LENGTH
 625  */
 626 #define         IPG_MAXRFDPROCESS_COUNT 0x80
 627
 628 /* Minimum margin between last freed RFD, and current RFD.
 629  * 1 < IPG_MINUSEDRFDSTOFREE < IPG_RFDLIST_LENGTH
 630  */
 631 #define         IPG_MINUSEDRFDSTOFREE   0x80
 632
 633 /* specify the jumbo frame maximum size
 634  * per unit is 0x600 (the RxBuffer size that one RFD can carry)
 635  */
 636 #define     MAX_JUMBOSIZE               0x8     // max is 12K
 637
 638 /* Key register values loaded at driver start up. */
 639
 640 /* TXDMAPollPeriod is specified in 320ns increments.
 641  *
 642  * Value        Time
 643  * ---------------------
 644  * 0x00-0x01    320ns
 645  * 0x03         ~1us
 646  * 0x1F         ~10us
 647  * 0xFF         ~82us
 648  */
 649 #define         IPG_TXDMAPOLLPERIOD_VALUE       0x26
 650
 651 /* TxDMAUrgentThresh specifies the minimum amount of
 652  * data in the transmit FIFO before asserting an
 653  * urgent transmit DMA request.
 654  *
 655  * Value        Min TxFIFO occupied space before urgent TX request
 656  * ---------------------------------------------------------------
 657  * 0x00-0x04    128 bytes (1024 bits)
 658  * 0x27         1248 bytes (~10000 bits)
 659  * 0x30         1536 bytes (12288 bits)
 660  * 0xFF         8192 bytes (65535 bits)
 661  */
 662 #define         IPG_TXDMAURGENTTHRESH_VALUE     0x04
 663
 664 /* TxDMABurstThresh specifies the minimum amount of
 665  * free space in the transmit FIFO before asserting an
 666  * transmit DMA request.
 667  *
 668  * Value        Min TxFIFO free space before TX request
 669  * ----------------------------------------------------
 670  * 0x00-0x08    256 bytes
 671  * 0x30         1536 bytes
 672  * 0xFF         8192 bytes
 673  */
 674 #define         IPG_TXDMABURSTTHRESH_VALUE      0x30
 675
 676 /* RXDMAPollPeriod is specified in 320ns increments.
 677  *
 678  * Value        Time
 679  * ---------------------
 680  * 0x00-0x01    320ns
 681  * 0x03         ~1us
 682  * 0x1F         ~10us
 683  * 0xFF         ~82us
 684  */
 685 #define         IPG_RXDMAPOLLPERIOD_VALUE       0x01
 686
 687 /* RxDMAUrgentThresh specifies the minimum amount of
 688  * free space within the receive FIFO before asserting
 689  * a urgent receive DMA request.
 690  *
 691  * Value        Min RxFIFO free space before urgent RX request
 692  * ---------------------------------------------------------------
 693  * 0x00-0x04    128 bytes (1024 bits)
 694  * 0x27         1248 bytes (~10000 bits)
 695  * 0x30         1536 bytes (12288 bits)
 696  * 0xFF         8192 bytes (65535 bits)
 697  */
 698 #define         IPG_RXDMAURGENTTHRESH_VALUE     0x30
 699
 700 /* RxDMABurstThresh specifies the minimum amount of
 701  * occupied space within the receive FIFO before asserting
 702  * a receive DMA request.
 703  *
 704  * Value        Min TxFIFO free space before TX request
 705  * ----------------------------------------------------
 706  * 0x00-0x08    256 bytes
 707  * 0x30         1536 bytes
 708  * 0xFF         8192 bytes
 709  */
 710 #define         IPG_RXDMABURSTTHRESH_VALUE      0x30
 711
 712 /* FlowOnThresh specifies the maximum amount of occupied
 713  * space in the receive FIFO before a PAUSE frame with
 714  * maximum pause time transmitted.
 715  *
 716  * Value        Max RxFIFO occupied space before PAUSE
 717  * ---------------------------------------------------
 718  * 0x0000       0 bytes
 719  * 0x0740       29,696 bytes
 720  * 0x07FF       32,752 bytes
 721  */
 722 #define         IPG_FLOWONTHRESH_VALUE  0x0740
 723
 724 /* FlowOffThresh specifies the minimum amount of occupied
 725  * space in the receive FIFO before a PAUSE frame with
 726  * zero pause time is transmitted.
 727  *
 728  * Value        Max RxFIFO occupied space before PAUSE
 729  * ---------------------------------------------------
 730  * 0x0000       0 bytes
 731  * 0x00BF       3056 bytes
 732  * 0x07FF       32,752 bytes
 733  */
 734 #define         IPG_FLOWOFFTHRESH_VALUE 0x00BF
 735
 736 /*
 737  * Miscellaneous macros.
 738  */
 739
 740 /* Marco for printing debug statements.
 741 #  define IPG_DDEBUG_MSG(args...) printk(KERN_DEBUG "IPG: " ## args) */
 742 #ifdef IPG_DEBUG
 743 #  define IPG_DEBUG_MSG(args...)
 744 #  define IPG_DDEBUG_MSG(args...) printk(KERN_DEBUG "IPG: " args)
 745 #  define IPG_DUMPRFDLIST(args) ipg_dump_rfdlist(args)
 746 #  define IPG_DUMPTFDLIST(args) ipg_dump_tfdlist(args)
 747 #else
 748 #  define IPG_DEBUG_MSG(args...)
 749 #  define IPG_DDEBUG_MSG(args...)
 750 #  define IPG_DUMPRFDLIST(args)
 751 #  define IPG_DUMPTFDLIST(args)
 752 #endif
 753
 754 /*
 755  * End miscellaneous macros.
 756  */
 757
 758 /* Transmit Frame Descriptor. The IPG supports 15 fragments,
 759  * however Linux requires only a single fragment. Note, each
 760  * TFD field is 64 bits wide.
 761  */
 762 struct ipg_tx {
 763         __le64 next_desc;
 764         __le64 tfc;
 765         __le64 frag_info;
 766 };
 767
 768 /* Receive Frame Descriptor. Note, each RFD field is 64 bits wide.
 769  */
 770 struct ipg_rx {
 771         __le64 next_desc;
 772         __le64 rfs;
 773         __le64 frag_info;
 774 };
 775
 776 struct SJumbo {
 777         int FoundStart;
 778         int CurrentSize;
 779         struct sk_buff *skb;
 780 };
 781 /* Structure of IPG NIC specific data. */
 782 struct ipg_nic_private {
 783         void __iomem *ioaddr;
 784         struct ipg_tx *txd;
 785         struct ipg_rx *rxd;
 786         dma_addr_t txd_map;
 787         dma_addr_t rxd_map;
 788         struct sk_buff *TxBuff[IPG_TFDLIST_LENGTH];
 789         struct sk_buff *RxBuff[IPG_RFDLIST_LENGTH];
 790         unsigned int tx_current;
 791         unsigned int tx_dirty;
 792         unsigned int rx_current;
 793         unsigned int rx_dirty;
 794 // Add by Grace 2005/05/19
 795 #ifdef JUMBO_FRAME
 796         struct SJumbo Jumbo;
 797 #endif
 798         unsigned int rx_buf_sz;
 799         struct pci_dev *pdev;
 800         struct net_device *dev;
 801         struct net_device_stats stats;
 802         spinlock_t lock;
 803         int tenmbpsmode;
 804
 805         /*Jesse20040128EEPROM_VALUE */
 806         u16 LED_Mode;
 807         u16 station_addr[3];    /* Station Address in EEPROM Reg 0x10..0x12 */
 808
 809         struct mutex            mii_mutex;
 810         struct mii_if_info      mii_if;
 811         int ResetCurrentTFD;
 812 #ifdef IPG_DEBUG
 813         int RFDlistendCount;
 814         int RFDListCheckedCount;
 815         int EmptyRFDListCount;
 816 #endif
 817         struct delayed_work task;
 818 };
 819
 820 #endif                          /* __LINUX_IPG_H */