2 * drivers/net/mv643xx_eth.c - Driver for MV643XX ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 rabeeh@galileo.co.il
8 * Copyright (C) 2003 PMC-Sierra, Inc.,
9 * written by Manish Lachwani
11 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 * Copyright (C) 2004-2005 MontaVista Software, Inc.
14 * Dale Farnsworth <dale@farnsworth.org>
16 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
17 * <sjhill@realitydiluted.com>
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version 2
22 * of the License, or (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
33 #include <linux/init.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/tcp.h>
36 #include <linux/udp.h>
37 #include <linux/etherdevice.h>
41 #include <linux/bitops.h>
42 #include <linux/delay.h>
43 #include <linux/ethtool.h>
44 #include <linux/platform_device.h>
47 #include <asm/types.h>
48 #include <asm/pgtable.h>
49 #include <asm/system.h>
50 #include <asm/delay.h>
51 #include "mv643xx_eth.h"
54 * The first part is the high level driver of the gigE ethernet ports.
60 #define WRAP NET_IP_ALIGN + ETH_HLEN + VLAN_HLEN + FCS_LEN
61 #define RX_SKB_SIZE ((dev->mtu + WRAP + 7) & ~0x7)
63 #define INT_CAUSE_UNMASK_ALL 0x0007ffff
64 #define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff
65 #define INT_CAUSE_MASK_ALL 0x00000000
66 #define INT_CAUSE_MASK_ALL_EXT 0x00000000
67 #define INT_CAUSE_CHECK_BITS INT_CAUSE_UNMASK_ALL
68 #define INT_CAUSE_CHECK_BITS_EXT INT_CAUSE_UNMASK_ALL_EXT
70 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
71 #define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
73 #define MAX_DESCS_PER_SKB 1
76 #define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */
77 #define PHY_WAIT_MICRO_SECONDS 10
79 /* Static function declarations */
80 static int eth_port_link_is_up(unsigned int eth_port_num);
81 static void eth_port_uc_addr_get(struct net_device *dev,
82 unsigned char *MacAddr);
83 static void eth_port_set_multicast_list(struct net_device *);
84 static int mv643xx_eth_real_open(struct net_device *);
85 static int mv643xx_eth_real_stop(struct net_device *);
86 static int mv643xx_eth_change_mtu(struct net_device *, int);
87 static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *);
88 static void eth_port_init_mac_tables(unsigned int eth_port_num);
90 static int mv643xx_poll(struct net_device *dev, int *budget);
92 static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr);
93 static int ethernet_phy_detect(unsigned int eth_port_num);
94 static struct ethtool_ops mv643xx_ethtool_ops;
96 static char mv643xx_driver_name[] = "mv643xx_eth";
97 static char mv643xx_driver_version[] = "1.0";
99 static void __iomem *mv643xx_eth_shared_base;
101 /* used to protect MV643XX_ETH_SMI_REG, which is shared across ports */
102 static DEFINE_SPINLOCK(mv643xx_eth_phy_lock);
104 static inline u32 mv_read(int offset)
106 void __iomem *reg_base;
108 reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS;
110 return readl(reg_base + offset);
113 static inline void mv_write(int offset, u32 data)
115 void __iomem *reg_base;
117 reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS;
118 writel(data, reg_base + offset);
122 * Changes MTU (maximum transfer unit) of the gigabit ethenret port
124 * Input : pointer to ethernet interface network device structure
126 * Output : 0 upon success, -EINVAL upon failure
128 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
130 struct mv643xx_private *mp = netdev_priv(dev);
133 spin_lock_irqsave(&mp->lock, flags);
135 if ((new_mtu > 9500) || (new_mtu < 64)) {
136 spin_unlock_irqrestore(&mp->lock, flags);
142 * Stop then re-open the interface. This will allocate RX skb's with
144 * There is a possible danger that the open will not successed, due
145 * to memory is full, which might fail the open function.
147 if (netif_running(dev)) {
148 if (mv643xx_eth_real_stop(dev))
150 "%s: Fatal error on stopping device\n",
152 if (mv643xx_eth_real_open(dev))
154 "%s: Fatal error on opening device\n",
158 spin_unlock_irqrestore(&mp->lock, flags);
163 * mv643xx_eth_rx_task
165 * Fills / refills RX queue on a certain gigabit ethernet port
167 * Input : pointer to ethernet interface network device structure
170 static void mv643xx_eth_rx_task(void *data)
172 struct net_device *dev = (struct net_device *)data;
173 struct mv643xx_private *mp = netdev_priv(dev);
174 struct pkt_info pkt_info;
177 if (test_and_set_bit(0, &mp->rx_task_busy))
178 panic("%s: Error in test_set_bit / clear_bit", dev->name);
180 while (mp->rx_ring_skbs < (mp->rx_ring_size - 5)) {
181 skb = dev_alloc_skb(RX_SKB_SIZE);
185 pkt_info.cmd_sts = ETH_RX_ENABLE_INTERRUPT;
186 pkt_info.byte_cnt = RX_SKB_SIZE;
187 pkt_info.buf_ptr = dma_map_single(NULL, skb->data, RX_SKB_SIZE,
189 pkt_info.return_info = skb;
190 if (eth_rx_return_buff(mp, &pkt_info) != ETH_OK) {
192 "%s: Error allocating RX Ring\n", dev->name);
197 clear_bit(0, &mp->rx_task_busy);
199 * If RX ring is empty of SKB, set a timer to try allocating
200 * again in a later time .
202 if ((mp->rx_ring_skbs == 0) && (mp->rx_timer_flag == 0)) {
203 printk(KERN_INFO "%s: Rx ring is empty\n", dev->name);
205 mp->timeout.expires = jiffies + (HZ / 10);
206 add_timer(&mp->timeout);
207 mp->rx_timer_flag = 1;
209 #ifdef MV643XX_RX_QUEUE_FILL_ON_TASK
211 /* Return interrupts */
212 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(mp->port_num),
213 INT_CAUSE_UNMASK_ALL);
219 * mv643xx_eth_rx_task_timer_wrapper
221 * Timer routine to wake up RX queue filling task. This function is
222 * used only in case the RX queue is empty, and all alloc_skb has
223 * failed (due to out of memory event).
225 * Input : pointer to ethernet interface network device structure
228 static void mv643xx_eth_rx_task_timer_wrapper(unsigned long data)
230 struct net_device *dev = (struct net_device *)data;
231 struct mv643xx_private *mp = netdev_priv(dev);
233 mp->rx_timer_flag = 0;
234 mv643xx_eth_rx_task((void *)data);
238 * mv643xx_eth_update_mac_address
240 * Update the MAC address of the port in the address table
242 * Input : pointer to ethernet interface network device structure
245 static void mv643xx_eth_update_mac_address(struct net_device *dev)
247 struct mv643xx_private *mp = netdev_priv(dev);
248 unsigned int port_num = mp->port_num;
250 eth_port_init_mac_tables(port_num);
251 memcpy(mp->port_mac_addr, dev->dev_addr, 6);
252 eth_port_uc_addr_set(port_num, mp->port_mac_addr);
256 * mv643xx_eth_set_rx_mode
258 * Change from promiscuos to regular rx mode
260 * Input : pointer to ethernet interface network device structure
263 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
265 struct mv643xx_private *mp = netdev_priv(dev);
267 if (dev->flags & IFF_PROMISC)
268 mp->port_config |= (u32) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE;
270 mp->port_config &= ~(u32) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE;
272 mv_write(MV643XX_ETH_PORT_CONFIG_REG(mp->port_num), mp->port_config);
274 eth_port_set_multicast_list(dev);
278 * mv643xx_eth_set_mac_address
280 * Change the interface's mac address.
281 * No special hardware thing should be done because interface is always
282 * put in promiscuous mode.
284 * Input : pointer to ethernet interface network device structure and
285 * a pointer to the designated entry to be added to the cache.
286 * Output : zero upon success, negative upon failure
288 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
292 for (i = 0; i < 6; i++)
293 /* +2 is for the offset of the HW addr type */
294 dev->dev_addr[i] = ((unsigned char *)addr)[i + 2];
295 mv643xx_eth_update_mac_address(dev);
300 * mv643xx_eth_tx_timeout
302 * Called upon a timeout on transmitting a packet
304 * Input : pointer to ethernet interface network device structure.
307 static void mv643xx_eth_tx_timeout(struct net_device *dev)
309 struct mv643xx_private *mp = netdev_priv(dev);
311 printk(KERN_INFO "%s: TX timeout ", dev->name);
313 /* Do the reset outside of interrupt context */
314 schedule_work(&mp->tx_timeout_task);
318 * mv643xx_eth_tx_timeout_task
320 * Actual routine to reset the adapter when a timeout on Tx has occurred
322 static void mv643xx_eth_tx_timeout_task(struct net_device *dev)
324 struct mv643xx_private *mp = netdev_priv(dev);
326 netif_device_detach(dev);
327 eth_port_reset(mp->port_num);
329 netif_device_attach(dev);
333 * mv643xx_eth_free_tx_queue
335 * Input : dev - a pointer to the required interface
337 * Output : 0 if was able to release skb , nonzero otherwise
339 static int mv643xx_eth_free_tx_queue(struct net_device *dev,
340 unsigned int eth_int_cause_ext)
342 struct mv643xx_private *mp = netdev_priv(dev);
343 struct net_device_stats *stats = &mp->stats;
344 struct pkt_info pkt_info;
347 if (!(eth_int_cause_ext & (BIT0 | BIT8)))
350 spin_lock(&mp->lock);
352 /* Check only queue 0 */
353 while (eth_tx_return_desc(mp, &pkt_info) == ETH_OK) {
354 if (pkt_info.cmd_sts & BIT0) {
355 printk("%s: Error in TX\n", dev->name);
359 if (pkt_info.cmd_sts & ETH_TX_FIRST_DESC)
360 dma_unmap_single(NULL, pkt_info.buf_ptr,
364 dma_unmap_page(NULL, pkt_info.buf_ptr,
368 if (pkt_info.return_info) {
369 dev_kfree_skb_irq(pkt_info.return_info);
374 spin_unlock(&mp->lock);
380 * mv643xx_eth_receive
382 * This function is forward packets that are received from the port's
383 * queues toward kernel core or FastRoute them to another interface.
385 * Input : dev - a pointer to the required interface
386 * max - maximum number to receive (0 means unlimted)
388 * Output : number of served packets
391 static int mv643xx_eth_receive_queue(struct net_device *dev, int budget)
393 static int mv643xx_eth_receive_queue(struct net_device *dev)
396 struct mv643xx_private *mp = netdev_priv(dev);
397 struct net_device_stats *stats = &mp->stats;
398 unsigned int received_packets = 0;
400 struct pkt_info pkt_info;
403 while (budget-- > 0 && eth_port_receive(mp, &pkt_info) == ETH_OK) {
405 while (eth_port_receive(mp, &pkt_info) == ETH_OK) {
410 /* Update statistics. Note byte count includes 4 byte CRC count */
412 stats->rx_bytes += pkt_info.byte_cnt;
413 skb = pkt_info.return_info;
415 * In case received a packet without first / last bits on OR
416 * the error summary bit is on, the packets needs to be dropeed.
418 if (((pkt_info.cmd_sts
419 & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
420 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
421 || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
423 if ((pkt_info.cmd_sts & (ETH_RX_FIRST_DESC |
424 ETH_RX_LAST_DESC)) !=
425 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) {
428 "%s: Received packet spread "
429 "on multiple descriptors\n",
432 if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)
435 dev_kfree_skb_irq(skb);
438 * The -4 is for the CRC in the trailer of the
441 skb_put(skb, pkt_info.byte_cnt - 4);
444 if (pkt_info.cmd_sts & ETH_LAYER_4_CHECKSUM_OK) {
445 skb->ip_summed = CHECKSUM_UNNECESSARY;
447 (pkt_info.cmd_sts & 0x0007fff8) >> 3);
449 skb->protocol = eth_type_trans(skb, dev);
451 netif_receive_skb(skb);
458 return received_packets;
462 * mv643xx_eth_int_handler
464 * Main interrupt handler for the gigbit ethernet ports
466 * Input : irq - irq number (not used)
467 * dev_id - a pointer to the required interface's data structure
472 static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id,
473 struct pt_regs *regs)
475 struct net_device *dev = (struct net_device *)dev_id;
476 struct mv643xx_private *mp = netdev_priv(dev);
477 u32 eth_int_cause, eth_int_cause_ext = 0;
478 unsigned int port_num = mp->port_num;
480 /* Read interrupt cause registers */
481 eth_int_cause = mv_read(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num)) &
482 INT_CAUSE_UNMASK_ALL;
484 if (eth_int_cause & BIT1)
485 eth_int_cause_ext = mv_read(
486 MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num)) &
487 INT_CAUSE_UNMASK_ALL_EXT;
490 if (!(eth_int_cause & 0x0007fffd)) {
491 /* Dont ack the Rx interrupt */
494 * Clear specific ethernet port intrerrupt registers by
495 * acknowleding relevant bits.
497 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num),
499 if (eth_int_cause_ext != 0x0)
500 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG
501 (port_num), ~eth_int_cause_ext);
503 /* UDP change : We may need this */
504 if ((eth_int_cause_ext & 0x0000ffff) &&
505 (mv643xx_eth_free_tx_queue(dev, eth_int_cause_ext) == 0) &&
506 (mp->tx_ring_size > mp->tx_ring_skbs + MAX_DESCS_PER_SKB))
507 netif_wake_queue(dev);
510 if (netif_rx_schedule_prep(dev)) {
511 /* Mask all the interrupts */
512 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), 0);
513 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG
515 __netif_rx_schedule(dev);
518 if (eth_int_cause & (BIT2 | BIT11))
519 mv643xx_eth_receive_queue(dev, 0);
522 * After forwarded received packets to upper layer, add a task
523 * in an interrupts enabled context that refills the RX ring
526 #ifdef MV643XX_RX_QUEUE_FILL_ON_TASK
527 /* Unmask all interrupts on ethernet port */
528 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
530 queue_task(&mp->rx_task, &tq_immediate);
531 mark_bh(IMMEDIATE_BH);
533 mp->rx_task.func(dev);
537 /* PHY status changed */
538 if (eth_int_cause_ext & (BIT16 | BIT20)) {
539 if (eth_port_link_is_up(port_num)) {
540 netif_carrier_on(dev);
541 netif_wake_queue(dev);
543 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG
546 netif_carrier_off(dev);
547 netif_stop_queue(dev);
552 * If no real interrupt occured, exit.
553 * This can happen when using gigE interrupt coalescing mechanism.
555 if ((eth_int_cause == 0x0) && (eth_int_cause_ext == 0x0))
564 * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
567 * This routine sets the RX coalescing interrupt mechanism parameter.
568 * This parameter is a timeout counter, that counts in 64 t_clk
569 * chunks ; that when timeout event occurs a maskable interrupt
571 * The parameter is calculated using the tClk of the MV-643xx chip
572 * , and the required delay of the interrupt in usec.
575 * unsigned int eth_port_num Ethernet port number
576 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
577 * unsigned int delay Delay in usec
580 * Interrupt coalescing mechanism value is set in MV-643xx chip.
583 * The interrupt coalescing value set in the gigE port.
586 static unsigned int eth_port_set_rx_coal(unsigned int eth_port_num,
587 unsigned int t_clk, unsigned int delay)
589 unsigned int coal = ((t_clk / 1000000) * delay) / 64;
591 /* Set RX Coalescing mechanism */
592 mv_write(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num),
593 ((coal & 0x3fff) << 8) |
594 (mv_read(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num))
602 * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
605 * This routine sets the TX coalescing interrupt mechanism parameter.
606 * This parameter is a timeout counter, that counts in 64 t_clk
607 * chunks ; that when timeout event occurs a maskable interrupt
609 * The parameter is calculated using the t_cLK frequency of the
610 * MV-643xx chip and the required delay in the interrupt in uSec
613 * unsigned int eth_port_num Ethernet port number
614 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
615 * unsigned int delay Delay in uSeconds
618 * Interrupt coalescing mechanism value is set in MV-643xx chip.
621 * The interrupt coalescing value set in the gigE port.
624 static unsigned int eth_port_set_tx_coal(unsigned int eth_port_num,
625 unsigned int t_clk, unsigned int delay)
628 coal = ((t_clk / 1000000) * delay) / 64;
629 /* Set TX Coalescing mechanism */
630 mv_write(MV643XX_ETH_TX_FIFO_URGENT_THRESHOLD_REG(eth_port_num),
638 * This function is called when openning the network device. The function
639 * should initialize all the hardware, initialize cyclic Rx/Tx
640 * descriptors chain and buffers and allocate an IRQ to the network
643 * Input : a pointer to the network device structure
645 * Output : zero of success , nonzero if fails.
648 static int mv643xx_eth_open(struct net_device *dev)
650 struct mv643xx_private *mp = netdev_priv(dev);
651 unsigned int port_num = mp->port_num;
654 spin_lock_irq(&mp->lock);
656 err = request_irq(dev->irq, mv643xx_eth_int_handler,
657 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
660 printk(KERN_ERR "Can not assign IRQ number to MV643XX_eth%d\n",
666 if (mv643xx_eth_real_open(dev)) {
667 printk("%s: Error opening interface\n", dev->name);
672 spin_unlock_irq(&mp->lock);
677 free_irq(dev->irq, dev);
680 spin_unlock_irq(&mp->lock);
686 * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
689 * This function prepares a Rx chained list of descriptors and packet
690 * buffers in a form of a ring. The routine must be called after port
691 * initialization routine and before port start routine.
692 * The Ethernet SDMA engine uses CPU bus addresses to access the various
693 * devices in the system (i.e. DRAM). This function uses the ethernet
694 * struct 'virtual to physical' routine (set by the user) to set the ring
695 * with physical addresses.
698 * struct mv643xx_private *mp Ethernet Port Control srtuct.
701 * The routine updates the Ethernet port control struct with information
702 * regarding the Rx descriptors and buffers.
707 static void ether_init_rx_desc_ring(struct mv643xx_private *mp)
709 volatile struct eth_rx_desc *p_rx_desc;
710 int rx_desc_num = mp->rx_ring_size;
713 /* initialize the next_desc_ptr links in the Rx descriptors ring */
714 p_rx_desc = (struct eth_rx_desc *)mp->p_rx_desc_area;
715 for (i = 0; i < rx_desc_num; i++) {
716 p_rx_desc[i].next_desc_ptr = mp->rx_desc_dma +
717 ((i + 1) % rx_desc_num) * sizeof(struct eth_rx_desc);
720 /* Save Rx desc pointer to driver struct. */
721 mp->rx_curr_desc_q = 0;
722 mp->rx_used_desc_q = 0;
724 mp->rx_desc_area_size = rx_desc_num * sizeof(struct eth_rx_desc);
726 /* Add the queue to the list of RX queues of this port */
727 mp->port_rx_queue_command |= 1;
731 * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
734 * This function prepares a Tx chained list of descriptors and packet
735 * buffers in a form of a ring. The routine must be called after port
736 * initialization routine and before port start routine.
737 * The Ethernet SDMA engine uses CPU bus addresses to access the various
738 * devices in the system (i.e. DRAM). This function uses the ethernet
739 * struct 'virtual to physical' routine (set by the user) to set the ring
740 * with physical addresses.
743 * struct mv643xx_private *mp Ethernet Port Control srtuct.
746 * The routine updates the Ethernet port control struct with information
747 * regarding the Tx descriptors and buffers.
752 static void ether_init_tx_desc_ring(struct mv643xx_private *mp)
754 int tx_desc_num = mp->tx_ring_size;
755 struct eth_tx_desc *p_tx_desc;
758 /* Initialize the next_desc_ptr links in the Tx descriptors ring */
759 p_tx_desc = (struct eth_tx_desc *)mp->p_tx_desc_area;
760 for (i = 0; i < tx_desc_num; i++) {
761 p_tx_desc[i].next_desc_ptr = mp->tx_desc_dma +
762 ((i + 1) % tx_desc_num) * sizeof(struct eth_tx_desc);
765 mp->tx_curr_desc_q = 0;
766 mp->tx_used_desc_q = 0;
767 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
768 mp->tx_first_desc_q = 0;
771 mp->tx_desc_area_size = tx_desc_num * sizeof(struct eth_tx_desc);
773 /* Add the queue to the list of Tx queues of this port */
774 mp->port_tx_queue_command |= 1;
777 /* Helper function for mv643xx_eth_open */
778 static int mv643xx_eth_real_open(struct net_device *dev)
780 struct mv643xx_private *mp = netdev_priv(dev);
781 unsigned int port_num = mp->port_num;
785 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num), 0x0000ff00);
787 /* Clear the ethernet port interrupts */
788 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
789 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
791 /* Unmask RX buffer and TX end interrupt */
792 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
793 INT_CAUSE_UNMASK_ALL);
795 /* Unmask phy and link status changes interrupts */
796 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
797 INT_CAUSE_UNMASK_ALL_EXT);
799 /* Set the MAC Address */
800 memcpy(mp->port_mac_addr, dev->dev_addr, 6);
804 INIT_WORK(&mp->rx_task, (void (*)(void *))mv643xx_eth_rx_task, dev);
806 memset(&mp->timeout, 0, sizeof(struct timer_list));
807 mp->timeout.function = mv643xx_eth_rx_task_timer_wrapper;
808 mp->timeout.data = (unsigned long)dev;
810 mp->rx_task_busy = 0;
811 mp->rx_timer_flag = 0;
813 /* Allocate RX and TX skb rings */
814 mp->rx_skb = kmalloc(sizeof(*mp->rx_skb) * mp->rx_ring_size,
817 printk(KERN_ERR "%s: Cannot allocate Rx skb ring\n", dev->name);
820 mp->tx_skb = kmalloc(sizeof(*mp->tx_skb) * mp->tx_ring_size,
823 printk(KERN_ERR "%s: Cannot allocate Tx skb ring\n", dev->name);
828 /* Allocate TX ring */
829 mp->tx_ring_skbs = 0;
830 size = mp->tx_ring_size * sizeof(struct eth_tx_desc);
831 mp->tx_desc_area_size = size;
833 if (mp->tx_sram_size) {
834 mp->p_tx_desc_area = ioremap(mp->tx_sram_addr,
836 mp->tx_desc_dma = mp->tx_sram_addr;
838 mp->p_tx_desc_area = dma_alloc_coherent(NULL, size,
842 if (!mp->p_tx_desc_area) {
843 printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n",
849 BUG_ON((u32) mp->p_tx_desc_area & 0xf); /* check 16-byte alignment */
850 memset((void *)mp->p_tx_desc_area, 0, mp->tx_desc_area_size);
852 ether_init_tx_desc_ring(mp);
854 /* Allocate RX ring */
855 mp->rx_ring_skbs = 0;
856 size = mp->rx_ring_size * sizeof(struct eth_rx_desc);
857 mp->rx_desc_area_size = size;
859 if (mp->rx_sram_size) {
860 mp->p_rx_desc_area = ioremap(mp->rx_sram_addr,
862 mp->rx_desc_dma = mp->rx_sram_addr;
864 mp->p_rx_desc_area = dma_alloc_coherent(NULL, size,
868 if (!mp->p_rx_desc_area) {
869 printk(KERN_ERR "%s: Cannot allocate Rx ring (size %d bytes)\n",
871 printk(KERN_ERR "%s: Freeing previously allocated TX queues...",
873 if (mp->rx_sram_size)
874 iounmap(mp->p_rx_desc_area);
876 dma_free_coherent(NULL, mp->tx_desc_area_size,
877 mp->p_tx_desc_area, mp->tx_desc_dma);
882 memset((void *)mp->p_rx_desc_area, 0, size);
884 ether_init_rx_desc_ring(mp);
886 mv643xx_eth_rx_task(dev); /* Fill RX ring with skb's */
890 /* Interrupt Coalescing */
894 eth_port_set_rx_coal(port_num, 133000000, MV643XX_RX_COAL);
898 eth_port_set_tx_coal(port_num, 133000000, MV643XX_TX_COAL);
900 netif_start_queue(dev);
905 static void mv643xx_eth_free_tx_rings(struct net_device *dev)
907 struct mv643xx_private *mp = netdev_priv(dev);
908 unsigned int port_num = mp->port_num;
912 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num), 0x0000ff00);
914 /* Free outstanding skb's on TX rings */
915 for (curr = 0; mp->tx_ring_skbs && curr < mp->tx_ring_size; curr++) {
916 if (mp->tx_skb[curr]) {
917 dev_kfree_skb(mp->tx_skb[curr]);
921 if (mp->tx_ring_skbs)
922 printk("%s: Error on Tx descriptor free - could not free %d"
923 " descriptors\n", dev->name, mp->tx_ring_skbs);
926 if (mp->tx_sram_size)
927 iounmap(mp->p_tx_desc_area);
929 dma_free_coherent(NULL, mp->tx_desc_area_size,
930 mp->p_tx_desc_area, mp->tx_desc_dma);
933 static void mv643xx_eth_free_rx_rings(struct net_device *dev)
935 struct mv643xx_private *mp = netdev_priv(dev);
936 unsigned int port_num = mp->port_num;
940 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num), 0x0000ff00);
942 /* Free preallocated skb's on RX rings */
943 for (curr = 0; mp->rx_ring_skbs && curr < mp->rx_ring_size; curr++) {
944 if (mp->rx_skb[curr]) {
945 dev_kfree_skb(mp->rx_skb[curr]);
950 if (mp->rx_ring_skbs)
952 "%s: Error in freeing Rx Ring. %d skb's still"
953 " stuck in RX Ring - ignoring them\n", dev->name,
956 if (mp->rx_sram_size)
957 iounmap(mp->p_rx_desc_area);
959 dma_free_coherent(NULL, mp->rx_desc_area_size,
960 mp->p_rx_desc_area, mp->rx_desc_dma);
966 * This function is used when closing the network device.
967 * It updates the hardware,
968 * release all memory that holds buffers and descriptors and release the IRQ.
969 * Input : a pointer to the device structure
970 * Output : zero if success , nonzero if fails
973 /* Helper function for mv643xx_eth_stop */
975 static int mv643xx_eth_real_stop(struct net_device *dev)
977 struct mv643xx_private *mp = netdev_priv(dev);
978 unsigned int port_num = mp->port_num;
980 netif_carrier_off(dev);
981 netif_stop_queue(dev);
983 mv643xx_eth_free_tx_rings(dev);
984 mv643xx_eth_free_rx_rings(dev);
986 eth_port_reset(mp->port_num);
988 /* Disable ethernet port interrupts */
989 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
990 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
992 /* Mask RX buffer and TX end interrupt */
993 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), 0);
995 /* Mask phy and link status changes interrupts */
996 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num), 0);
1001 static int mv643xx_eth_stop(struct net_device *dev)
1003 struct mv643xx_private *mp = netdev_priv(dev);
1005 spin_lock_irq(&mp->lock);
1007 mv643xx_eth_real_stop(dev);
1009 free_irq(dev->irq, dev);
1010 spin_unlock_irq(&mp->lock);
1016 static void mv643xx_tx(struct net_device *dev)
1018 struct mv643xx_private *mp = netdev_priv(dev);
1019 struct pkt_info pkt_info;
1021 while (eth_tx_return_desc(mp, &pkt_info) == ETH_OK) {
1022 if (pkt_info.cmd_sts & ETH_TX_FIRST_DESC)
1023 dma_unmap_single(NULL, pkt_info.buf_ptr,
1027 dma_unmap_page(NULL, pkt_info.buf_ptr,
1031 if (pkt_info.return_info)
1032 dev_kfree_skb_irq(pkt_info.return_info);
1035 if (netif_queue_stopped(dev) &&
1036 mp->tx_ring_size > mp->tx_ring_skbs + MAX_DESCS_PER_SKB)
1037 netif_wake_queue(dev);
1043 * This function is used in case of NAPI
1045 static int mv643xx_poll(struct net_device *dev, int *budget)
1047 struct mv643xx_private *mp = netdev_priv(dev);
1048 int done = 1, orig_budget, work_done;
1049 unsigned int port_num = mp->port_num;
1050 unsigned long flags;
1052 #ifdef MV643XX_TX_FAST_REFILL
1053 if (++mp->tx_clean_threshold > 5) {
1054 spin_lock_irqsave(&mp->lock, flags);
1056 mp->tx_clean_threshold = 0;
1057 spin_unlock_irqrestore(&mp->lock, flags);
1061 if ((mv_read(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num)))
1062 != (u32) mp->rx_used_desc_q) {
1063 orig_budget = *budget;
1064 if (orig_budget > dev->quota)
1065 orig_budget = dev->quota;
1066 work_done = mv643xx_eth_receive_queue(dev, orig_budget);
1067 mp->rx_task.func(dev);
1068 *budget -= work_done;
1069 dev->quota -= work_done;
1070 if (work_done >= orig_budget)
1075 spin_lock_irqsave(&mp->lock, flags);
1076 __netif_rx_complete(dev);
1077 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
1078 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
1079 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
1080 INT_CAUSE_UNMASK_ALL);
1081 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
1082 INT_CAUSE_UNMASK_ALL_EXT);
1083 spin_unlock_irqrestore(&mp->lock, flags);
1086 return done ? 0 : 1;
1091 * mv643xx_eth_start_xmit
1093 * This function is queues a packet in the Tx descriptor for
1096 * Input : skb - a pointer to socket buffer
1097 * dev - a pointer to the required port
1099 * Output : zero upon success
1101 static int mv643xx_eth_start_xmit(struct sk_buff *skb, struct net_device *dev)
1103 struct mv643xx_private *mp = netdev_priv(dev);
1104 struct net_device_stats *stats = &mp->stats;
1105 ETH_FUNC_RET_STATUS status;
1106 unsigned long flags;
1107 struct pkt_info pkt_info;
1109 if (netif_queue_stopped(dev)) {
1111 "%s: Tried sending packet when interface is stopped\n",
1116 /* This is a hard error, log it. */
1117 if ((mp->tx_ring_size - mp->tx_ring_skbs) <=
1118 (skb_shinfo(skb)->nr_frags + 1)) {
1119 netif_stop_queue(dev);
1121 "%s: Bug in mv643xx_eth - Trying to transmit when"
1122 " queue full !\n", dev->name);
1126 /* Paranoid check - this shouldn't happen */
1128 stats->tx_dropped++;
1129 printk(KERN_ERR "mv64320_eth paranoid check failed\n");
1133 spin_lock_irqsave(&mp->lock, flags);
1135 /* Update packet info data structure -- DMA owned, first last */
1136 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1137 if (!skb_shinfo(skb)->nr_frags) {
1139 if (skb->ip_summed != CHECKSUM_HW) {
1140 /* Errata BTS #50, IHL must be 5 if no HW checksum */
1141 pkt_info.cmd_sts = ETH_TX_ENABLE_INTERRUPT |
1144 5 << ETH_TX_IHL_SHIFT;
1145 pkt_info.l4i_chk = 0;
1148 pkt_info.cmd_sts = ETH_TX_ENABLE_INTERRUPT |
1151 ETH_GEN_TCP_UDP_CHECKSUM |
1152 ETH_GEN_IP_V_4_CHECKSUM |
1153 skb->nh.iph->ihl << ETH_TX_IHL_SHIFT;
1154 /* CPU already calculated pseudo header checksum. */
1155 if (skb->nh.iph->protocol == IPPROTO_UDP) {
1156 pkt_info.cmd_sts |= ETH_UDP_FRAME;
1157 pkt_info.l4i_chk = skb->h.uh->check;
1158 } else if (skb->nh.iph->protocol == IPPROTO_TCP)
1159 pkt_info.l4i_chk = skb->h.th->check;
1162 "%s: chksum proto != TCP or UDP\n",
1164 spin_unlock_irqrestore(&mp->lock, flags);
1168 pkt_info.byte_cnt = skb->len;
1169 pkt_info.buf_ptr = dma_map_single(NULL, skb->data, skb->len,
1171 pkt_info.return_info = skb;
1172 status = eth_port_send(mp, &pkt_info);
1173 if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL))
1174 printk(KERN_ERR "%s: Error on transmitting packet\n",
1176 stats->tx_bytes += pkt_info.byte_cnt;
1180 /* Since hardware can't handle unaligned fragments smaller
1181 * than 9 bytes, if we find any, we linearize the skb
1182 * and start again. When I've seen it, it's always been
1183 * the first frag (probably near the end of the page),
1184 * but we check all frags to be safe.
1186 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1189 fragp = &skb_shinfo(skb)->frags[frag];
1190 if (fragp->size <= 8 && fragp->page_offset & 0x7) {
1191 skb_linearize(skb, GFP_ATOMIC);
1192 printk(KERN_DEBUG "%s: unaligned tiny fragment"
1193 "%d of %d, fixed\n",
1195 skb_shinfo(skb)->nr_frags);
1200 /* first frag which is skb header */
1201 pkt_info.byte_cnt = skb_headlen(skb);
1202 pkt_info.buf_ptr = dma_map_single(NULL, skb->data,
1205 pkt_info.l4i_chk = 0;
1206 pkt_info.return_info = 0;
1208 if (skb->ip_summed != CHECKSUM_HW)
1209 /* Errata BTS #50, IHL must be 5 if no HW checksum */
1210 pkt_info.cmd_sts = ETH_TX_FIRST_DESC |
1211 5 << ETH_TX_IHL_SHIFT;
1213 pkt_info.cmd_sts = ETH_TX_FIRST_DESC |
1214 ETH_GEN_TCP_UDP_CHECKSUM |
1215 ETH_GEN_IP_V_4_CHECKSUM |
1216 skb->nh.iph->ihl << ETH_TX_IHL_SHIFT;
1217 /* CPU already calculated pseudo header checksum. */
1218 if (skb->nh.iph->protocol == IPPROTO_UDP) {
1219 pkt_info.cmd_sts |= ETH_UDP_FRAME;
1220 pkt_info.l4i_chk = skb->h.uh->check;
1221 } else if (skb->nh.iph->protocol == IPPROTO_TCP)
1222 pkt_info.l4i_chk = skb->h.th->check;
1225 "%s: chksum proto != TCP or UDP\n",
1227 spin_unlock_irqrestore(&mp->lock, flags);
1232 status = eth_port_send(mp, &pkt_info);
1233 if (status != ETH_OK) {
1234 if ((status == ETH_ERROR))
1236 "%s: Error on transmitting packet\n",
1238 if (status == ETH_QUEUE_FULL)
1239 printk("Error on Queue Full \n");
1240 if (status == ETH_QUEUE_LAST_RESOURCE)
1241 printk("Tx resource error \n");
1243 stats->tx_bytes += pkt_info.byte_cnt;
1245 /* Check for the remaining frags */
1246 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1247 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
1248 pkt_info.l4i_chk = 0x0000;
1249 pkt_info.cmd_sts = 0x00000000;
1251 /* Last Frag enables interrupt and frees the skb */
1252 if (frag == (skb_shinfo(skb)->nr_frags - 1)) {
1253 pkt_info.cmd_sts |= ETH_TX_ENABLE_INTERRUPT |
1255 pkt_info.return_info = skb;
1257 pkt_info.return_info = 0;
1259 pkt_info.l4i_chk = 0;
1260 pkt_info.byte_cnt = this_frag->size;
1262 pkt_info.buf_ptr = dma_map_page(NULL, this_frag->page,
1263 this_frag->page_offset,
1267 status = eth_port_send(mp, &pkt_info);
1269 if (status != ETH_OK) {
1270 if ((status == ETH_ERROR))
1271 printk(KERN_ERR "%s: Error on "
1272 "transmitting packet\n",
1275 if (status == ETH_QUEUE_LAST_RESOURCE)
1276 printk("Tx resource error \n");
1278 if (status == ETH_QUEUE_FULL)
1279 printk("Queue is full \n");
1281 stats->tx_bytes += pkt_info.byte_cnt;
1285 pkt_info.cmd_sts = ETH_TX_ENABLE_INTERRUPT | ETH_TX_FIRST_DESC |
1287 pkt_info.l4i_chk = 0;
1288 pkt_info.byte_cnt = skb->len;
1289 pkt_info.buf_ptr = dma_map_single(NULL, skb->data, skb->len,
1291 pkt_info.return_info = skb;
1292 status = eth_port_send(mp, &pkt_info);
1293 if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL))
1294 printk(KERN_ERR "%s: Error on transmitting packet\n",
1296 stats->tx_bytes += pkt_info.byte_cnt;
1299 /* Check if TX queue can handle another skb. If not, then
1300 * signal higher layers to stop requesting TX
1302 if (mp->tx_ring_size <= (mp->tx_ring_skbs + MAX_DESCS_PER_SKB))
1304 * Stop getting skb's from upper layers.
1305 * Getting skb's from upper layers will be enabled again after
1306 * packets are released.
1308 netif_stop_queue(dev);
1310 /* Update statistics and start of transmittion time */
1311 stats->tx_packets++;
1312 dev->trans_start = jiffies;
1314 spin_unlock_irqrestore(&mp->lock, flags);
1316 return 0; /* success */
1320 * mv643xx_eth_get_stats
1322 * Returns a pointer to the interface statistics.
1324 * Input : dev - a pointer to the required interface
1326 * Output : a pointer to the interface's statistics
1329 static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1331 struct mv643xx_private *mp = netdev_priv(dev);
1336 #ifdef CONFIG_NET_POLL_CONTROLLER
1337 static inline void mv643xx_enable_irq(struct mv643xx_private *mp)
1339 int port_num = mp->port_num;
1340 unsigned long flags;
1342 spin_lock_irqsave(&mp->lock, flags);
1343 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
1344 INT_CAUSE_UNMASK_ALL);
1345 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
1346 INT_CAUSE_UNMASK_ALL_EXT);
1347 spin_unlock_irqrestore(&mp->lock, flags);
1350 static inline void mv643xx_disable_irq(struct mv643xx_private *mp)
1352 int port_num = mp->port_num;
1353 unsigned long flags;
1355 spin_lock_irqsave(&mp->lock, flags);
1356 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
1357 INT_CAUSE_MASK_ALL);
1358 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
1359 INT_CAUSE_MASK_ALL_EXT);
1360 spin_unlock_irqrestore(&mp->lock, flags);
1363 static void mv643xx_netpoll(struct net_device *netdev)
1365 struct mv643xx_private *mp = netdev_priv(netdev);
1367 mv643xx_disable_irq(mp);
1368 mv643xx_eth_int_handler(netdev->irq, netdev, NULL);
1369 mv643xx_enable_irq(mp);
1376 * First function called after registering the network device.
1377 * It's purpose is to initialize the device as an ethernet device,
1378 * fill the ethernet device structure with pointers * to functions,
1379 * and set the MAC address of the interface
1381 * Input : struct device *
1382 * Output : -ENOMEM if failed , 0 if success
1384 static int mv643xx_eth_probe(struct platform_device *pdev)
1386 struct mv643xx_eth_platform_data *pd;
1387 int port_num = pdev->id;
1388 struct mv643xx_private *mp;
1389 struct net_device *dev;
1391 struct resource *res;
1394 dev = alloc_etherdev(sizeof(struct mv643xx_private));
1398 platform_set_drvdata(pdev, dev);
1400 mp = netdev_priv(dev);
1402 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1404 dev->irq = res->start;
1406 mp->port_num = port_num;
1408 dev->open = mv643xx_eth_open;
1409 dev->stop = mv643xx_eth_stop;
1410 dev->hard_start_xmit = mv643xx_eth_start_xmit;
1411 dev->get_stats = mv643xx_eth_get_stats;
1412 dev->set_mac_address = mv643xx_eth_set_mac_address;
1413 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
1415 /* No need to Tx Timeout */
1416 dev->tx_timeout = mv643xx_eth_tx_timeout;
1418 dev->poll = mv643xx_poll;
1422 #ifdef CONFIG_NET_POLL_CONTROLLER
1423 dev->poll_controller = mv643xx_netpoll;
1426 dev->watchdog_timeo = 2 * HZ;
1427 dev->tx_queue_len = mp->tx_ring_size;
1429 dev->change_mtu = mv643xx_eth_change_mtu;
1430 SET_ETHTOOL_OPS(dev, &mv643xx_ethtool_ops);
1432 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1433 #ifdef MAX_SKB_FRAGS
1435 * Zero copy can only work if we use Discovery II memory. Else, we will
1436 * have to map the buffers to ISA memory which is only 16 MB
1438 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_HW_CSUM;
1442 /* Configure the timeout task */
1443 INIT_WORK(&mp->tx_timeout_task,
1444 (void (*)(void *))mv643xx_eth_tx_timeout_task, dev);
1446 spin_lock_init(&mp->lock);
1448 /* set default config values */
1449 eth_port_uc_addr_get(dev, dev->dev_addr);
1450 mp->port_config = MV643XX_ETH_PORT_CONFIG_DEFAULT_VALUE;
1451 mp->port_config_extend = MV643XX_ETH_PORT_CONFIG_EXTEND_DEFAULT_VALUE;
1452 mp->port_sdma_config = MV643XX_ETH_PORT_SDMA_CONFIG_DEFAULT_VALUE;
1453 mp->port_serial_control = MV643XX_ETH_PORT_SERIAL_CONTROL_DEFAULT_VALUE;
1454 mp->rx_ring_size = MV643XX_ETH_PORT_DEFAULT_RECEIVE_QUEUE_SIZE;
1455 mp->tx_ring_size = MV643XX_ETH_PORT_DEFAULT_TRANSMIT_QUEUE_SIZE;
1457 pd = pdev->dev.platform_data;
1459 if (pd->mac_addr != NULL)
1460 memcpy(dev->dev_addr, pd->mac_addr, 6);
1462 if (pd->phy_addr || pd->force_phy_addr)
1463 ethernet_phy_set(port_num, pd->phy_addr);
1465 if (pd->port_config || pd->force_port_config)
1466 mp->port_config = pd->port_config;
1468 if (pd->port_config_extend || pd->force_port_config_extend)
1469 mp->port_config_extend = pd->port_config_extend;
1471 if (pd->port_sdma_config || pd->force_port_sdma_config)
1472 mp->port_sdma_config = pd->port_sdma_config;
1474 if (pd->port_serial_control || pd->force_port_serial_control)
1475 mp->port_serial_control = pd->port_serial_control;
1477 if (pd->rx_queue_size)
1478 mp->rx_ring_size = pd->rx_queue_size;
1480 if (pd->tx_queue_size)
1481 mp->tx_ring_size = pd->tx_queue_size;
1483 if (pd->tx_sram_size) {
1484 mp->tx_sram_size = pd->tx_sram_size;
1485 mp->tx_sram_addr = pd->tx_sram_addr;
1488 if (pd->rx_sram_size) {
1489 mp->rx_sram_size = pd->rx_sram_size;
1490 mp->rx_sram_addr = pd->rx_sram_addr;
1494 err = ethernet_phy_detect(port_num);
1496 pr_debug("MV643xx ethernet port %d: "
1497 "No PHY detected at addr %d\n",
1498 port_num, ethernet_phy_get(port_num));
1502 err = register_netdev(dev);
1508 "%s: port %d with MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
1509 dev->name, port_num, p[0], p[1], p[2], p[3], p[4], p[5]);
1511 if (dev->features & NETIF_F_SG)
1512 printk(KERN_NOTICE "%s: Scatter Gather Enabled\n", dev->name);
1514 if (dev->features & NETIF_F_IP_CSUM)
1515 printk(KERN_NOTICE "%s: TX TCP/IP Checksumming Supported\n",
1518 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1519 printk(KERN_NOTICE "%s: RX TCP/UDP Checksum Offload ON \n", dev->name);
1523 printk(KERN_NOTICE "%s: TX and RX Interrupt Coalescing ON \n",
1528 printk(KERN_NOTICE "%s: RX NAPI Enabled \n", dev->name);
1531 if (mp->tx_sram_size > 0)
1532 printk(KERN_NOTICE "%s: Using SRAM\n", dev->name);
1542 static int mv643xx_eth_remove(struct platform_device *pdev)
1544 struct net_device *dev = platform_get_drvdata(pdev);
1546 unregister_netdev(dev);
1547 flush_scheduled_work();
1550 platform_set_drvdata(pdev, NULL);
1554 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
1556 struct resource *res;
1558 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
1560 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1564 mv643xx_eth_shared_base = ioremap(res->start,
1565 MV643XX_ETH_SHARED_REGS_SIZE);
1566 if (mv643xx_eth_shared_base == NULL)
1573 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
1575 iounmap(mv643xx_eth_shared_base);
1576 mv643xx_eth_shared_base = NULL;
1581 static struct platform_driver mv643xx_eth_driver = {
1582 .probe = mv643xx_eth_probe,
1583 .remove = mv643xx_eth_remove,
1585 .name = MV643XX_ETH_NAME,
1589 static struct platform_driver mv643xx_eth_shared_driver = {
1590 .probe = mv643xx_eth_shared_probe,
1591 .remove = mv643xx_eth_shared_remove,
1593 .name = MV643XX_ETH_SHARED_NAME,
1598 * mv643xx_init_module
1600 * Registers the network drivers into the Linux kernel
1606 static int __init mv643xx_init_module(void)
1610 rc = platform_driver_register(&mv643xx_eth_shared_driver);
1612 rc = platform_driver_register(&mv643xx_eth_driver);
1614 platform_driver_unregister(&mv643xx_eth_shared_driver);
1620 * mv643xx_cleanup_module
1622 * Registers the network drivers into the Linux kernel
1628 static void __exit mv643xx_cleanup_module(void)
1630 platform_driver_unregister(&mv643xx_eth_driver);
1631 platform_driver_unregister(&mv643xx_eth_shared_driver);
1634 module_init(mv643xx_init_module);
1635 module_exit(mv643xx_cleanup_module);
1637 MODULE_LICENSE("GPL");
1638 MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani"
1639 " and Dale Farnsworth");
1640 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
1643 * The second part is the low level driver of the gigE ethernet ports.
1647 * Marvell's Gigabit Ethernet controller low level driver
1650 * This file introduce low level API to Marvell's Gigabit Ethernet
1651 * controller. This Gigabit Ethernet Controller driver API controls
1652 * 1) Operations (i.e. port init, start, reset etc').
1653 * 2) Data flow (i.e. port send, receive etc').
1654 * Each Gigabit Ethernet port is controlled via
1655 * struct mv643xx_private.
1656 * This struct includes user configuration information as well as
1657 * driver internal data needed for its operations.
1659 * Supported Features:
1660 * - This low level driver is OS independent. Allocating memory for
1661 * the descriptor rings and buffers are not within the scope of
1663 * - The user is free from Rx/Tx queue managing.
1664 * - This low level driver introduce functionality API that enable
1665 * the to operate Marvell's Gigabit Ethernet Controller in a
1667 * - Simple Gigabit Ethernet port operation API.
1668 * - Simple Gigabit Ethernet port data flow API.
1669 * - Data flow and operation API support per queue functionality.
1670 * - Support cached descriptors for better performance.
1671 * - Enable access to all four DRAM banks and internal SRAM memory
1673 * - PHY access and control API.
1674 * - Port control register configuration API.
1675 * - Full control over Unicast and Multicast MAC configurations.
1679 * Initialization phase
1680 * This phase complete the initialization of the the
1681 * mv643xx_private struct.
1682 * User information regarding port configuration has to be set
1683 * prior to calling the port initialization routine.
1685 * In this phase any port Tx/Rx activity is halted, MIB counters
1686 * are cleared, PHY address is set according to user parameter and
1687 * access to DRAM and internal SRAM memory spaces.
1689 * Driver ring initialization
1690 * Allocating memory for the descriptor rings and buffers is not
1691 * within the scope of this driver. Thus, the user is required to
1692 * allocate memory for the descriptors ring and buffers. Those
1693 * memory parameters are used by the Rx and Tx ring initialization
1694 * routines in order to curve the descriptor linked list in a form
1696 * Note: Pay special attention to alignment issues when using
1697 * cached descriptors/buffers. In this phase the driver store
1698 * information in the mv643xx_private struct regarding each queue
1702 * This phase prepares the Ethernet port for Rx and Tx activity.
1703 * It uses the information stored in the mv643xx_private struct to
1704 * initialize the various port registers.
1707 * All packet references to/from the driver are done using
1709 * This struct is a unified struct used with Rx and Tx operations.
1710 * This way the user is not required to be familiar with neither
1711 * Tx nor Rx descriptors structures.
1712 * The driver's descriptors rings are management by indexes.
1713 * Those indexes controls the ring resources and used to indicate
1714 * a SW resource error:
1716 * This index points to the current available resource for use. For
1717 * example in Rx process this index will point to the descriptor
1718 * that will be passed to the user upon calling the receive
1719 * routine. In Tx process, this index will point to the descriptor
1720 * that will be assigned with the user packet info and transmitted.
1722 * This index points to the descriptor that need to restore its
1723 * resources. For example in Rx process, using the Rx buffer return
1724 * API will attach the buffer returned in packet info to the
1725 * descriptor pointed by 'used'. In Tx process, using the Tx
1726 * descriptor return will merely return the user packet info with
1727 * the command status of the transmitted buffer pointed by the
1728 * 'used' index. Nevertheless, it is essential to use this routine
1729 * to update the 'used' index.
1731 * This index supports Tx Scatter-Gather. It points to the first
1732 * descriptor of a packet assembled of multiple buffers. For
1733 * example when in middle of Such packet we have a Tx resource
1734 * error the 'curr' index get the value of 'first' to indicate
1735 * that the ring returned to its state before trying to transmit
1738 * Receive operation:
1739 * The eth_port_receive API set the packet information struct,
1740 * passed by the caller, with received information from the
1741 * 'current' SDMA descriptor.
1742 * It is the user responsibility to return this resource back
1743 * to the Rx descriptor ring to enable the reuse of this source.
1744 * Return Rx resource is done using the eth_rx_return_buff API.
1746 * Transmit operation:
1747 * The eth_port_send API supports Scatter-Gather which enables to
1748 * send a packet spanned over multiple buffers. This means that
1749 * for each packet info structure given by the user and put into
1750 * the Tx descriptors ring, will be transmitted only if the 'LAST'
1751 * bit will be set in the packet info command status field. This
1752 * API also consider restriction regarding buffer alignments and
1754 * The user must return a Tx resource after ensuring the buffer
1755 * has been transmitted to enable the Tx ring indexes to update.
1758 * This device is on-board. No jumper diagram is necessary.
1760 * EXTERNAL INTERFACE
1762 * Prior to calling the initialization routine eth_port_init() the user
1763 * must set the following fields under mv643xx_private struct:
1764 * port_num User Ethernet port number.
1765 * port_mac_addr[6] User defined port MAC address.
1766 * port_config User port configuration value.
1767 * port_config_extend User port config extend value.
1768 * port_sdma_config User port SDMA config value.
1769 * port_serial_control User port serial control value.
1771 * This driver data flow is done using the struct pkt_info which
1772 * is a unified struct for Rx and Tx operations:
1774 * byte_cnt Tx/Rx descriptor buffer byte count.
1775 * l4i_chk CPU provided TCP Checksum. For Tx operation
1777 * cmd_sts Tx/Rx descriptor command status.
1778 * buf_ptr Tx/Rx descriptor buffer pointer.
1779 * return_info Tx/Rx user resource return information.
1783 /* SDMA command macros */
1784 #define ETH_ENABLE_TX_QUEUE(eth_port) \
1785 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), 1)
1790 static int ethernet_phy_get(unsigned int eth_port_num);
1791 static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr);
1793 /* Ethernet Port routines */
1794 static int eth_port_uc_addr(unsigned int eth_port_num, unsigned char uc_nibble,
1798 * eth_port_init - Initialize the Ethernet port driver
1801 * This function prepares the ethernet port to start its activity:
1802 * 1) Completes the ethernet port driver struct initialization toward port
1804 * 2) Resets the device to a quiescent state in case of warm reboot.
1805 * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
1806 * 4) Clean MAC tables. The reset status of those tables is unknown.
1807 * 5) Set PHY address.
1808 * Note: Call this routine prior to eth_port_start routine and after
1809 * setting user values in the user fields of Ethernet port control
1813 * struct mv643xx_private *mp Ethernet port control struct
1821 static void eth_port_init(struct mv643xx_private *mp)
1823 mp->port_rx_queue_command = 0;
1824 mp->port_tx_queue_command = 0;
1826 mp->rx_resource_err = 0;
1827 mp->tx_resource_err = 0;
1829 eth_port_reset(mp->port_num);
1831 eth_port_init_mac_tables(mp->port_num);
1833 ethernet_phy_reset(mp->port_num);
1837 * eth_port_start - Start the Ethernet port activity.
1840 * This routine prepares the Ethernet port for Rx and Tx activity:
1841 * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
1842 * has been initialized a descriptor's ring (using
1843 * ether_init_tx_desc_ring for Tx and ether_init_rx_desc_ring for Rx)
1844 * 2. Initialize and enable the Ethernet configuration port by writing to
1845 * the port's configuration and command registers.
1846 * 3. Initialize and enable the SDMA by writing to the SDMA's
1847 * configuration and command registers. After completing these steps,
1848 * the ethernet port SDMA can starts to perform Rx and Tx activities.
1850 * Note: Each Rx and Tx queue descriptor's list must be initialized prior
1851 * to calling this function (use ether_init_tx_desc_ring for Tx queues
1852 * and ether_init_rx_desc_ring for Rx queues).
1855 * struct mv643xx_private *mp Ethernet port control struct
1858 * Ethernet port is ready to receive and transmit.
1863 static void eth_port_start(struct mv643xx_private *mp)
1865 unsigned int port_num = mp->port_num;
1866 int tx_curr_desc, rx_curr_desc;
1868 /* Assignment of Tx CTRP of given queue */
1869 tx_curr_desc = mp->tx_curr_desc_q;
1870 mv_write(MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port_num),
1871 (u32)((struct eth_tx_desc *)mp->tx_desc_dma + tx_curr_desc));
1873 /* Assignment of Rx CRDP of given queue */
1874 rx_curr_desc = mp->rx_curr_desc_q;
1875 mv_write(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num),
1876 (u32)((struct eth_rx_desc *)mp->rx_desc_dma + rx_curr_desc));
1878 /* Add the assigned Ethernet address to the port's address table */
1879 eth_port_uc_addr_set(port_num, mp->port_mac_addr);
1881 /* Assign port configuration and command. */
1882 mv_write(MV643XX_ETH_PORT_CONFIG_REG(port_num), mp->port_config);
1884 mv_write(MV643XX_ETH_PORT_CONFIG_EXTEND_REG(port_num),
1885 mp->port_config_extend);
1888 /* Increase the Rx side buffer size if supporting GigE */
1889 if (mp->port_serial_control & MV643XX_ETH_SET_GMII_SPEED_TO_1000)
1890 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
1891 (mp->port_serial_control & 0xfff1ffff) | (0x5 << 17));
1893 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
1894 mp->port_serial_control);
1896 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
1897 mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num)) |
1898 MV643XX_ETH_SERIAL_PORT_ENABLE);
1900 /* Assign port SDMA configuration */
1901 mv_write(MV643XX_ETH_SDMA_CONFIG_REG(port_num),
1902 mp->port_sdma_config);
1904 /* Enable port Rx. */
1905 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num),
1906 mp->port_rx_queue_command);
1908 /* Disable port bandwidth limits by clearing MTU register */
1909 mv_write(MV643XX_ETH_MAXIMUM_TRANSMIT_UNIT(port_num), 0);
1913 * eth_port_uc_addr_set - This function Set the port Unicast address.
1916 * This function Set the port Ethernet MAC address.
1919 * unsigned int eth_port_num Port number.
1920 * char * p_addr Address to be set
1923 * Set MAC address low and high registers. also calls eth_port_uc_addr()
1924 * To set the unicast table with the proper information.
1930 static void eth_port_uc_addr_set(unsigned int eth_port_num,
1931 unsigned char *p_addr)
1936 mac_l = (p_addr[4] << 8) | (p_addr[5]);
1937 mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
1940 mv_write(MV643XX_ETH_MAC_ADDR_LOW(eth_port_num), mac_l);
1941 mv_write(MV643XX_ETH_MAC_ADDR_HIGH(eth_port_num), mac_h);
1943 /* Accept frames of this address */
1944 eth_port_uc_addr(eth_port_num, p_addr[5], ACCEPT_MAC_ADDR);
1950 * eth_port_uc_addr_get - This function retrieves the port Unicast address
1951 * (MAC address) from the ethernet hw registers.
1954 * This function retrieves the port Ethernet MAC address.
1957 * unsigned int eth_port_num Port number.
1958 * char *MacAddr pointer where the MAC address is stored
1961 * Copy the MAC address to the location pointed to by MacAddr
1967 static void eth_port_uc_addr_get(struct net_device *dev, unsigned char *p_addr)
1969 struct mv643xx_private *mp = netdev_priv(dev);
1973 mac_h = mv_read(MV643XX_ETH_MAC_ADDR_HIGH(mp->port_num));
1974 mac_l = mv_read(MV643XX_ETH_MAC_ADDR_LOW(mp->port_num));
1976 p_addr[0] = (mac_h >> 24) & 0xff;
1977 p_addr[1] = (mac_h >> 16) & 0xff;
1978 p_addr[2] = (mac_h >> 8) & 0xff;
1979 p_addr[3] = mac_h & 0xff;
1980 p_addr[4] = (mac_l >> 8) & 0xff;
1981 p_addr[5] = mac_l & 0xff;
1985 * eth_port_uc_addr - This function Set the port unicast address table
1988 * This function locates the proper entry in the Unicast table for the
1989 * specified MAC nibble and sets its properties according to function
1993 * unsigned int eth_port_num Port number.
1994 * unsigned char uc_nibble Unicast MAC Address last nibble.
1995 * int option 0 = Add, 1 = remove address.
1998 * This function add/removes MAC addresses from the port unicast address
2002 * true is output succeeded.
2003 * false if option parameter is invalid.
2006 static int eth_port_uc_addr(unsigned int eth_port_num, unsigned char uc_nibble,
2009 unsigned int unicast_reg;
2010 unsigned int tbl_offset;
2011 unsigned int reg_offset;
2013 /* Locate the Unicast table entry */
2014 uc_nibble = (0xf & uc_nibble);
2015 tbl_offset = (uc_nibble / 4) * 4; /* Register offset from unicast table base */
2016 reg_offset = uc_nibble % 4; /* Entry offset within the above register */
2019 case REJECT_MAC_ADDR:
2020 /* Clear accepts frame bit at given unicast DA table entry */
2021 unicast_reg = mv_read((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2022 (eth_port_num) + tbl_offset));
2024 unicast_reg &= (0x0E << (8 * reg_offset));
2026 mv_write((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2027 (eth_port_num) + tbl_offset), unicast_reg);
2030 case ACCEPT_MAC_ADDR:
2031 /* Set accepts frame bit at unicast DA filter table entry */
2033 mv_read((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2034 (eth_port_num) + tbl_offset));
2036 unicast_reg |= (0x01 << (8 * reg_offset));
2038 mv_write((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2039 (eth_port_num) + tbl_offset), unicast_reg);
2051 * The entries in each table are indexed by a hash of a packet's MAC
2052 * address. One bit in each entry determines whether the packet is
2053 * accepted. There are 4 entries (each 8 bits wide) in each register
2054 * of the table. The bits in each entry are defined as follows:
2055 * 0 Accept=1, Drop=0
2056 * 3-1 Queue (ETH_Q0=0)
2059 static void eth_port_set_filter_table_entry(int table, unsigned char entry)
2061 unsigned int table_reg;
2062 unsigned int tbl_offset;
2063 unsigned int reg_offset;
2065 tbl_offset = (entry / 4) * 4; /* Register offset of DA table entry */
2066 reg_offset = entry % 4; /* Entry offset within the register */
2068 /* Set "accepts frame bit" at specified table entry */
2069 table_reg = mv_read(table + tbl_offset);
2070 table_reg |= 0x01 << (8 * reg_offset);
2071 mv_write(table + tbl_offset, table_reg);
2075 * eth_port_mc_addr - Multicast address settings.
2077 * The MV device supports multicast using two tables:
2078 * 1) Special Multicast Table for MAC addresses of the form
2079 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_FF).
2080 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
2081 * Table entries in the DA-Filter table.
2082 * 2) Other Multicast Table for multicast of another type. A CRC-8bit
2083 * is used as an index to the Other Multicast Table entries in the
2084 * DA-Filter table. This function calculates the CRC-8bit value.
2085 * In either case, eth_port_set_filter_table_entry() is then called
2086 * to set to set the actual table entry.
2088 static void eth_port_mc_addr(unsigned int eth_port_num, unsigned char *p_addr)
2092 unsigned char crc_result = 0;
2098 if ((p_addr[0] == 0x01) && (p_addr[1] == 0x00) &&
2099 (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) {
2100 table = MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2102 eth_port_set_filter_table_entry(table, p_addr[5]);
2106 /* Calculate CRC-8 out of the given address */
2107 mac_h = (p_addr[0] << 8) | (p_addr[1]);
2108 mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) |
2109 (p_addr[4] << 8) | (p_addr[5] << 0);
2111 for (i = 0; i < 32; i++)
2112 mac_array[i] = (mac_l >> i) & 0x1;
2113 for (i = 32; i < 48; i++)
2114 mac_array[i] = (mac_h >> (i - 32)) & 0x1;
2116 crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ mac_array[39] ^
2117 mac_array[35] ^ mac_array[34] ^ mac_array[31] ^ mac_array[30] ^
2118 mac_array[28] ^ mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
2119 mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ mac_array[12] ^
2120 mac_array[8] ^ mac_array[7] ^ mac_array[6] ^ mac_array[0];
2122 crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
2123 mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ mac_array[34] ^
2124 mac_array[32] ^ mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
2125 mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ mac_array[21] ^
2126 mac_array[20] ^ mac_array[18] ^ mac_array[17] ^ mac_array[16] ^
2127 mac_array[15] ^ mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
2128 mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ mac_array[0];
2130 crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ mac_array[43] ^
2131 mac_array[42] ^ mac_array[39] ^ mac_array[37] ^ mac_array[34] ^
2132 mac_array[33] ^ mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
2133 mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ mac_array[15] ^
2134 mac_array[13] ^ mac_array[12] ^ mac_array[10] ^ mac_array[8] ^
2135 mac_array[6] ^ mac_array[2] ^ mac_array[1] ^ mac_array[0];
2137 crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
2138 mac_array[40] ^ mac_array[38] ^ mac_array[35] ^ mac_array[34] ^
2139 mac_array[30] ^ mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
2140 mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
2141 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[7] ^
2142 mac_array[3] ^ mac_array[2] ^ mac_array[1];
2144 crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[41] ^
2145 mac_array[39] ^ mac_array[36] ^ mac_array[35] ^ mac_array[31] ^
2146 mac_array[30] ^ mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
2147 mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ mac_array[14] ^
2148 mac_array[12] ^ mac_array[10] ^ mac_array[8] ^ mac_array[4] ^
2149 mac_array[3] ^ mac_array[2];
2151 crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ mac_array[42] ^
2152 mac_array[40] ^ mac_array[37] ^ mac_array[36] ^ mac_array[32] ^
2153 mac_array[31] ^ mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
2154 mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ mac_array[15] ^
2155 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[5] ^
2156 mac_array[4] ^ mac_array[3];
2158 crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ mac_array[41] ^
2159 mac_array[38] ^ mac_array[37] ^ mac_array[33] ^ mac_array[32] ^
2160 mac_array[29] ^ mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
2161 mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ mac_array[14] ^
2162 mac_array[12] ^ mac_array[10] ^ mac_array[6] ^ mac_array[5] ^
2165 crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ mac_array[39] ^
2166 mac_array[38] ^ mac_array[34] ^ mac_array[33] ^ mac_array[30] ^
2167 mac_array[29] ^ mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
2168 mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ mac_array[13] ^
2169 mac_array[11] ^ mac_array[7] ^ mac_array[6] ^ mac_array[5];
2171 for (i = 0; i < 8; i++)
2172 crc_result = crc_result | (crc[i] << i);
2174 table = MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num);
2175 eth_port_set_filter_table_entry(table, crc_result);
2179 * Set the entire multicast list based on dev->mc_list.
2181 static void eth_port_set_multicast_list(struct net_device *dev)
2184 struct dev_mc_list *mc_list;
2187 struct mv643xx_private *mp = netdev_priv(dev);
2188 unsigned int eth_port_num = mp->port_num;
2190 /* If the device is in promiscuous mode or in all multicast mode,
2191 * we will fully populate both multicast tables with accept.
2192 * This is guaranteed to yield a match on all multicast addresses...
2194 if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) {
2195 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2196 /* Set all entries in DA filter special multicast
2198 * Set for ETH_Q0 for now
2200 * 0 Accept=1, Drop=0
2201 * 3-1 Queue ETH_Q0=0
2204 mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101);
2206 /* Set all entries in DA filter other multicast
2208 * Set for ETH_Q0 for now
2210 * 0 Accept=1, Drop=0
2211 * 3-1 Queue ETH_Q0=0
2214 mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101);
2219 /* We will clear out multicast tables every time we get the list.
2220 * Then add the entire new list...
2222 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2223 /* Clear DA filter special multicast table (Ex_dFSMT) */
2224 mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2225 (eth_port_num) + table_index, 0);
2227 /* Clear DA filter other multicast table (Ex_dFOMT) */
2228 mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE
2229 (eth_port_num) + table_index, 0);
2232 /* Get pointer to net_device multicast list and add each one... */
2233 for (i = 0, mc_list = dev->mc_list;
2234 (i < 256) && (mc_list != NULL) && (i < dev->mc_count);
2235 i++, mc_list = mc_list->next)
2236 if (mc_list->dmi_addrlen == 6)
2237 eth_port_mc_addr(eth_port_num, mc_list->dmi_addr);
2241 * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
2244 * Go through all the DA filter tables (Unicast, Special Multicast &
2245 * Other Multicast) and set each entry to 0.
2248 * unsigned int eth_port_num Ethernet Port number.
2251 * Multicast and Unicast packets are rejected.
2256 static void eth_port_init_mac_tables(unsigned int eth_port_num)
2260 /* Clear DA filter unicast table (Ex_dFUT) */
2261 for (table_index = 0; table_index <= 0xC; table_index += 4)
2262 mv_write((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2263 (eth_port_num) + table_index), 0);
2265 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2266 /* Clear DA filter special multicast table (Ex_dFSMT) */
2267 mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2268 (eth_port_num) + table_index, 0);
2269 /* Clear DA filter other multicast table (Ex_dFOMT) */
2270 mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE
2271 (eth_port_num) + table_index, 0);
2276 * eth_clear_mib_counters - Clear all MIB counters
2279 * This function clears all MIB counters of a specific ethernet port.
2280 * A read from the MIB counter will reset the counter.
2283 * unsigned int eth_port_num Ethernet Port number.
2286 * After reading all MIB counters, the counters resets.
2289 * MIB counter value.
2292 static void eth_clear_mib_counters(unsigned int eth_port_num)
2296 /* Perform dummy reads from MIB counters */
2297 for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
2299 mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(eth_port_num) + i);
2302 static inline u32 read_mib(struct mv643xx_private *mp, int offset)
2304 return mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(mp->port_num) + offset);
2307 static void eth_update_mib_counters(struct mv643xx_private *mp)
2309 struct mv643xx_mib_counters *p = &mp->mib_counters;
2312 p->good_octets_received +=
2313 read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
2314 p->good_octets_received +=
2315 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32;
2317 for (offset = ETH_MIB_BAD_OCTETS_RECEIVED;
2318 offset <= ETH_MIB_FRAMES_1024_TO_MAX_OCTETS;
2320 *(u32 *)((char *)p + offset) = read_mib(mp, offset);
2322 p->good_octets_sent += read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_LOW);
2323 p->good_octets_sent +=
2324 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_HIGH) << 32;
2326 for (offset = ETH_MIB_GOOD_FRAMES_SENT;
2327 offset <= ETH_MIB_LATE_COLLISION;
2329 *(u32 *)((char *)p + offset) = read_mib(mp, offset);
2333 * ethernet_phy_detect - Detect whether a phy is present
2336 * This function tests whether there is a PHY present on
2337 * the specified port.
2340 * unsigned int eth_port_num Ethernet Port number.
2347 * -ENODEV on failure
2350 static int ethernet_phy_detect(unsigned int port_num)
2352 unsigned int phy_reg_data0;
2355 eth_port_read_smi_reg(port_num, 0, &phy_reg_data0);
2356 auto_neg = phy_reg_data0 & 0x1000;
2357 phy_reg_data0 ^= 0x1000; /* invert auto_neg */
2358 eth_port_write_smi_reg(port_num, 0, phy_reg_data0);
2360 eth_port_read_smi_reg(port_num, 0, &phy_reg_data0);
2361 if ((phy_reg_data0 & 0x1000) == auto_neg)
2362 return -ENODEV; /* change didn't take */
2364 phy_reg_data0 ^= 0x1000;
2365 eth_port_write_smi_reg(port_num, 0, phy_reg_data0);
2370 * ethernet_phy_get - Get the ethernet port PHY address.
2373 * This routine returns the given ethernet port PHY address.
2376 * unsigned int eth_port_num Ethernet Port number.
2385 static int ethernet_phy_get(unsigned int eth_port_num)
2387 unsigned int reg_data;
2389 reg_data = mv_read(MV643XX_ETH_PHY_ADDR_REG);
2391 return ((reg_data >> (5 * eth_port_num)) & 0x1f);
2395 * ethernet_phy_set - Set the ethernet port PHY address.
2398 * This routine sets the given ethernet port PHY address.
2401 * unsigned int eth_port_num Ethernet Port number.
2402 * int phy_addr PHY address.
2411 static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr)
2414 int addr_shift = 5 * eth_port_num;
2416 reg_data = mv_read(MV643XX_ETH_PHY_ADDR_REG);
2417 reg_data &= ~(0x1f << addr_shift);
2418 reg_data |= (phy_addr & 0x1f) << addr_shift;
2419 mv_write(MV643XX_ETH_PHY_ADDR_REG, reg_data);
2423 * ethernet_phy_reset - Reset Ethernet port PHY.
2426 * This routine utilizes the SMI interface to reset the ethernet port PHY.
2429 * unsigned int eth_port_num Ethernet Port number.
2438 static void ethernet_phy_reset(unsigned int eth_port_num)
2440 unsigned int phy_reg_data;
2443 eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data);
2444 phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
2445 eth_port_write_smi_reg(eth_port_num, 0, phy_reg_data);
2449 * eth_port_reset - Reset Ethernet port
2452 * This routine resets the chip by aborting any SDMA engine activity and
2453 * clearing the MIB counters. The Receiver and the Transmit unit are in
2454 * idle state after this command is performed and the port is disabled.
2457 * unsigned int eth_port_num Ethernet Port number.
2460 * Channel activity is halted.
2466 static void eth_port_reset(unsigned int port_num)
2468 unsigned int reg_data;
2470 /* Stop Tx port activity. Check port Tx activity. */
2471 reg_data = mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num));
2473 if (reg_data & 0xFF) {
2474 /* Issue stop command for active channels only */
2475 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num),
2478 /* Wait for all Tx activity to terminate. */
2479 /* Check port cause register that all Tx queues are stopped */
2480 while (mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num))
2485 /* Stop Rx port activity. Check port Rx activity. */
2486 reg_data = mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num));
2488 if (reg_data & 0xFF) {
2489 /* Issue stop command for active channels only */
2490 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num),
2493 /* Wait for all Rx activity to terminate. */
2494 /* Check port cause register that all Rx queues are stopped */
2495 while (mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num))
2500 /* Clear all MIB counters */
2501 eth_clear_mib_counters(port_num);
2503 /* Reset the Enable bit in the Configuration Register */
2504 reg_data = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num));
2505 reg_data &= ~MV643XX_ETH_SERIAL_PORT_ENABLE;
2506 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), reg_data);
2510 static int eth_port_autoneg_supported(unsigned int eth_port_num)
2512 unsigned int phy_reg_data0;
2514 eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data0);
2516 return phy_reg_data0 & 0x1000;
2519 static int eth_port_link_is_up(unsigned int eth_port_num)
2521 unsigned int phy_reg_data1;
2523 eth_port_read_smi_reg(eth_port_num, 1, &phy_reg_data1);
2525 if (eth_port_autoneg_supported(eth_port_num)) {
2526 if (phy_reg_data1 & 0x20) /* auto-neg complete */
2528 } else if (phy_reg_data1 & 0x4) /* link up */
2535 * eth_port_read_smi_reg - Read PHY registers
2538 * This routine utilize the SMI interface to interact with the PHY in
2539 * order to perform PHY register read.
2542 * unsigned int port_num Ethernet Port number.
2543 * unsigned int phy_reg PHY register address offset.
2544 * unsigned int *value Register value buffer.
2547 * Write the value of a specified PHY register into given buffer.
2550 * false if the PHY is busy or read data is not in valid state.
2554 static void eth_port_read_smi_reg(unsigned int port_num,
2555 unsigned int phy_reg, unsigned int *value)
2557 int phy_addr = ethernet_phy_get(port_num);
2558 unsigned long flags;
2561 /* the SMI register is a shared resource */
2562 spin_lock_irqsave(&mv643xx_eth_phy_lock, flags);
2564 /* wait for the SMI register to become available */
2565 for (i = 0; mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_BUSY; i++) {
2566 if (i == PHY_WAIT_ITERATIONS) {
2567 printk("mv643xx PHY busy timeout, port %d\n", port_num);
2570 udelay(PHY_WAIT_MICRO_SECONDS);
2573 mv_write(MV643XX_ETH_SMI_REG,
2574 (phy_addr << 16) | (phy_reg << 21) | ETH_SMI_OPCODE_READ);
2576 /* now wait for the data to be valid */
2577 for (i = 0; !(mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_READ_VALID); i++) {
2578 if (i == PHY_WAIT_ITERATIONS) {
2579 printk("mv643xx PHY read timeout, port %d\n", port_num);
2582 udelay(PHY_WAIT_MICRO_SECONDS);
2585 *value = mv_read(MV643XX_ETH_SMI_REG) & 0xffff;
2587 spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags);
2591 * eth_port_write_smi_reg - Write to PHY registers
2594 * This routine utilize the SMI interface to interact with the PHY in
2595 * order to perform writes to PHY registers.
2598 * unsigned int eth_port_num Ethernet Port number.
2599 * unsigned int phy_reg PHY register address offset.
2600 * unsigned int value Register value.
2603 * Write the given value to the specified PHY register.
2606 * false if the PHY is busy.
2610 static void eth_port_write_smi_reg(unsigned int eth_port_num,
2611 unsigned int phy_reg, unsigned int value)
2615 unsigned long flags;
2617 phy_addr = ethernet_phy_get(eth_port_num);
2619 /* the SMI register is a shared resource */
2620 spin_lock_irqsave(&mv643xx_eth_phy_lock, flags);
2622 /* wait for the SMI register to become available */
2623 for (i = 0; mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_BUSY; i++) {
2624 if (i == PHY_WAIT_ITERATIONS) {
2625 printk("mv643xx PHY busy timeout, port %d\n",
2629 udelay(PHY_WAIT_MICRO_SECONDS);
2632 mv_write(MV643XX_ETH_SMI_REG, (phy_addr << 16) | (phy_reg << 21) |
2633 ETH_SMI_OPCODE_WRITE | (value & 0xffff));
2635 spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags);
2639 * eth_port_send - Send an Ethernet packet
2642 * This routine send a given packet described by p_pktinfo parameter. It
2643 * supports transmitting of a packet spaned over multiple buffers. The
2644 * routine updates 'curr' and 'first' indexes according to the packet
2645 * segment passed to the routine. In case the packet segment is first,
2646 * the 'first' index is update. In any case, the 'curr' index is updated.
2647 * If the routine get into Tx resource error it assigns 'curr' index as
2648 * 'first'. This way the function can abort Tx process of multiple
2649 * descriptors per packet.
2652 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2653 * struct pkt_info *p_pkt_info User packet buffer.
2656 * Tx ring 'curr' and 'first' indexes are updated.
2659 * ETH_QUEUE_FULL in case of Tx resource error.
2660 * ETH_ERROR in case the routine can not access Tx desc ring.
2661 * ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource.
2665 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
2667 * Modified to include the first descriptor pointer in case of SG
2669 static ETH_FUNC_RET_STATUS eth_port_send(struct mv643xx_private *mp,
2670 struct pkt_info *p_pkt_info)
2672 int tx_desc_curr, tx_desc_used, tx_first_desc, tx_next_desc;
2673 struct eth_tx_desc *current_descriptor;
2674 struct eth_tx_desc *first_descriptor;
2677 /* Do not process Tx ring in case of Tx ring resource error */
2678 if (mp->tx_resource_err)
2679 return ETH_QUEUE_FULL;
2682 * The hardware requires that each buffer that is <= 8 bytes
2683 * in length must be aligned on an 8 byte boundary.
2685 if (p_pkt_info->byte_cnt <= 8 && p_pkt_info->buf_ptr & 0x7) {
2687 "mv643xx_eth port %d: packet size <= 8 problem\n",
2693 BUG_ON(mp->tx_ring_skbs > mp->tx_ring_size);
2695 /* Get the Tx Desc ring indexes */
2696 tx_desc_curr = mp->tx_curr_desc_q;
2697 tx_desc_used = mp->tx_used_desc_q;
2699 current_descriptor = &mp->p_tx_desc_area[tx_desc_curr];
2701 tx_next_desc = (tx_desc_curr + 1) % mp->tx_ring_size;
2703 current_descriptor->buf_ptr = p_pkt_info->buf_ptr;
2704 current_descriptor->byte_cnt = p_pkt_info->byte_cnt;
2705 current_descriptor->l4i_chk = p_pkt_info->l4i_chk;
2706 mp->tx_skb[tx_desc_curr] = p_pkt_info->return_info;
2708 command = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC |
2709 ETH_BUFFER_OWNED_BY_DMA;
2710 if (command & ETH_TX_FIRST_DESC) {
2711 tx_first_desc = tx_desc_curr;
2712 mp->tx_first_desc_q = tx_first_desc;
2713 first_descriptor = current_descriptor;
2714 mp->tx_first_command = command;
2716 tx_first_desc = mp->tx_first_desc_q;
2717 first_descriptor = &mp->p_tx_desc_area[tx_first_desc];
2718 BUG_ON(first_descriptor == NULL);
2719 current_descriptor->cmd_sts = command;
2722 if (command & ETH_TX_LAST_DESC) {
2724 first_descriptor->cmd_sts = mp->tx_first_command;
2727 ETH_ENABLE_TX_QUEUE(mp->port_num);
2730 * Finish Tx packet. Update first desc in case of Tx resource
2732 tx_first_desc = tx_next_desc;
2733 mp->tx_first_desc_q = tx_first_desc;
2736 /* Check for ring index overlap in the Tx desc ring */
2737 if (tx_next_desc == tx_desc_used) {
2738 mp->tx_resource_err = 1;
2739 mp->tx_curr_desc_q = tx_first_desc;
2741 return ETH_QUEUE_LAST_RESOURCE;
2744 mp->tx_curr_desc_q = tx_next_desc;
2749 static ETH_FUNC_RET_STATUS eth_port_send(struct mv643xx_private *mp,
2750 struct pkt_info *p_pkt_info)
2754 struct eth_tx_desc *current_descriptor;
2755 unsigned int command_status;
2757 /* Do not process Tx ring in case of Tx ring resource error */
2758 if (mp->tx_resource_err)
2759 return ETH_QUEUE_FULL;
2762 BUG_ON(mp->tx_ring_skbs > mp->tx_ring_size);
2764 /* Get the Tx Desc ring indexes */
2765 tx_desc_curr = mp->tx_curr_desc_q;
2766 tx_desc_used = mp->tx_used_desc_q;
2767 current_descriptor = &mp->p_tx_desc_area[tx_desc_curr];
2769 command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC;
2770 current_descriptor->buf_ptr = p_pkt_info->buf_ptr;
2771 current_descriptor->byte_cnt = p_pkt_info->byte_cnt;
2772 mp->tx_skb[tx_desc_curr] = p_pkt_info->return_info;
2774 /* Set last desc with DMA ownership and interrupt enable. */
2776 current_descriptor->cmd_sts = command_status |
2777 ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT;
2780 ETH_ENABLE_TX_QUEUE(mp->port_num);
2782 /* Finish Tx packet. Update first desc in case of Tx resource error */
2783 tx_desc_curr = (tx_desc_curr + 1) % mp->tx_ring_size;
2785 /* Update the current descriptor */
2786 mp->tx_curr_desc_q = tx_desc_curr;
2788 /* Check for ring index overlap in the Tx desc ring */
2789 if (tx_desc_curr == tx_desc_used) {
2790 mp->tx_resource_err = 1;
2791 return ETH_QUEUE_LAST_RESOURCE;
2799 * eth_tx_return_desc - Free all used Tx descriptors
2802 * This routine returns the transmitted packet information to the caller.
2803 * It uses the 'first' index to support Tx desc return in case a transmit
2804 * of a packet spanned over multiple buffer still in process.
2805 * In case the Tx queue was in "resource error" condition, where there are
2806 * no available Tx resources, the function resets the resource error flag.
2809 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2810 * struct pkt_info *p_pkt_info User packet buffer.
2813 * Tx ring 'first' and 'used' indexes are updated.
2816 * ETH_ERROR in case the routine can not access Tx desc ring.
2817 * ETH_RETRY in case there is transmission in process.
2818 * ETH_END_OF_JOB if the routine has nothing to release.
2822 static ETH_FUNC_RET_STATUS eth_tx_return_desc(struct mv643xx_private *mp,
2823 struct pkt_info *p_pkt_info)
2826 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
2827 int tx_busy_desc = mp->tx_first_desc_q;
2829 int tx_busy_desc = mp->tx_curr_desc_q;
2831 struct eth_tx_desc *p_tx_desc_used;
2832 unsigned int command_status;
2834 /* Get the Tx Desc ring indexes */
2835 tx_desc_used = mp->tx_used_desc_q;
2837 p_tx_desc_used = &mp->p_tx_desc_area[tx_desc_used];
2840 if (p_tx_desc_used == NULL)
2843 /* Stop release. About to overlap the current available Tx descriptor */
2844 if (tx_desc_used == tx_busy_desc && !mp->tx_resource_err)
2845 return ETH_END_OF_JOB;
2847 command_status = p_tx_desc_used->cmd_sts;
2849 /* Still transmitting... */
2850 if (command_status & (ETH_BUFFER_OWNED_BY_DMA))
2853 /* Pass the packet information to the caller */
2854 p_pkt_info->cmd_sts = command_status;
2855 p_pkt_info->return_info = mp->tx_skb[tx_desc_used];
2856 p_pkt_info->buf_ptr = p_tx_desc_used->buf_ptr;
2857 p_pkt_info->byte_cnt = p_tx_desc_used->byte_cnt;
2858 mp->tx_skb[tx_desc_used] = NULL;
2860 /* Update the next descriptor to release. */
2861 mp->tx_used_desc_q = (tx_desc_used + 1) % mp->tx_ring_size;
2863 /* Any Tx return cancels the Tx resource error status */
2864 mp->tx_resource_err = 0;
2866 BUG_ON(mp->tx_ring_skbs == 0);
2873 * eth_port_receive - Get received information from Rx ring.
2876 * This routine returns the received data to the caller. There is no
2877 * data copying during routine operation. All information is returned
2878 * using pointer to packet information struct passed from the caller.
2879 * If the routine exhausts Rx ring resources then the resource error flag
2883 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2884 * struct pkt_info *p_pkt_info User packet buffer.
2887 * Rx ring current and used indexes are updated.
2890 * ETH_ERROR in case the routine can not access Rx desc ring.
2891 * ETH_QUEUE_FULL if Rx ring resources are exhausted.
2892 * ETH_END_OF_JOB if there is no received data.
2895 static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
2896 struct pkt_info *p_pkt_info)
2898 int rx_next_curr_desc, rx_curr_desc, rx_used_desc;
2899 volatile struct eth_rx_desc *p_rx_desc;
2900 unsigned int command_status;
2902 /* Do not process Rx ring in case of Rx ring resource error */
2903 if (mp->rx_resource_err)
2904 return ETH_QUEUE_FULL;
2906 /* Get the Rx Desc ring 'curr and 'used' indexes */
2907 rx_curr_desc = mp->rx_curr_desc_q;
2908 rx_used_desc = mp->rx_used_desc_q;
2910 p_rx_desc = &mp->p_rx_desc_area[rx_curr_desc];
2912 /* The following parameters are used to save readings from memory */
2913 command_status = p_rx_desc->cmd_sts;
2916 /* Nothing to receive... */
2917 if (command_status & (ETH_BUFFER_OWNED_BY_DMA))
2918 return ETH_END_OF_JOB;
2920 p_pkt_info->byte_cnt = (p_rx_desc->byte_cnt) - RX_BUF_OFFSET;
2921 p_pkt_info->cmd_sts = command_status;
2922 p_pkt_info->buf_ptr = (p_rx_desc->buf_ptr) + RX_BUF_OFFSET;
2923 p_pkt_info->return_info = mp->rx_skb[rx_curr_desc];
2924 p_pkt_info->l4i_chk = p_rx_desc->buf_size;
2926 /* Clean the return info field to indicate that the packet has been */
2927 /* moved to the upper layers */
2928 mp->rx_skb[rx_curr_desc] = NULL;
2930 /* Update current index in data structure */
2931 rx_next_curr_desc = (rx_curr_desc + 1) % mp->rx_ring_size;
2932 mp->rx_curr_desc_q = rx_next_curr_desc;
2934 /* Rx descriptors exhausted. Set the Rx ring resource error flag */
2935 if (rx_next_curr_desc == rx_used_desc)
2936 mp->rx_resource_err = 1;
2942 * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
2945 * This routine returns a Rx buffer back to the Rx ring. It retrieves the
2946 * next 'used' descriptor and attached the returned buffer to it.
2947 * In case the Rx ring was in "resource error" condition, where there are
2948 * no available Rx resources, the function resets the resource error flag.
2951 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2952 * struct pkt_info *p_pkt_info Information on returned buffer.
2955 * New available Rx resource in Rx descriptor ring.
2958 * ETH_ERROR in case the routine can not access Rx desc ring.
2961 static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
2962 struct pkt_info *p_pkt_info)
2964 int used_rx_desc; /* Where to return Rx resource */
2965 volatile struct eth_rx_desc *p_used_rx_desc;
2967 /* Get 'used' Rx descriptor */
2968 used_rx_desc = mp->rx_used_desc_q;
2969 p_used_rx_desc = &mp->p_rx_desc_area[used_rx_desc];
2971 p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
2972 p_used_rx_desc->buf_size = p_pkt_info->byte_cnt;
2973 mp->rx_skb[used_rx_desc] = p_pkt_info->return_info;
2975 /* Flush the write pipe */
2977 /* Return the descriptor to DMA ownership */
2979 p_used_rx_desc->cmd_sts =
2980 ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
2983 /* Move the used descriptor pointer to the next descriptor */
2984 mp->rx_used_desc_q = (used_rx_desc + 1) % mp->rx_ring_size;
2986 /* Any Rx return cancels the Rx resource error status */
2987 mp->rx_resource_err = 0;
2992 /************* Begin ethtool support *************************/
2994 struct mv643xx_stats {
2995 char stat_string[ETH_GSTRING_LEN];
3000 #define MV643XX_STAT(m) sizeof(((struct mv643xx_private *)0)->m), \
3001 offsetof(struct mv643xx_private, m)
3003 static const struct mv643xx_stats mv643xx_gstrings_stats[] = {
3004 { "rx_packets", MV643XX_STAT(stats.rx_packets) },
3005 { "tx_packets", MV643XX_STAT(stats.tx_packets) },
3006 { "rx_bytes", MV643XX_STAT(stats.rx_bytes) },
3007 { "tx_bytes", MV643XX_STAT(stats.tx_bytes) },
3008 { "rx_errors", MV643XX_STAT(stats.rx_errors) },
3009 { "tx_errors", MV643XX_STAT(stats.tx_errors) },
3010 { "rx_dropped", MV643XX_STAT(stats.rx_dropped) },
3011 { "tx_dropped", MV643XX_STAT(stats.tx_dropped) },
3012 { "good_octets_received", MV643XX_STAT(mib_counters.good_octets_received) },
3013 { "bad_octets_received", MV643XX_STAT(mib_counters.bad_octets_received) },
3014 { "internal_mac_transmit_err", MV643XX_STAT(mib_counters.internal_mac_transmit_err) },
3015 { "good_frames_received", MV643XX_STAT(mib_counters.good_frames_received) },
3016 { "bad_frames_received", MV643XX_STAT(mib_counters.bad_frames_received) },
3017 { "broadcast_frames_received", MV643XX_STAT(mib_counters.broadcast_frames_received) },
3018 { "multicast_frames_received", MV643XX_STAT(mib_counters.multicast_frames_received) },
3019 { "frames_64_octets", MV643XX_STAT(mib_counters.frames_64_octets) },
3020 { "frames_65_to_127_octets", MV643XX_STAT(mib_counters.frames_65_to_127_octets) },
3021 { "frames_128_to_255_octets", MV643XX_STAT(mib_counters.frames_128_to_255_octets) },
3022 { "frames_256_to_511_octets", MV643XX_STAT(mib_counters.frames_256_to_511_octets) },
3023 { "frames_512_to_1023_octets", MV643XX_STAT(mib_counters.frames_512_to_1023_octets) },
3024 { "frames_1024_to_max_octets", MV643XX_STAT(mib_counters.frames_1024_to_max_octets) },
3025 { "good_octets_sent", MV643XX_STAT(mib_counters.good_octets_sent) },
3026 { "good_frames_sent", MV643XX_STAT(mib_counters.good_frames_sent) },
3027 { "excessive_collision", MV643XX_STAT(mib_counters.excessive_collision) },
3028 { "multicast_frames_sent", MV643XX_STAT(mib_counters.multicast_frames_sent) },
3029 { "broadcast_frames_sent", MV643XX_STAT(mib_counters.broadcast_frames_sent) },
3030 { "unrec_mac_control_received", MV643XX_STAT(mib_counters.unrec_mac_control_received) },
3031 { "fc_sent", MV643XX_STAT(mib_counters.fc_sent) },
3032 { "good_fc_received", MV643XX_STAT(mib_counters.good_fc_received) },
3033 { "bad_fc_received", MV643XX_STAT(mib_counters.bad_fc_received) },
3034 { "undersize_received", MV643XX_STAT(mib_counters.undersize_received) },
3035 { "fragments_received", MV643XX_STAT(mib_counters.fragments_received) },
3036 { "oversize_received", MV643XX_STAT(mib_counters.oversize_received) },
3037 { "jabber_received", MV643XX_STAT(mib_counters.jabber_received) },
3038 { "mac_receive_error", MV643XX_STAT(mib_counters.mac_receive_error) },
3039 { "bad_crc_event", MV643XX_STAT(mib_counters.bad_crc_event) },
3040 { "collision", MV643XX_STAT(mib_counters.collision) },
3041 { "late_collision", MV643XX_STAT(mib_counters.late_collision) },
3044 #define MV643XX_STATS_LEN \
3045 sizeof(mv643xx_gstrings_stats) / sizeof(struct mv643xx_stats)
3048 mv643xx_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
3050 struct mv643xx_private *mp = netdev->priv;
3051 int port_num = mp->port_num;
3052 int autoneg = eth_port_autoneg_supported(port_num);
3055 int half_duplex = 0;
3056 int full_duplex = 0;
3062 u32 pcs = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num));
3063 u32 psr = mv_read(MV643XX_ETH_PORT_STATUS_REG(port_num));
3065 mode_10_bit = psr & MV643XX_ETH_PORT_STATUS_MODE_10_BIT;
3068 ecmd->supported = SUPPORTED_10baseT_Half;
3070 ecmd->supported = (SUPPORTED_10baseT_Half |
3071 SUPPORTED_10baseT_Full |
3072 SUPPORTED_100baseT_Half |
3073 SUPPORTED_100baseT_Full |
3074 SUPPORTED_1000baseT_Full |
3075 (autoneg ? SUPPORTED_Autoneg : 0) |
3078 auto_duplex = !(pcs & MV643XX_ETH_DISABLE_AUTO_NEG_FOR_DUPLX);
3079 auto_speed = !(pcs & MV643XX_ETH_DISABLE_AUTO_NEG_SPEED_GMII);
3081 ecmd->advertising = ADVERTISED_TP;
3084 ecmd->advertising |= ADVERTISED_Autoneg;
3090 if (pcs & MV643XX_ETH_SET_FULL_DUPLEX_MODE)
3101 if (pcs & MV643XX_ETH_SET_GMII_SPEED_TO_1000)
3103 else if (pcs & MV643XX_ETH_SET_MII_SPEED_TO_100)
3109 if (speed_10 & half_duplex)
3110 ecmd->advertising |= ADVERTISED_10baseT_Half;
3111 if (speed_10 & full_duplex)
3112 ecmd->advertising |= ADVERTISED_10baseT_Full;
3113 if (speed_100 & half_duplex)
3114 ecmd->advertising |= ADVERTISED_100baseT_Half;
3115 if (speed_100 & full_duplex)
3116 ecmd->advertising |= ADVERTISED_100baseT_Full;
3118 ecmd->advertising |= ADVERTISED_1000baseT_Full;
3122 ecmd->port = PORT_TP;
3123 ecmd->phy_address = ethernet_phy_get(port_num);
3125 ecmd->transceiver = XCVR_EXTERNAL;
3127 if (netif_carrier_ok(netdev)) {
3129 ecmd->speed = SPEED_10;
3131 if (psr & MV643XX_ETH_PORT_STATUS_GMII_1000)
3132 ecmd->speed = SPEED_1000;
3133 else if (psr & MV643XX_ETH_PORT_STATUS_MII_100)
3134 ecmd->speed = SPEED_100;
3136 ecmd->speed = SPEED_10;
3139 if (psr & MV643XX_ETH_PORT_STATUS_FULL_DUPLEX)
3140 ecmd->duplex = DUPLEX_FULL;
3142 ecmd->duplex = DUPLEX_HALF;
3148 ecmd->autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3153 mv643xx_get_drvinfo(struct net_device *netdev,
3154 struct ethtool_drvinfo *drvinfo)
3156 strncpy(drvinfo->driver, mv643xx_driver_name, 32);
3157 strncpy(drvinfo->version, mv643xx_driver_version, 32);
3158 strncpy(drvinfo->fw_version, "N/A", 32);
3159 strncpy(drvinfo->bus_info, "mv643xx", 32);
3160 drvinfo->n_stats = MV643XX_STATS_LEN;
3164 mv643xx_get_stats_count(struct net_device *netdev)
3166 return MV643XX_STATS_LEN;
3170 mv643xx_get_ethtool_stats(struct net_device *netdev,
3171 struct ethtool_stats *stats, uint64_t *data)
3173 struct mv643xx_private *mp = netdev->priv;
3176 eth_update_mib_counters(mp);
3178 for(i = 0; i < MV643XX_STATS_LEN; i++) {
3179 char *p = (char *)mp+mv643xx_gstrings_stats[i].stat_offset;
3180 data[i] = (mv643xx_gstrings_stats[i].sizeof_stat ==
3181 sizeof(uint64_t)) ? *(uint64_t *)p : *(uint32_t *)p;
3186 mv643xx_get_strings(struct net_device *netdev, uint32_t stringset, uint8_t *data)
3192 for (i=0; i < MV643XX_STATS_LEN; i++) {
3193 memcpy(data + i * ETH_GSTRING_LEN,
3194 mv643xx_gstrings_stats[i].stat_string,
3201 static struct ethtool_ops mv643xx_ethtool_ops = {
3202 .get_settings = mv643xx_get_settings,
3203 .get_drvinfo = mv643xx_get_drvinfo,
3204 .get_link = ethtool_op_get_link,
3205 .get_sg = ethtool_op_get_sg,
3206 .set_sg = ethtool_op_set_sg,
3207 .get_strings = mv643xx_get_strings,
3208 .get_stats_count = mv643xx_get_stats_count,
3209 .get_ethtool_stats = mv643xx_get_ethtool_stats,
3212 /************* End ethtool support *************************/