1 #ifndef __MV643XX_ETH_H__
2 #define __MV643XX_ETH_H__
4 #include <linux/module.h>
5 #include <linux/kernel.h>
6 #include <linux/spinlock.h>
7 #include <linux/workqueue.h>
10 #include <linux/mv643xx_eth.h>
12 #include <asm/dma-mapping.h>
14 /* Checksum offload for Tx works for most packets, but
15 * fails if previous packet sent did not use hw csum
17 #define MV643XX_CHECKSUM_OFFLOAD_TX
19 #define MV643XX_TX_FAST_REFILL
23 * Number of RX / TX descriptors on RX / TX rings.
24 * Note that allocating RX descriptors is done by allocating the RX
25 * ring AND a preallocated RX buffers (skb's) for each descriptor.
26 * The TX descriptors only allocates the TX descriptors ring,
27 * with no pre allocated TX buffers (skb's are allocated by higher layers.
30 /* Default TX ring size is 1000 descriptors */
31 #define MV643XX_DEFAULT_TX_QUEUE_SIZE 1000
33 /* Default RX ring size is 400 descriptors */
34 #define MV643XX_DEFAULT_RX_QUEUE_SIZE 400
36 #define MV643XX_TX_COAL 100
38 #define MV643XX_RX_COAL 100
41 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
42 #define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
44 #define MAX_DESCS_PER_SKB 1
47 #define ETH_VLAN_HLEN 4
49 #define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */
50 #define ETH_WRAPPER_LEN (ETH_HW_IP_ALIGN + ETH_HLEN + \
51 ETH_VLAN_HLEN + ETH_FCS_LEN)
52 #define ETH_RX_SKB_SIZE (dev->mtu + ETH_WRAPPER_LEN + dma_get_cache_alignment())
54 /****************************************/
55 /* Ethernet Unit Registers */
56 /****************************************/
58 #define PHY_ADDR_REG 0x0000
59 #define SMI_REG 0x0004
60 #define UNIT_DEFAULT_ADDR_REG 0x0008
61 #define UNIT_DEFAULTID_REG 0x000c
62 #define UNIT_INTERRUPT_CAUSE_REG 0x0080
63 #define UNIT_INTERRUPT_MASK_REG 0x0084
64 #define UNIT_INTERNAL_USE_REG 0x04fc
65 #define UNIT_ERROR_ADDR_REG 0x0094
72 #define SIZE_REG_0 0x0204
73 #define SIZE_REG_1 0x020c
74 #define SIZE_REG_2 0x0214
75 #define SIZE_REG_3 0x021c
76 #define SIZE_REG_4 0x0224
77 #define SIZE_REG_5 0x022c
78 #define HEADERS_RETARGET_BASE_REG 0x0230
79 #define HEADERS_RETARGET_CONTROL_REG 0x0234
80 #define HIGH_ADDR_REMAP_REG_0 0x0280
81 #define HIGH_ADDR_REMAP_REG_1 0x0284
82 #define HIGH_ADDR_REMAP_REG_2 0x0288
83 #define HIGH_ADDR_REMAP_REG_3 0x028c
84 #define BASE_ADDR_ENABLE_REG 0x0290
85 #define ACCESS_PROTECTION_REG(port) (0x0294 + (port<<2))
86 #define MIB_COUNTERS_BASE(port) (0x1000 + (port<<7))
87 #define PORT_CONFIG_REG(port) (0x0400 + (port<<10))
88 #define PORT_CONFIG_EXTEND_REG(port) (0x0404 + (port<<10))
89 #define MII_SERIAL_PARAMETRS_REG(port) (0x0408 + (port<<10))
90 #define GMII_SERIAL_PARAMETRS_REG(port) (0x040c + (port<<10))
91 #define VLAN_ETHERTYPE_REG(port) (0x0410 + (port<<10))
92 #define MAC_ADDR_LOW(port) (0x0414 + (port<<10))
93 #define MAC_ADDR_HIGH(port) (0x0418 + (port<<10))
94 #define SDMA_CONFIG_REG(port) (0x041c + (port<<10))
95 #define DSCP_0(port) (0x0420 + (port<<10))
96 #define DSCP_1(port) (0x0424 + (port<<10))
97 #define DSCP_2(port) (0x0428 + (port<<10))
98 #define DSCP_3(port) (0x042c + (port<<10))
99 #define DSCP_4(port) (0x0430 + (port<<10))
100 #define DSCP_5(port) (0x0434 + (port<<10))
101 #define DSCP_6(port) (0x0438 + (port<<10))
102 #define PORT_SERIAL_CONTROL_REG(port) (0x043c + (port<<10))
103 #define VLAN_PRIORITY_TAG_TO_PRIORITY(port) (0x0440 + (port<<10))
104 #define PORT_STATUS_REG(port) (0x0444 + (port<<10))
105 #define TRANSMIT_QUEUE_COMMAND_REG(port) (0x0448 + (port<<10))
106 #define TX_QUEUE_FIXED_PRIORITY(port) (0x044c + (port<<10))
107 #define PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port) (0x0450 + (port<<10))
108 #define MAXIMUM_TRANSMIT_UNIT(port) (0x0458 + (port<<10))
109 #define PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port) (0x045c + (port<<10))
110 #define INTERRUPT_CAUSE_REG(port) (0x0460 + (port<<10))
111 #define INTERRUPT_CAUSE_EXTEND_REG(port) (0x0464 + (port<<10))
112 #define INTERRUPT_MASK_REG(port) (0x0468 + (port<<10))
113 #define INTERRUPT_EXTEND_MASK_REG(port) (0x046c + (port<<10))
114 #define RX_FIFO_URGENT_THRESHOLD_REG(port) (0x0470 + (port<<10))
115 #define TX_FIFO_URGENT_THRESHOLD_REG(port) (0x0474 + (port<<10))
116 #define RX_MINIMAL_FRAME_SIZE_REG(port) (0x047c + (port<<10))
117 #define RX_DISCARDED_FRAMES_COUNTER(port) (0x0484 + (port<<10))
118 #define PORT_DEBUG_0_REG(port) (0x048c + (port<<10))
119 #define PORT_DEBUG_1_REG(port) (0x0490 + (port<<10))
120 #define PORT_INTERNAL_ADDR_ERROR_REG(port) (0x0494 + (port<<10))
121 #define INTERNAL_USE_REG(port) (0x04fc + (port<<10))
122 #define RECEIVE_QUEUE_COMMAND_REG(port) (0x0680 + (port<<10))
123 #define CURRENT_SERVED_TX_DESC_PTR(port) (0x0684 + (port<<10))
124 #define RX_CURRENT_QUEUE_DESC_PTR_0(port) (0x060c + (port<<10))
125 #define RX_CURRENT_QUEUE_DESC_PTR_1(port) (0x061c + (port<<10))
126 #define RX_CURRENT_QUEUE_DESC_PTR_2(port) (0x062c + (port<<10))
127 #define RX_CURRENT_QUEUE_DESC_PTR_3(port) (0x063c + (port<<10))
128 #define RX_CURRENT_QUEUE_DESC_PTR_4(port) (0x064c + (port<<10))
129 #define RX_CURRENT_QUEUE_DESC_PTR_5(port) (0x065c + (port<<10))
130 #define RX_CURRENT_QUEUE_DESC_PTR_6(port) (0x066c + (port<<10))
131 #define RX_CURRENT_QUEUE_DESC_PTR_7(port) (0x067c + (port<<10))
132 #define TX_CURRENT_QUEUE_DESC_PTR_0(port) (0x06c0 + (port<<10))
133 #define TX_CURRENT_QUEUE_DESC_PTR_1(port) (0x06c4 + (port<<10))
134 #define TX_CURRENT_QUEUE_DESC_PTR_2(port) (0x06c8 + (port<<10))
135 #define TX_CURRENT_QUEUE_DESC_PTR_3(port) (0x06cc + (port<<10))
136 #define TX_CURRENT_QUEUE_DESC_PTR_4(port) (0x06d0 + (port<<10))
137 #define TX_CURRENT_QUEUE_DESC_PTR_5(port) (0x06d4 + (port<<10))
138 #define TX_CURRENT_QUEUE_DESC_PTR_6(port) (0x06d8 + (port<<10))
139 #define TX_CURRENT_QUEUE_DESC_PTR_7(port) (0x06dc + (port<<10))
140 #define TX_QUEUE_0_TOKEN_BUCKET_COUNT(port) (0x0700 + (port<<10))
141 #define TX_QUEUE_1_TOKEN_BUCKET_COUNT(port) (0x0710 + (port<<10))
142 #define TX_QUEUE_2_TOKEN_BUCKET_COUNT(port) (0x0720 + (port<<10))
143 #define TX_QUEUE_3_TOKEN_BUCKET_COUNT(port) (0x0730 + (port<<10))
144 #define TX_QUEUE_4_TOKEN_BUCKET_COUNT(port) (0x0740 + (port<<10))
145 #define TX_QUEUE_5_TOKEN_BUCKET_COUNT(port) (0x0750 + (port<<10))
146 #define TX_QUEUE_6_TOKEN_BUCKET_COUNT(port) (0x0760 + (port<<10))
147 #define TX_QUEUE_7_TOKEN_BUCKET_COUNT(port) (0x0770 + (port<<10))
148 #define TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port) (0x0704 + (port<<10))
149 #define TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port) (0x0714 + (port<<10))
150 #define TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port) (0x0724 + (port<<10))
151 #define TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port) (0x0734 + (port<<10))
152 #define TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port) (0x0744 + (port<<10))
153 #define TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port) (0x0754 + (port<<10))
154 #define TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port) (0x0764 + (port<<10))
155 #define TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port) (0x0774 + (port<<10))
156 #define TX_QUEUE_0_ARBITER_CONFIG(port) (0x0708 + (port<<10))
157 #define TX_QUEUE_1_ARBITER_CONFIG(port) (0x0718 + (port<<10))
158 #define TX_QUEUE_2_ARBITER_CONFIG(port) (0x0728 + (port<<10))
159 #define TX_QUEUE_3_ARBITER_CONFIG(port) (0x0738 + (port<<10))
160 #define TX_QUEUE_4_ARBITER_CONFIG(port) (0x0748 + (port<<10))
161 #define TX_QUEUE_5_ARBITER_CONFIG(port) (0x0758 + (port<<10))
162 #define TX_QUEUE_6_ARBITER_CONFIG(port) (0x0768 + (port<<10))
163 #define TX_QUEUE_7_ARBITER_CONFIG(port) (0x0778 + (port<<10))
164 #define PORT_TX_TOKEN_BUCKET_COUNT(port) (0x0780 + (port<<10))
165 #define DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port) (0x1400 + (port<<10))
166 #define DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x1500 + (port<<10))
167 #define DA_FILTER_UNICAST_TABLE_BASE(port) (0x1600 + (port<<10))
169 /* These macros describe Ethernet Port configuration reg (Px_cR) bits */
170 #define UNICAST_NORMAL_MODE 0
171 #define UNICAST_PROMISCUOUS_MODE (1<<0)
172 #define DEFAULT_RX_QUEUE_0 0
173 #define DEFAULT_RX_QUEUE_1 (1<<1)
174 #define DEFAULT_RX_QUEUE_2 (1<<2)
175 #define DEFAULT_RX_QUEUE_3 ((1<<2) | (1<<1))
176 #define DEFAULT_RX_QUEUE_4 (1<<3)
177 #define DEFAULT_RX_QUEUE_5 ((1<<3) | (1<<1))
178 #define DEFAULT_RX_QUEUE_6 ((1<<3) | (1<<2))
179 #define DEFAULT_RX_QUEUE_7 ((1<<3) | (1<<2) | (1<<1))
180 #define DEFAULT_RX_ARP_QUEUE_0 0
181 #define DEFAULT_RX_ARP_QUEUE_1 (1<<4)
182 #define DEFAULT_RX_ARP_QUEUE_2 (1<<5)
183 #define DEFAULT_RX_ARP_QUEUE_3 ((1<<5) | (1<<4))
184 #define DEFAULT_RX_ARP_QUEUE_4 (1<<6)
185 #define DEFAULT_RX_ARP_QUEUE_5 ((1<<6) | (1<<4))
186 #define DEFAULT_RX_ARP_QUEUE_6 ((1<<6) | (1<<5))
187 #define DEFAULT_RX_ARP_QUEUE_7 ((1<<6) | (1<<5) | (1<<4))
188 #define RECEIVE_BC_IF_NOT_IP_OR_ARP 0
189 #define REJECT_BC_IF_NOT_IP_OR_ARP (1<<7)
190 #define RECEIVE_BC_IF_IP 0
191 #define REJECT_BC_IF_IP (1<<8)
192 #define RECEIVE_BC_IF_ARP 0
193 #define REJECT_BC_IF_ARP (1<<9)
194 #define TX_AM_NO_UPDATE_ERROR_SUMMARY (1<<12)
195 #define CAPTURE_TCP_FRAMES_DIS 0
196 #define CAPTURE_TCP_FRAMES_EN (1<<14)
197 #define CAPTURE_UDP_FRAMES_DIS 0
198 #define CAPTURE_UDP_FRAMES_EN (1<<15)
199 #define DEFAULT_RX_TCP_QUEUE_0 0
200 #define DEFAULT_RX_TCP_QUEUE_1 (1<<16)
201 #define DEFAULT_RX_TCP_QUEUE_2 (1<<17)
202 #define DEFAULT_RX_TCP_QUEUE_3 ((1<<17) | (1<<16))
203 #define DEFAULT_RX_TCP_QUEUE_4 (1<<18)
204 #define DEFAULT_RX_TCP_QUEUE_5 ((1<<18) | (1<<16))
205 #define DEFAULT_RX_TCP_QUEUE_6 ((1<<18) | (1<<17))
206 #define DEFAULT_RX_TCP_QUEUE_7 ((1<<18) | (1<<17) | (1<<16))
207 #define DEFAULT_RX_UDP_QUEUE_0 0
208 #define DEFAULT_RX_UDP_QUEUE_1 (1<<19)
209 #define DEFAULT_RX_UDP_QUEUE_2 (1<<20)
210 #define DEFAULT_RX_UDP_QUEUE_3 ((1<<20) | (1<<19))
211 #define DEFAULT_RX_UDP_QUEUE_4 (1<<21)
212 #define DEFAULT_RX_UDP_QUEUE_5 ((1<<21) | (1<<19))
213 #define DEFAULT_RX_UDP_QUEUE_6 ((1<<21) | (1<<20))
214 #define DEFAULT_RX_UDP_QUEUE_7 ((1<<21) | (1<<20) | (1<<19))
215 #define DEFAULT_RX_BPDU_QUEUE_0 0
216 #define DEFAULT_RX_BPDU_QUEUE_1 (1<<22)
217 #define DEFAULT_RX_BPDU_QUEUE_2 (1<<23)
218 #define DEFAULT_RX_BPDU_QUEUE_3 ((1<<23) | (1<<22))
219 #define DEFAULT_RX_BPDU_QUEUE_4 (1<<24)
220 #define DEFAULT_RX_BPDU_QUEUE_5 ((1<<24) | (1<<22))
221 #define DEFAULT_RX_BPDU_QUEUE_6 ((1<<24) | (1<<23))
222 #define DEFAULT_RX_BPDU_QUEUE_7 ((1<<24) | (1<<23) | (1<<22))
224 #define PORT_CONFIG_DEFAULT_VALUE \
225 UNICAST_NORMAL_MODE | \
226 DEFAULT_RX_QUEUE_0 | \
227 DEFAULT_RX_ARP_QUEUE_0 | \
228 RECEIVE_BC_IF_NOT_IP_OR_ARP | \
230 RECEIVE_BC_IF_ARP | \
231 CAPTURE_TCP_FRAMES_DIS | \
232 CAPTURE_UDP_FRAMES_DIS | \
233 DEFAULT_RX_TCP_QUEUE_0 | \
234 DEFAULT_RX_UDP_QUEUE_0 | \
235 DEFAULT_RX_BPDU_QUEUE_0
237 /* These macros describe Ethernet Port configuration extend reg (Px_cXR) bits*/
238 #define CLASSIFY_EN (1<<0)
239 #define SPAN_BPDU_PACKETS_AS_NORMAL 0
240 #define SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 (1<<1)
241 #define PARTITION_DISABLE 0
242 #define PARTITION_ENABLE (1<<2)
244 #define PORT_CONFIG_EXTEND_DEFAULT_VALUE \
245 SPAN_BPDU_PACKETS_AS_NORMAL | \
248 /* These macros describe Ethernet Port Sdma configuration reg (SDCR) bits */
250 #define RX_BURST_SIZE_1_64BIT 0
251 #define RX_BURST_SIZE_2_64BIT (1<<1)
252 #define RX_BURST_SIZE_4_64BIT (1<<2)
253 #define RX_BURST_SIZE_8_64BIT ((1<<2) | (1<<1))
254 #define RX_BURST_SIZE_16_64BIT (1<<3)
255 #define BLM_RX_NO_SWAP (1<<4)
256 #define BLM_RX_BYTE_SWAP 0
257 #define BLM_TX_NO_SWAP (1<<5)
258 #define BLM_TX_BYTE_SWAP 0
259 #define DESCRIPTORS_BYTE_SWAP (1<<6)
260 #define DESCRIPTORS_NO_SWAP 0
261 #define TX_BURST_SIZE_1_64BIT 0
262 #define TX_BURST_SIZE_2_64BIT (1<<22)
263 #define TX_BURST_SIZE_4_64BIT (1<<23)
264 #define TX_BURST_SIZE_8_64BIT ((1<<23) | (1<<22))
265 #define TX_BURST_SIZE_16_64BIT (1<<24)
267 #define IPG_INT_RX(value) ((value & 0x3fff) << 8)
269 #if defined(__BIG_ENDIAN)
270 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
271 RX_BURST_SIZE_4_64BIT | \
273 TX_BURST_SIZE_4_64BIT
274 #elif defined(__LITTLE_ENDIAN)
275 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
276 RX_BURST_SIZE_4_64BIT | \
280 TX_BURST_SIZE_4_64BIT
282 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
285 /* These macros describe Ethernet Port serial control reg (PSCR) bits */
286 #define SERIAL_PORT_DISABLE 0
287 #define SERIAL_PORT_ENABLE (1<<0)
288 #define FORCE_LINK_PASS (1<<1)
289 #define DO_NOT_FORCE_LINK_PASS 0
290 #define ENABLE_AUTO_NEG_FOR_DUPLX 0
291 #define DISABLE_AUTO_NEG_FOR_DUPLX (1<<2)
292 #define ENABLE_AUTO_NEG_FOR_FLOW_CTRL 0
293 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1<<3)
294 #define ADV_NO_FLOW_CTRL 0
295 #define ADV_SYMMETRIC_FLOW_CTRL (1<<4)
296 #define FORCE_FC_MODE_NO_PAUSE_DIS_TX 0
297 #define FORCE_FC_MODE_TX_PAUSE_DIS (1<<5)
298 #define FORCE_BP_MODE_NO_JAM 0
299 #define FORCE_BP_MODE_JAM_TX (1<<7)
300 #define FORCE_BP_MODE_JAM_TX_ON_RX_ERR (1<<8)
301 #define SERIAL_PORT_CONTROL_RESERVED (1<<9)
302 #define FORCE_LINK_FAIL 0
303 #define DO_NOT_FORCE_LINK_FAIL (1<<10)
304 #define RETRANSMIT_16_ATTEMPTS 0
305 #define RETRANSMIT_FOREVER (1<<11)
306 #define DISABLE_AUTO_NEG_SPEED_GMII (1<<13)
307 #define ENABLE_AUTO_NEG_SPEED_GMII 0
309 #define DTE_ADV_1 (1<<14)
310 #define DISABLE_AUTO_NEG_BYPASS 0
311 #define ENABLE_AUTO_NEG_BYPASS (1<<15)
312 #define AUTO_NEG_NO_CHANGE 0
313 #define RESTART_AUTO_NEG (1<<16)
314 #define MAX_RX_PACKET_1518BYTE 0
315 #define MAX_RX_PACKET_1522BYTE (1<<17)
316 #define MAX_RX_PACKET_1552BYTE (1<<18)
317 #define MAX_RX_PACKET_9022BYTE ((1<<18) | (1<<17))
318 #define MAX_RX_PACKET_9192BYTE (1<<19)
319 #define MAX_RX_PACKET_9700BYTE ((1<<19) | (1<<17))
320 #define SET_EXT_LOOPBACK (1<<20)
321 #define CLR_EXT_LOOPBACK 0
322 #define SET_FULL_DUPLEX_MODE (1<<21)
323 #define SET_HALF_DUPLEX_MODE 0
324 #define ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1<<22)
325 #define DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
326 #define SET_GMII_SPEED_TO_10_100 0
327 #define SET_GMII_SPEED_TO_1000 (1<<23)
328 #define SET_MII_SPEED_TO_10 0
329 #define SET_MII_SPEED_TO_100 (1<<24)
331 #define MAX_RX_PACKET_MASK (0x7<<17)
333 #define PORT_SERIAL_CONTROL_DEFAULT_VALUE \
334 DO_NOT_FORCE_LINK_PASS | \
335 ENABLE_AUTO_NEG_FOR_DUPLX | \
336 DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \
337 ADV_SYMMETRIC_FLOW_CTRL | \
338 FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
339 FORCE_BP_MODE_NO_JAM | \
340 (1<<9) /* reserved */ | \
341 DO_NOT_FORCE_LINK_FAIL | \
342 RETRANSMIT_16_ATTEMPTS | \
343 ENABLE_AUTO_NEG_SPEED_GMII | \
345 DISABLE_AUTO_NEG_BYPASS | \
346 AUTO_NEG_NO_CHANGE | \
347 MAX_RX_PACKET_9700BYTE | \
349 SET_FULL_DUPLEX_MODE | \
350 ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX
352 /* These macros describe Ethernet Serial Status reg (PSR) bits */
353 #define PORT_STATUS_MODE_10_BIT (1<<0)
354 #define PORT_STATUS_LINK_UP (1<<1)
355 #define PORT_STATUS_FULL_DUPLEX (1<<2)
356 #define PORT_STATUS_FLOW_CONTROL (1<<3)
357 #define PORT_STATUS_GMII_1000 (1<<4)
358 #define PORT_STATUS_MII_100 (1<<5)
359 /* PSR bit 6 is undocumented */
360 #define PORT_STATUS_TX_IN_PROGRESS (1<<7)
361 #define PORT_STATUS_AUTONEG_BYPASSED (1<<8)
362 #define PORT_STATUS_PARTITION (1<<9)
363 #define PORT_STATUS_TX_FIFO_EMPTY (1<<10)
364 /* PSR bits 11-31 are reserved */
366 #define PORT_DEFAULT_TRANSMIT_QUEUE_SIZE 800
367 #define PORT_DEFAULT_RECEIVE_QUEUE_SIZE 400
371 #define ETH_RX_QUEUES_ENABLED (1 << 0) /* use only Q0 for receive */
372 #define ETH_TX_QUEUES_ENABLED (1 << 0) /* use only Q0 for transmit */
374 #define ETH_INT_CAUSE_RX_DONE (ETH_RX_QUEUES_ENABLED << 2)
375 #define ETH_INT_CAUSE_RX_ERROR (ETH_RX_QUEUES_ENABLED << 9)
376 #define ETH_INT_CAUSE_RX (ETH_INT_CAUSE_RX_DONE | ETH_INT_CAUSE_RX_ERROR)
377 #define ETH_INT_CAUSE_EXT 0x00000002
378 #define ETH_INT_UNMASK_ALL (ETH_INT_CAUSE_RX | ETH_INT_CAUSE_EXT)
380 #define ETH_INT_CAUSE_TX_DONE (ETH_TX_QUEUES_ENABLED << 0)
381 #define ETH_INT_CAUSE_TX_ERROR (ETH_TX_QUEUES_ENABLED << 8)
382 #define ETH_INT_CAUSE_TX (ETH_INT_CAUSE_TX_DONE | ETH_INT_CAUSE_TX_ERROR)
383 #define ETH_INT_CAUSE_PHY 0x00010000
384 #define ETH_INT_CAUSE_STATE 0x00100000
385 #define ETH_INT_UNMASK_ALL_EXT (ETH_INT_CAUSE_TX | ETH_INT_CAUSE_PHY | \
388 #define ETH_INT_MASK_ALL 0x00000000
389 #define ETH_INT_MASK_ALL_EXT 0x00000000
391 #define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */
392 #define PHY_WAIT_MICRO_SECONDS 10
394 /* Buffer offset from buffer pointer */
395 #define RX_BUF_OFFSET 0x2
397 /* Gigabit Ethernet Unit Global Registers */
399 /* MIB Counters register definitions */
400 #define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0
401 #define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4
402 #define ETH_MIB_BAD_OCTETS_RECEIVED 0x8
403 #define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc
404 #define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10
405 #define ETH_MIB_BAD_FRAMES_RECEIVED 0x14
406 #define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18
407 #define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c
408 #define ETH_MIB_FRAMES_64_OCTETS 0x20
409 #define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24
410 #define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28
411 #define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c
412 #define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30
413 #define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34
414 #define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38
415 #define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c
416 #define ETH_MIB_GOOD_FRAMES_SENT 0x40
417 #define ETH_MIB_EXCESSIVE_COLLISION 0x44
418 #define ETH_MIB_MULTICAST_FRAMES_SENT 0x48
419 #define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c
420 #define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
421 #define ETH_MIB_FC_SENT 0x54
422 #define ETH_MIB_GOOD_FC_RECEIVED 0x58
423 #define ETH_MIB_BAD_FC_RECEIVED 0x5c
424 #define ETH_MIB_UNDERSIZE_RECEIVED 0x60
425 #define ETH_MIB_FRAGMENTS_RECEIVED 0x64
426 #define ETH_MIB_OVERSIZE_RECEIVED 0x68
427 #define ETH_MIB_JABBER_RECEIVED 0x6c
428 #define ETH_MIB_MAC_RECEIVE_ERROR 0x70
429 #define ETH_MIB_BAD_CRC_EVENT 0x74
430 #define ETH_MIB_COLLISION 0x78
431 #define ETH_MIB_LATE_COLLISION 0x7c
433 /* Port serial status reg (PSR) */
434 #define ETH_INTERFACE_PCM 0x00000001
435 #define ETH_LINK_IS_UP 0x00000002
436 #define ETH_PORT_AT_FULL_DUPLEX 0x00000004
437 #define ETH_RX_FLOW_CTRL_ENABLED 0x00000008
438 #define ETH_GMII_SPEED_1000 0x00000010
439 #define ETH_MII_SPEED_100 0x00000020
440 #define ETH_TX_IN_PROGRESS 0x00000080
441 #define ETH_BYPASS_ACTIVE 0x00000100
442 #define ETH_PORT_AT_PARTITION_STATE 0x00000200
443 #define ETH_PORT_TX_FIFO_EMPTY 0x00000400
446 #define ETH_SMI_BUSY 0x10000000 /* 0 - Write, 1 - Read */
447 #define ETH_SMI_READ_VALID 0x08000000 /* 0 - Write, 1 - Read */
448 #define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read */
449 #define ETH_SMI_OPCODE_READ 0x04000000 /* Operation is in progress */
451 /* Interrupt Cause Register Bit Definitions */
453 /* SDMA command status fields macros */
455 /* Tx & Rx descriptors status */
456 #define ETH_ERROR_SUMMARY 0x00000001
458 /* Tx & Rx descriptors command */
459 #define ETH_BUFFER_OWNED_BY_DMA 0x80000000
461 /* Tx descriptors status */
462 #define ETH_LC_ERROR 0
463 #define ETH_UR_ERROR 0x00000002
464 #define ETH_RL_ERROR 0x00000004
465 #define ETH_LLC_SNAP_FORMAT 0x00000200
467 /* Rx descriptors status */
468 #define ETH_OVERRUN_ERROR 0x00000002
469 #define ETH_MAX_FRAME_LENGTH_ERROR 0x00000004
470 #define ETH_RESOURCE_ERROR 0x00000006
471 #define ETH_VLAN_TAGGED 0x00080000
472 #define ETH_BPDU_FRAME 0x00100000
473 #define ETH_UDP_FRAME_OVER_IP_V_4 0x00200000
474 #define ETH_OTHER_FRAME_TYPE 0x00400000
475 #define ETH_LAYER_2_IS_ETH_V_2 0x00800000
476 #define ETH_FRAME_TYPE_IP_V_4 0x01000000
477 #define ETH_FRAME_HEADER_OK 0x02000000
478 #define ETH_RX_LAST_DESC 0x04000000
479 #define ETH_RX_FIRST_DESC 0x08000000
480 #define ETH_UNKNOWN_DESTINATION_ADDR 0x10000000
481 #define ETH_RX_ENABLE_INTERRUPT 0x20000000
482 #define ETH_LAYER_4_CHECKSUM_OK 0x40000000
484 /* Rx descriptors byte count */
485 #define ETH_FRAME_FRAGMENTED 0x00000004
487 /* Tx descriptors command */
488 #define ETH_LAYER_4_CHECKSUM_FIRST_DESC 0x00000400
489 #define ETH_FRAME_SET_TO_VLAN 0x00008000
490 #define ETH_UDP_FRAME 0x00010000
491 #define ETH_GEN_TCP_UDP_CHECKSUM 0x00020000
492 #define ETH_GEN_IP_V_4_CHECKSUM 0x00040000
493 #define ETH_ZERO_PADDING 0x00080000
494 #define ETH_TX_LAST_DESC 0x00100000
495 #define ETH_TX_FIRST_DESC 0x00200000
496 #define ETH_GEN_CRC 0x00400000
497 #define ETH_TX_ENABLE_INTERRUPT 0x00800000
498 #define ETH_AUTO_MODE 0x40000000
500 #define ETH_TX_IHL_SHIFT 11
504 typedef enum _eth_func_ret_status {
505 ETH_OK, /* Returned as expected. */
506 ETH_ERROR, /* Fundamental error. */
507 ETH_RETRY, /* Could not process request. Try later.*/
508 ETH_END_OF_JOB, /* Ring has nothing to process. */
509 ETH_QUEUE_FULL, /* Ring resource error. */
510 ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */
511 } ETH_FUNC_RET_STATUS;
513 typedef enum _eth_target {
521 /* These are for big-endian machines. Little endian needs different
524 #if defined(__BIG_ENDIAN)
526 u16 byte_cnt; /* Descriptor buffer byte count */
527 u16 buf_size; /* Buffer size */
528 u32 cmd_sts; /* Descriptor command status */
529 u32 next_desc_ptr; /* Next descriptor pointer */
530 u32 buf_ptr; /* Descriptor buffer pointer */
534 u16 byte_cnt; /* buffer byte count */
535 u16 l4i_chk; /* CPU provided TCP checksum */
536 u32 cmd_sts; /* Command/status field */
537 u32 next_desc_ptr; /* Pointer to next descriptor */
538 u32 buf_ptr; /* pointer to buffer for this descriptor*/
541 #elif defined(__LITTLE_ENDIAN)
543 u32 cmd_sts; /* Descriptor command status */
544 u16 buf_size; /* Buffer size */
545 u16 byte_cnt; /* Descriptor buffer byte count */
546 u32 buf_ptr; /* Descriptor buffer pointer */
547 u32 next_desc_ptr; /* Next descriptor pointer */
551 u32 cmd_sts; /* Command/status field */
552 u16 l4i_chk; /* CPU provided TCP checksum */
553 u16 byte_cnt; /* buffer byte count */
554 u32 buf_ptr; /* pointer to buffer for this descriptor*/
555 u32 next_desc_ptr; /* Pointer to next descriptor */
558 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
561 /* Unified struct for Rx and Tx operations. The user is not required to */
562 /* be familier with neither Tx nor Rx descriptors. */
564 unsigned short byte_cnt; /* Descriptor buffer byte count */
565 unsigned short l4i_chk; /* Tx CPU provided TCP Checksum */
566 unsigned int cmd_sts; /* Descriptor command status */
567 dma_addr_t buf_ptr; /* Descriptor buffer pointer */
568 struct sk_buff *return_info; /* User resource return information */
571 /* Ethernet port specific information */
573 struct mv643xx_mib_counters {
574 u64 good_octets_received;
575 u32 bad_octets_received;
576 u32 internal_mac_transmit_err;
577 u32 good_frames_received;
578 u32 bad_frames_received;
579 u32 broadcast_frames_received;
580 u32 multicast_frames_received;
581 u32 frames_64_octets;
582 u32 frames_65_to_127_octets;
583 u32 frames_128_to_255_octets;
584 u32 frames_256_to_511_octets;
585 u32 frames_512_to_1023_octets;
586 u32 frames_1024_to_max_octets;
587 u64 good_octets_sent;
588 u32 good_frames_sent;
589 u32 excessive_collision;
590 u32 multicast_frames_sent;
591 u32 broadcast_frames_sent;
592 u32 unrec_mac_control_received;
594 u32 good_fc_received;
596 u32 undersize_received;
597 u32 fragments_received;
598 u32 oversize_received;
600 u32 mac_receive_error;
606 struct mv643xx_private {
607 int port_num; /* User Ethernet port number */
609 u32 rx_sram_addr; /* Base address of rx sram area */
610 u32 rx_sram_size; /* Size of rx sram area */
611 u32 tx_sram_addr; /* Base address of tx sram area */
612 u32 tx_sram_size; /* Size of tx sram area */
614 int rx_resource_err; /* Rx ring resource error flag */
616 /* Tx/Rx rings managment indexes fields. For driver use */
618 /* Next available and first returning Rx resource */
619 int rx_curr_desc_q, rx_used_desc_q;
621 /* Next available and first returning Tx resource */
622 int tx_curr_desc_q, tx_used_desc_q;
624 #ifdef MV643XX_TX_FAST_REFILL
625 u32 tx_clean_threshold;
628 struct eth_rx_desc *p_rx_desc_area;
629 dma_addr_t rx_desc_dma;
630 int rx_desc_area_size;
631 struct sk_buff **rx_skb;
633 struct eth_tx_desc *p_tx_desc_area;
634 dma_addr_t tx_desc_dma;
635 int tx_desc_area_size;
636 struct sk_buff **tx_skb;
638 struct work_struct tx_timeout_task;
640 struct net_device *dev;
641 struct napi_struct napi;
642 struct net_device_stats stats;
643 struct mv643xx_mib_counters mib_counters;
645 /* Size of Tx Ring per queue */
647 /* Number of tx descriptors in use */
649 /* Size of Rx Ring per queue */
651 /* Number of rx descriptors in use */
655 * Used in case RX Ring is empty, which can be caused when
656 * system does not have resources (skb's)
658 struct timer_list timeout;
662 struct mii_if_info mii;
665 /* Port operation control routines */
666 static void eth_port_init(struct mv643xx_private *mp);
667 static void eth_port_reset(unsigned int eth_port_num);
668 static void eth_port_start(struct net_device *dev);
670 /* PHY and MIB routines */
671 static void ethernet_phy_reset(unsigned int eth_port_num);
673 static void eth_port_write_smi_reg(unsigned int eth_port_num,
674 unsigned int phy_reg, unsigned int value);
676 static void eth_port_read_smi_reg(unsigned int eth_port_num,
677 unsigned int phy_reg, unsigned int *value);
679 static void eth_clear_mib_counters(unsigned int eth_port_num);
681 /* Port data flow control routines */
682 static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
683 struct pkt_info *p_pkt_info);
684 static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
685 struct pkt_info *p_pkt_info);
687 #endif /* __MV643XX_ETH_H__ */
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