2 * Copyright (C) 2003 - 2006 NetXen, Inc.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
23 * Contact Information:
26 * 3965 Freedom Circle, Fourth floor,
27 * Santa Clara, CA 95054
30 #ifndef _NETXEN_NIC_H_
31 #define _NETXEN_NIC_H_
33 #include <linux/module.h>
34 #include <linux/kernel.h>
35 #include <linux/types.h>
36 #include <linux/compiler.h>
37 #include <linux/slab.h>
38 #include <linux/delay.h>
39 #include <linux/init.h>
40 #include <linux/ioport.h>
41 #include <linux/pci.h>
42 #include <linux/netdevice.h>
43 #include <linux/etherdevice.h>
46 #include <linux/tcp.h>
47 #include <linux/skbuff.h>
48 #include <linux/version.h>
50 #include <linux/ethtool.h>
51 #include <linux/mii.h>
52 #include <linux/interrupt.h>
53 #include <linux/timer.h>
56 #include <linux/mman.h>
58 #include <asm/system.h>
60 #include <asm/byteorder.h>
61 #include <asm/uaccess.h>
62 #include <asm/pgtable.h>
64 #include "netxen_nic_hw.h"
66 #define NETXEN_NIC_BUILD_NO "232"
67 #define _NETXEN_NIC_LINUX_MAJOR 2
68 #define _NETXEN_NIC_LINUX_MINOR 3
69 #define _NETXEN_NIC_LINUX_SUBVERSION 57
70 #define NETXEN_NIC_LINUX_VERSIONID "2.3.57"
71 #define NETXEN_NIC_FW_VERSIONID "2.3.57"
73 #define RCV_DESC_RINGSIZE \
74 (sizeof(struct rcv_desc) * adapter->max_rx_desc_count)
75 #define STATUS_DESC_RINGSIZE \
76 (sizeof(struct status_desc)* adapter->max_rx_desc_count)
78 (sizeof(struct netxen_cmd_buffer) * adapter->max_tx_desc_count)
79 #define RCV_BUFFSIZE \
80 (sizeof(struct netxen_rx_buffer) * rcv_desc->max_rx_desc_count)
81 #define find_diff_among(a,b,range) ((a)<(b)?((b)-(a)):((b)+(range)-(a)))
83 #define NETXEN_NETDEV_STATUS 0x1
85 #define ADDR_IN_WINDOW1(off) \
86 ((off > NETXEN_CRB_PCIX_HOST2) && (off < NETXEN_CRB_MAX)) ? 1 : 0
89 * normalize a 64MB crb address to 32MB PCI window
90 * To use NETXEN_CRB_NORMALIZE, window _must_ be set to 1
92 #define NETXEN_CRB_NORMALIZE(adapter, reg) \
93 ((adapter)->ahw.pci_base + (reg) \
94 - NETXEN_CRB_PCIX_HOST2 + NETXEN_CRB_PCIX_HOST)
96 #define MAX_RX_BUFFER_LENGTH 2000
97 #define MAX_RX_JUMBO_BUFFER_LENGTH 9046
98 #define RX_DMA_MAP_LEN (MAX_RX_BUFFER_LENGTH - NET_IP_ALIGN)
99 #define RX_JUMBO_DMA_MAP_LEN \
100 (MAX_RX_JUMBO_BUFFER_LENGTH - NET_IP_ALIGN)
101 #define NETXEN_ROM_ROUNDUP 0x80000000ULL
104 * Maximum number of ring contexts
106 #define MAX_RING_CTX 1
108 /* Opcodes to be used with the commands */
111 /* The following opcodes are for IP checksum */
120 /* The following opcodes are for internal consumption. */
121 #define NETXEN_CONTROL_OP 0x10
122 #define PEGNET_REQUEST 0x11
124 #define MAX_NUM_CARDS 4
126 #define MAX_BUFFERS_PER_CMD 32
129 * Following are the states of the Phantom. Phantom will set them and
130 * Host will read to check if the fields are correct.
132 #define PHAN_INITIALIZE_START 0xff00
133 #define PHAN_INITIALIZE_FAILED 0xffff
134 #define PHAN_INITIALIZE_COMPLETE 0xff01
136 /* Host writes the following to notify that it has done the init-handshake */
137 #define PHAN_INITIALIZE_ACK 0xf00f
139 #define NUM_RCV_DESC_RINGS 2 /* No of Rcv Descriptor contexts */
141 /* descriptor types */
142 #define RCV_DESC_NORMAL 0x01
143 #define RCV_DESC_JUMBO 0x02
144 #define RCV_DESC_NORMAL_CTXID 0
145 #define RCV_DESC_JUMBO_CTXID 1
147 #define RCV_DESC_TYPE(ID) \
148 ((ID == RCV_DESC_JUMBO_CTXID) ? RCV_DESC_JUMBO : RCV_DESC_NORMAL)
150 #define MAX_CMD_DESCRIPTORS 1024
151 #define MAX_RCV_DESCRIPTORS 32768
152 #define MAX_JUMBO_RCV_DESCRIPTORS 1024
153 #define MAX_RCVSTATUS_DESCRIPTORS MAX_RCV_DESCRIPTORS
154 #define MAX_JUMBO_RCV_DESC MAX_JUMBO_RCV_DESCRIPTORS
155 #define MAX_RCV_DESC MAX_RCV_DESCRIPTORS
156 #define MAX_RCVSTATUS_DESC MAX_RCV_DESCRIPTORS
157 #define NUM_RCV_DESC (MAX_RCV_DESC + MAX_JUMBO_RCV_DESCRIPTORS)
158 #define MAX_EPG_DESCRIPTORS (MAX_CMD_DESCRIPTORS * 8)
160 #define MIN_TX_COUNT 4096
161 #define MIN_RX_COUNT 4096
163 #define MAX_FRAME_SIZE 0x10000 /* 64K MAX size for LSO */
165 #define PHAN_PEG_RCV_INITIALIZED 0xff01
166 #define PHAN_PEG_RCV_START_INITIALIZE 0xff00
168 #define get_next_index(index, length) \
169 (((index) + 1) & ((length) - 1))
171 #define get_index_range(index,length,count) \
172 (((index) + (count)) & ((length) - 1))
175 * Following data structures describe the descriptors that will be used.
176 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
177 * we are doing LSO (above the 1500 size packet) only.
181 * The size of reference handle been changed to 16 bits to pass the MSS fields
185 #define FLAGS_CHECKSUM_ENABLED 0x01
186 #define FLAGS_LSO_ENABLED 0x02
187 #define FLAGS_IPSEC_SA_ADD 0x04
188 #define FLAGS_IPSEC_SA_DELETE 0x08
189 #define FLAGS_VLAN_TAGGED 0x10
191 #define CMD_DESC_TOTAL_LENGTH(cmd_desc) \
192 ((cmd_desc)->length_tcp_hdr & 0x00FFFFFF)
193 #define CMD_DESC_TCP_HDR_OFFSET(cmd_desc) \
194 (((cmd_desc)->length_tcp_hdr >> 24) & 0x0FF)
195 #define CMD_DESC_PORT(cmd_desc) ((cmd_desc)->port_ctxid & 0x0F)
196 #define CMD_DESC_CTX_ID(cmd_desc) (((cmd_desc)->port_ctxid >> 4) & 0x0F)
198 #define CMD_DESC_TOTAL_LENGTH_WRT(cmd_desc, var) \
199 ((cmd_desc)->length_tcp_hdr |= ((var) & 0x00FFFFFF))
200 #define CMD_DESC_TCP_HDR_OFFSET_WRT(cmd_desc, var) \
201 ((cmd_desc)->length_tcp_hdr |= (((var) << 24) & 0xFF000000))
202 #define CMD_DESC_PORT_WRT(cmd_desc, var) \
203 ((cmd_desc)->port_ctxid |= ((var) & 0x0F))
205 struct cmd_desc_type0 {
206 u64 netxen_next; /* for fragments handled by Phantom */
215 /* Bit pattern: 0-23 total length, 24-32 tcp header offset */
217 u8 ip_hdr_offset; /* For LSO only */
218 u8 num_of_buffers; /* total number of segments */
219 u8 flags; /* as defined above */
222 u16 reference_handle; /* changed to u16 to add mss */
223 u16 mss; /* passed by NDIS_PACKET for LSO */
224 /* Bit pattern 0-3 port, 0-3 ctx id */
226 u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */
227 u16 conn_id; /* IPSec offoad only */
258 } __attribute__ ((aligned(64)));
260 /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
262 u16 reference_handle;
264 u32 buffer_length; /* allocated buffer length (usually 2K) */
268 /* opcode field in status_desc */
269 #define RCV_NIC_PKT (0xA)
270 #define STATUS_NIC_PKT ((RCV_NIC_PKT) << 12)
272 /* for status field in status_desc */
273 #define STATUS_NEED_CKSUM (1)
274 #define STATUS_CKSUM_OK (2)
276 /* owner bits of status_desc */
277 #define STATUS_OWNER_HOST (0x1)
278 #define STATUS_OWNER_PHANTOM (0x2)
280 #define NETXEN_PROT_IP (1)
281 #define NETXEN_PROT_UNKNOWN (0)
283 /* Note: sizeof(status_desc) should always be a mutliple of 2 */
284 #define STATUS_DESC_PORT(status_desc) \
285 ((status_desc)->port_status_type_op & 0x0F)
286 #define STATUS_DESC_STATUS(status_desc) \
287 (((status_desc)->port_status_type_op >> 4) & 0x0F)
288 #define STATUS_DESC_TYPE(status_desc) \
289 (((status_desc)->port_status_type_op >> 8) & 0x0F)
290 #define STATUS_DESC_OPCODE(status_desc) \
291 (((status_desc)->port_status_type_op >> 12) & 0x0F)
294 /* Bit pattern: 0-3 port, 4-7 status, 8-11 type, 12-15 opcode */
295 u16 port_status_type_op;
296 u16 total_length; /* NIC mode */
297 u16 reference_handle; /* handle for the associated packet */
298 /* Bit pattern: 0-1 owner, 2-5 protocol */
299 u16 owner; /* Owner of the descriptor */
300 } __attribute__ ((aligned(8)));
303 NETXEN_RCV_PEG_0 = 0,
306 /* The version of the main data structure */
307 #define NETXEN_BDINFO_VERSION 1
309 /* Magic number to let user know flash is programmed */
310 #define NETXEN_BDINFO_MAGIC 0x12345678
312 /* Max number of Gig ports on a Phantom board */
313 #define NETXEN_MAX_PORTS 4
316 NETXEN_BRDTYPE_P1_BD = 0x0000,
317 NETXEN_BRDTYPE_P1_SB = 0x0001,
318 NETXEN_BRDTYPE_P1_SMAX = 0x0002,
319 NETXEN_BRDTYPE_P1_SOCK = 0x0003,
321 NETXEN_BRDTYPE_P2_SOCK_31 = 0x0008,
322 NETXEN_BRDTYPE_P2_SOCK_35 = 0x0009,
323 NETXEN_BRDTYPE_P2_SB35_4G = 0x000a,
324 NETXEN_BRDTYPE_P2_SB31_10G = 0x000b,
325 NETXEN_BRDTYPE_P2_SB31_2G = 0x000c,
327 NETXEN_BRDTYPE_P2_SB31_10G_IMEZ = 0x000d,
328 NETXEN_BRDTYPE_P2_SB31_10G_HMEZ = 0x000e,
329 NETXEN_BRDTYPE_P2_SB31_10G_CX4 = 0x000f
333 NETXEN_BRDMFG_INVENTEC = 1
337 MEM_ORG_128Mbx4 = 0x0, /* DDR1 only */
338 MEM_ORG_128Mbx8 = 0x1, /* DDR1 only */
339 MEM_ORG_128Mbx16 = 0x2, /* DDR1 only */
340 MEM_ORG_256Mbx4 = 0x3,
341 MEM_ORG_256Mbx8 = 0x4,
342 MEM_ORG_256Mbx16 = 0x5,
343 MEM_ORG_512Mbx4 = 0x6,
344 MEM_ORG_512Mbx8 = 0x7,
345 MEM_ORG_512Mbx16 = 0x8,
348 MEM_ORG_1Gbx16 = 0xb,
351 MEM_ORG_2Gbx16 = 0xe,
352 MEM_ORG_128Mbx32 = 0x10002, /* GDDR only */
353 MEM_ORG_256Mbx32 = 0x10005 /* GDDR only */
354 } netxen_mn_mem_org_t;
357 MEM_ORG_512Kx36 = 0x0,
360 } netxen_sn_mem_org_t;
365 MEM_DEPTH_16MB = 0x3,
366 MEM_DEPTH_32MB = 0x4,
367 MEM_DEPTH_64MB = 0x5,
368 MEM_DEPTH_128MB = 0x6,
369 MEM_DEPTH_256MB = 0x7,
370 MEM_DEPTH_512MB = 0x8,
375 MEM_DEPTH_16GB = 0xd,
377 } netxen_mem_depth_t;
379 struct netxen_board_info {
391 u32 port_mask; /* available niu ports */
392 u32 peg_mask; /* available pegs */
393 u32 icache_ok; /* can we run with icache? */
394 u32 dcache_ok; /* can we run with dcache? */
402 /* MN-related config */
403 u32 mn_sync_mode; /* enable/ sync shift cclk/ sync shift mclk */
404 u32 mn_sync_shift_cclk;
405 u32 mn_sync_shift_mclk;
407 u32 mn_crystal_freq; /* in MHz */
408 u32 mn_speed; /* in MHz */
411 u32 mn_ranks_0; /* ranks per slot */
412 u32 mn_ranks_1; /* ranks per slot */
423 u32 mn_mode_reg; /* MIU DDR Mode Register */
424 u32 mn_ext_mode_reg; /* MIU DDR Extended Mode Register */
425 u32 mn_timing_0; /* MIU Memory Control Timing Rgister */
426 u32 mn_timing_1; /* MIU Extended Memory Ctrl Timing Register */
427 u32 mn_timing_2; /* MIU Extended Memory Ctrl Timing2 Register */
429 /* SN-related config */
430 u32 sn_sync_mode; /* enable/ sync shift cclk / sync shift mclk */
431 u32 sn_pt_mode; /* pass through mode */
446 u32 magic; /* indicates flash has been initialized */
453 #define FLASH_NUM_PORTS (4)
455 struct netxen_flash_mac_addr {
459 struct netxen_user_old_info {
471 /* primary image status */
473 u32 secondary_present;
475 /* MAC address , 4 ports */
476 struct netxen_flash_mac_addr mac_addr[FLASH_NUM_PORTS];
478 #define FLASH_NUM_MAC_PER_PORT 32
479 struct netxen_user_info {
480 u8 flash_md5[16 * 64];
487 /* primary image status */
489 u32 secondary_present;
491 /* MAC address , 4 ports, 32 address per port */
492 u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
496 /* Any user defined data */
500 * Flash Layout - new format.
502 struct netxen_new_user_info {
503 u8 flash_md5[16 * 64];
510 /* primary image status */
512 u32 secondary_present;
514 /* MAC address , 4 ports, 32 address per port */
515 u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
519 /* Any user defined data */
522 #define SECONDARY_IMAGE_PRESENT 0xb3b4b5b6
523 #define SECONDARY_IMAGE_ABSENT 0xffffffff
524 #define PRIMARY_IMAGE_GOOD 0x5a5a5a5a
525 #define PRIMARY_IMAGE_BAD 0xffffffff
527 /* Flash memory map */
529 CRBINIT_START = 0, /* Crbinit section */
530 BRDCFG_START = 0x4000, /* board config */
531 INITCODE_START = 0x6000, /* pegtune code */
532 BOOTLD_START = 0x10000, /* bootld */
533 IMAGE_START = 0x43000, /* compressed image */
534 SECONDARY_START = 0x200000, /* backup images */
535 PXE_START = 0x3E0000, /* user defined region */
536 USER_START = 0x3E8000, /* User defined region for new boards */
537 FIXED_START = 0x3F0000 /* backup of crbinit */
538 } netxen_flash_map_t;
540 #define USER_START_OLD PXE_START /* for backward compatibility */
542 #define FLASH_START (CRBINIT_START)
543 #define INIT_SECTOR (0)
544 #define PRIMARY_START (BOOTLD_START)
545 #define FLASH_CRBINIT_SIZE (0x4000)
546 #define FLASH_BRDCFG_SIZE (sizeof(struct netxen_board_info))
547 #define FLASH_USER_SIZE (sizeof(netxen_user_info)/sizeof(u32))
548 #define FLASH_SECONDARY_SIZE (USER_START-SECONDARY_START)
549 #define NUM_PRIMARY_SECTORS (0x20)
550 #define NUM_CONFIG_SECTORS (1)
551 #define PFX "netxen: "
553 /* Note: Make sure to not call this before adapter->port is valid */
554 #if !defined(NETXEN_DEBUG)
555 #define DPRINTK(klevel, fmt, args...) do { \
558 #define DPRINTK(klevel, fmt, args...) do { \
559 printk(KERN_##klevel PFX "%s: %s: " fmt, __FUNCTION__,\
560 (adapter != NULL && adapter->port != NULL && \
561 adapter->port[0] != NULL && \
562 adapter->port[0]->netdev != NULL) ? \
563 adapter->port[0]->netdev->name : NULL, \
567 /* Number of status descriptors to handle per interrupt */
568 #define MAX_STATUS_HANDLE (128)
571 * netxen_skb_frag{} is to contain mapping info for each SG list. This
572 * has to be freed when DMA is complete. This is part of netxen_tx_buffer{}.
574 struct netxen_skb_frag {
579 /* Following defines are for the state of the buffers */
580 #define NETXEN_BUFFER_FREE 0
581 #define NETXEN_BUFFER_BUSY 1
584 * There will be one netxen_buffer per skb packet. These will be
585 * used to save the dma info for pci_unmap_page()
587 struct netxen_cmd_buffer {
589 struct netxen_skb_frag frag_array[MAX_BUFFERS_PER_CMD + 1];
595 unsigned long time_stamp;
597 u32 no_of_descriptors;
600 /* In rx_buffer, we do not need multiple fragments as is a single buffer */
601 struct netxen_rx_buffer {
609 #define NETXEN_NIC_GBE 0x01
610 #define NETXEN_NIC_XGBE 0x02
613 * One hardware_context{} per adapter
614 * contains interrupt info as well shared hardware info.
616 struct netxen_hardware_context {
617 struct pci_dev *pdev;
618 void __iomem *pci_base; /* base of mapped phantom memory */
622 struct netxen_board_info boardcfg;
624 /* Address of cmd ring in Phantom */
625 struct cmd_desc_type0 *cmd_desc_head;
626 dma_addr_t cmd_desc_phys_addr;
627 struct netxen_adapter *adapter;
630 #define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */
631 #define ETHERNET_FCS_SIZE 4
633 struct netxen_adapter_stats {
648 * Rcv Descriptor Context. One such per Rcv Descriptor. There may
649 * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
651 struct netxen_rcv_desc_ctx {
654 u32 rcv_pending; /* Num of bufs posted in phantom */
655 u32 rcv_free; /* Num of bufs in free list */
656 dma_addr_t phys_addr;
657 struct rcv_desc *desc_head; /* address of rx ring in Phantom */
658 u32 max_rx_desc_count;
661 struct netxen_rx_buffer *rx_buf_arr; /* rx buffers for receive */
666 * Receive context. There is one such structure per instance of the
667 * receive processing. Any state information that is relevant to
668 * the receive, and is must be in this structure. The global data may be
671 struct netxen_recv_context {
672 struct netxen_rcv_desc_ctx rcv_desc[NUM_RCV_DESC_RINGS];
673 u32 status_rx_producer;
674 u32 status_rx_consumer;
675 dma_addr_t rcv_status_desc_phys_addr;
676 struct status_desc *rcv_status_desc_head;
679 #define NETXEN_NIC_MSI_ENABLED 0x02
681 struct netxen_drvops;
683 struct netxen_adapter {
684 struct netxen_hardware_context ahw;
685 int port_count; /* Number of configured ports */
686 int active_ports; /* Number of open ports */
687 struct netxen_port *port[NETXEN_MAX_PORTS]; /* ptr to each port */
690 struct work_struct watchdog_task;
691 struct work_struct tx_timeout_task;
692 struct timer_list watchdog_timer;
699 u32 last_cmd_consumer;
700 u32 max_tx_desc_count;
701 u32 max_rx_desc_count;
702 u32 max_jumbo_rx_desc_count;
703 /* Num of instances active on cmd buffer ring */
704 u32 proc_cmd_buf_counter;
706 u32 num_threads, total_threads; /*Use to keep track of xmit threads */
712 struct netxen_adapter_stats stats;
714 struct netxen_cmd_buffer *cmd_buf_arr; /* Command buffers for xmit */
717 * Receive instances. These can be either one per port,
718 * or one per peg, etc.
720 struct netxen_recv_context recv_ctx[MAX_RCV_CTX];
724 struct netxen_drvops *ops;
725 }; /* netxen_adapter structure */
727 /* Max number of xmit producer threads that can run simultaneously */
728 #define MAX_XMIT_PRODUCERS 16
730 struct netxen_port_stats {
754 struct netxen_adapter *adapter;
756 u16 portnum; /* GBE port number */
763 struct net_device *netdev;
764 struct pci_dev *pdev;
765 struct net_device_stats net_stats;
766 struct netxen_port_stats stats;
769 struct netxen_drvops {
770 int (*enable_phy_interrupts) (struct netxen_adapter *, int);
771 int (*disable_phy_interrupts) (struct netxen_adapter *, int);
772 void (*handle_phy_intr) (struct netxen_adapter *);
773 int (*macaddr_set) (struct netxen_port *, netxen_ethernet_macaddr_t);
774 int (*set_mtu) (struct netxen_port *, int);
775 int (*set_promisc) (struct netxen_adapter *, int,
776 netxen_niu_prom_mode_t);
777 int (*unset_promisc) (struct netxen_adapter *, int,
778 netxen_niu_prom_mode_t);
779 int (*phy_read) (struct netxen_adapter *, long phy, long reg, u32 *);
780 int (*phy_write) (struct netxen_adapter *, long phy, long reg, u32 val);
781 int (*init_port) (struct netxen_adapter *, int);
782 void (*init_niu) (struct netxen_adapter *);
783 int (*stop_port) (struct netxen_adapter *, int);
786 extern char netxen_nic_driver_name[];
788 int netxen_niu_xgbe_enable_phy_interrupts(struct netxen_adapter *adapter,
790 int netxen_niu_gbe_enable_phy_interrupts(struct netxen_adapter *adapter,
792 int netxen_niu_xgbe_disable_phy_interrupts(struct netxen_adapter *adapter,
794 int netxen_niu_gbe_disable_phy_interrupts(struct netxen_adapter *adapter,
796 int netxen_niu_xgbe_clear_phy_interrupts(struct netxen_adapter *adapter,
798 int netxen_niu_gbe_clear_phy_interrupts(struct netxen_adapter *adapter,
800 void netxen_nic_xgbe_handle_phy_intr(struct netxen_adapter *adapter);
801 void netxen_nic_gbe_handle_phy_intr(struct netxen_adapter *adapter);
802 void netxen_niu_gbe_set_mii_mode(struct netxen_adapter *adapter, int port,
804 void netxen_niu_gbe_set_gmii_mode(struct netxen_adapter *adapter, int port,
806 int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long phy, long reg,
808 int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter, long phy,
809 long reg, __le32 val);
811 /* Functions available from netxen_nic_hw.c */
812 int netxen_niu_xginit(struct netxen_adapter *);
813 int netxen_nic_set_mtu_xgb(struct netxen_port *port, int new_mtu);
814 int netxen_nic_set_mtu_gb(struct netxen_port *port, int new_mtu);
815 void netxen_nic_init_niu_gb(struct netxen_adapter *adapter);
816 void netxen_nic_pci_change_crbwindow(struct netxen_adapter *adapter, u32 wndw);
817 void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val);
818 int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off);
819 void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value);
820 void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 * value);
822 int netxen_nic_get_board_info(struct netxen_adapter *adapter);
823 int netxen_nic_hw_read_wx(struct netxen_adapter *adapter, u64 off, void *data,
825 int netxen_nic_hw_write_wx(struct netxen_adapter *adapter, u64 off, void *data,
827 void netxen_crb_writelit_adapter(struct netxen_adapter *adapter,
828 unsigned long off, int data);
830 /* Functions from netxen_nic_init.c */
831 void netxen_phantom_init(struct netxen_adapter *adapter);
832 void netxen_load_firmware(struct netxen_adapter *adapter);
833 int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose);
834 int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp);
836 /* Functions from netxen_nic_isr.c */
837 void netxen_nic_isr_other(struct netxen_adapter *adapter);
838 void netxen_indicate_link_status(struct netxen_adapter *adapter, u32 port,
840 void netxen_handle_port_int(struct netxen_adapter *adapter, u32 port,
842 void netxen_nic_stop_all_ports(struct netxen_adapter *adapter);
843 void netxen_initialize_adapter_sw(struct netxen_adapter *adapter);
844 void netxen_initialize_adapter_hw(struct netxen_adapter *adapter);
845 void netxen_initialize_adapter_ops(struct netxen_adapter *adapter);
846 int netxen_init_firmware(struct netxen_adapter *adapter);
847 void netxen_free_hw_resources(struct netxen_adapter *adapter);
848 void netxen_tso_check(struct netxen_adapter *adapter,
849 struct cmd_desc_type0 *desc, struct sk_buff *skb);
850 int netxen_nic_hw_resources(struct netxen_adapter *adapter);
851 void netxen_nic_clear_stats(struct netxen_adapter *adapter);
853 netxen_nic_do_ioctl(struct netxen_adapter *adapter, void *u_data,
854 struct netxen_port *port);
855 int netxen_nic_rx_has_work(struct netxen_adapter *adapter);
856 int netxen_nic_tx_has_work(struct netxen_adapter *adapter);
857 void netxen_watchdog_task(unsigned long v);
858 void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ctx,
860 void netxen_process_cmd_ring(unsigned long data);
861 u32 netxen_process_rcv_ring(struct netxen_adapter *adapter, int ctx, int max);
862 void netxen_nic_set_multi(struct net_device *netdev);
863 int netxen_nic_change_mtu(struct net_device *netdev, int new_mtu);
864 int netxen_nic_set_mac(struct net_device *netdev, void *p);
865 struct net_device_stats *netxen_nic_get_stats(struct net_device *netdev);
867 static inline void netxen_nic_disable_int(struct netxen_adapter *adapter)
870 * ISR_INT_MASK: Can be read from window 0 or 1.
872 writel(0x7ff, (void __iomem *)(adapter->ahw.pci_base + ISR_INT_MASK));
875 static inline void netxen_nic_enable_int(struct netxen_adapter *adapter)
879 switch (adapter->ahw.board_type) {
883 case NETXEN_NIC_XGBE:
891 writel(mask, (void __iomem *)(adapter->ahw.pci_base + ISR_INT_MASK));
893 if (!(adapter->flags & NETXEN_NIC_MSI_ENABLED)) {
895 writel(mask, (void __iomem *)
896 (adapter->ahw.pci_base + ISR_INT_TARGET_MASK));
900 int netxen_is_flash_supported(struct netxen_adapter *adapter);
901 int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, u64 mac[]);
903 extern void netxen_change_ringparam(struct netxen_adapter *adapter);
904 extern int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr,
907 extern struct ethtool_ops netxen_nic_ethtool_ops;
909 #endif /* __NETXEN_NIC_H_ */