git.rot13.org Git - linux/blob - drivers/net/phy/dp83867.c

   1 /*
   2  * Driver for the Texas Instruments DP83867 PHY
   3  *
   4  * Copyright (C) 2015 Texas Instruments Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/ethtool.h>
  17 #include <linux/kernel.h>
  18 #include <linux/mii.h>
  19 #include <linux/module.h>
  20 #include <linux/of.h>
  21 #include <linux/phy.h>
  22
  23 #include <dt-bindings/net/ti-dp83867.h>
  24
  25 #define DP83867_PHY_ID          0x2000a231
  26 #define DP83867_DEVADDR         0x1f
  27
  28 #define MII_DP83867_PHYCTRL     0x10
  29 #define MII_DP83867_MICR        0x12
  30 #define MII_DP83867_ISR         0x13
  31 #define DP83867_CTRL            0x1f
  32 #define DP83867_CFG3            0x1e
  33
  34 /* Extended Registers */
  35 #define DP83867_CFG4            0x0031
  36 #define DP83867_RGMIICTL        0x0032
  37 #define DP83867_STRAP_STS1      0x006E
  38 #define DP83867_RGMIIDCTL       0x0086
  39 #define DP83867_IO_MUX_CFG      0x0170
  40
  41 #define DP83867_SW_RESET        BIT(15)
  42 #define DP83867_SW_RESTART      BIT(14)
  43
  44 /* MICR Interrupt bits */
  45 #define MII_DP83867_MICR_AN_ERR_INT_EN          BIT(15)
  46 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN      BIT(14)
  47 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN   BIT(13)
  48 #define MII_DP83867_MICR_PAGE_RXD_INT_EN        BIT(12)
  49 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN    BIT(11)
  50 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN   BIT(10)
  51 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN   BIT(8)
  52 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
  53 #define MII_DP83867_MICR_WOL_INT_EN             BIT(3)
  54 #define MII_DP83867_MICR_XGMII_ERR_INT_EN       BIT(2)
  55 #define MII_DP83867_MICR_POL_CHNG_INT_EN        BIT(1)
  56 #define MII_DP83867_MICR_JABBER_INT_EN          BIT(0)
  57
  58 /* RGMIICTL bits */
  59 #define DP83867_RGMII_TX_CLK_DELAY_EN           BIT(1)
  60 #define DP83867_RGMII_RX_CLK_DELAY_EN           BIT(0)
  61
  62 /* STRAP_STS1 bits */
  63 #define DP83867_STRAP_STS1_RESERVED             BIT(11)
  64
  65 /* PHY CTRL bits */
  66 #define DP83867_PHYCR_FIFO_DEPTH_SHIFT          14
  67 #define DP83867_PHYCR_FIFO_DEPTH_MASK           (3 << 14)
  68 #define DP83867_PHYCR_RESERVED_MASK             BIT(11)
  69
  70 /* RGMIIDCTL bits */
  71 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT        4
  72
  73 /* IO_MUX_CFG bits */
  74 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL    0x1f
  75
  76 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX     0x0
  77 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN     0x1f
  78 #define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK       (0x1f << 8)
  79 #define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT      8
  80
  81 /* CFG4 bits */
  82 #define DP83867_CFG4_PORT_MIRROR_EN              BIT(0)
  83
  84 enum {
  85         DP83867_PORT_MIRROING_KEEP,
  86         DP83867_PORT_MIRROING_EN,
  87         DP83867_PORT_MIRROING_DIS,
  88 };
  89
  90 struct dp83867_private {
  91         int rx_id_delay;
  92         int tx_id_delay;
  93         int fifo_depth;
  94         int io_impedance;
  95         int port_mirroring;
  96         bool rxctrl_strap_quirk;
  97         int clk_output_sel;
  98 };
  99
 100 static int dp83867_ack_interrupt(struct phy_device *phydev)
 101 {
 102         int err = phy_read(phydev, MII_DP83867_ISR);
 103
 104         if (err < 0)
 105                 return err;
 106
 107         return 0;
 108 }
 109
 110 static int dp83867_config_intr(struct phy_device *phydev)
 111 {
 112         int micr_status;
 113
 114         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
 115                 micr_status = phy_read(phydev, MII_DP83867_MICR);
 116                 if (micr_status < 0)
 117                         return micr_status;
 118
 119                 micr_status |=
 120                         (MII_DP83867_MICR_AN_ERR_INT_EN |
 121                         MII_DP83867_MICR_SPEED_CHNG_INT_EN |
 122                         MII_DP83867_MICR_AUTONEG_COMP_INT_EN |
 123                         MII_DP83867_MICR_LINK_STS_CHNG_INT_EN |
 124                         MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN |
 125                         MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN);
 126
 127                 return phy_write(phydev, MII_DP83867_MICR, micr_status);
 128         }
 129
 130         micr_status = 0x0;
 131         return phy_write(phydev, MII_DP83867_MICR, micr_status);
 132 }
 133
 134 static int dp83867_config_port_mirroring(struct phy_device *phydev)
 135 {
 136         struct dp83867_private *dp83867 =
 137                 (struct dp83867_private *)phydev->priv;
 138         u16 val;
 139
 140         val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4);
 141
 142         if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN)
 143                 val |= DP83867_CFG4_PORT_MIRROR_EN;
 144         else
 145                 val &= ~DP83867_CFG4_PORT_MIRROR_EN;
 146
 147         phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val);
 148
 149         return 0;
 150 }
 151
 152 #ifdef CONFIG_OF_MDIO
 153 static int dp83867_of_init(struct phy_device *phydev)
 154 {
 155         struct dp83867_private *dp83867 = phydev->priv;
 156         struct device *dev = &phydev->mdio.dev;
 157         struct device_node *of_node = dev->of_node;
 158         int ret;
 159
 160         if (!of_node)
 161                 return -ENODEV;
 162
 163         dp83867->io_impedance = -EINVAL;
 164
 165         /* Optional configuration */
 166         ret = of_property_read_u32(of_node, "ti,clk-output-sel",
 167                                    &dp83867->clk_output_sel);
 168         if (ret || dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK)
 169                 /* Keep the default value if ti,clk-output-sel is not set
 170                  * or too high
 171                  */
 172                 dp83867->clk_output_sel = DP83867_CLK_O_SEL_REF_CLK;
 173
 174         if (of_property_read_bool(of_node, "ti,max-output-impedance"))
 175                 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
 176         else if (of_property_read_bool(of_node, "ti,min-output-impedance"))
 177                 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
 178
 179         dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node,
 180                                         "ti,dp83867-rxctrl-strap-quirk");
 181
 182         ret = of_property_read_u32(of_node, "ti,rx-internal-delay",
 183                                    &dp83867->rx_id_delay);
 184         if (ret &&
 185             (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
 186              phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID))
 187                 return ret;
 188
 189         ret = of_property_read_u32(of_node, "ti,tx-internal-delay",
 190                                    &dp83867->tx_id_delay);
 191         if (ret &&
 192             (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
 193              phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID))
 194                 return ret;
 195
 196         if (of_property_read_bool(of_node, "enet-phy-lane-swap"))
 197                 dp83867->port_mirroring = DP83867_PORT_MIRROING_EN;
 198
 199         if (of_property_read_bool(of_node, "enet-phy-lane-no-swap"))
 200                 dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS;
 201
 202         return of_property_read_u32(of_node, "ti,fifo-depth",
 203                                    &dp83867->fifo_depth);
 204 }
 205 #else
 206 static int dp83867_of_init(struct phy_device *phydev)
 207 {
 208         return 0;
 209 }
 210 #endif /* CONFIG_OF_MDIO */
 211
 212 static int dp83867_config_init(struct phy_device *phydev)
 213 {
 214         struct dp83867_private *dp83867;
 215         int ret, val, bs;
 216         u16 delay;
 217
 218         if (!phydev->priv) {
 219                 dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867),
 220                                        GFP_KERNEL);
 221                 if (!dp83867)
 222                         return -ENOMEM;
 223
 224                 phydev->priv = dp83867;
 225                 ret = dp83867_of_init(phydev);
 226                 if (ret)
 227                         return ret;
 228         } else {
 229                 dp83867 = (struct dp83867_private *)phydev->priv;
 230         }
 231
 232         /* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */
 233         if (dp83867->rxctrl_strap_quirk) {
 234                 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4);
 235                 val &= ~BIT(7);
 236                 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val);
 237         }
 238
 239         if (phy_interface_is_rgmii(phydev)) {
 240                 val = phy_read(phydev, MII_DP83867_PHYCTRL);
 241                 if (val < 0)
 242                         return val;
 243                 val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK;
 244                 val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT);
 245
 246                 /* The code below checks if "port mirroring" N/A MODE4 has been
 247                  * enabled during power on bootstrap.
 248                  *
 249                  * Such N/A mode enabled by mistake can put PHY IC in some
 250                  * internal testing mode and disable RGMII transmission.
 251                  *
 252                  * In this particular case one needs to check STRAP_STS1
 253                  * register's bit 11 (marked as RESERVED).
 254                  */
 255
 256                 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1);
 257                 if (bs & DP83867_STRAP_STS1_RESERVED)
 258                         val &= ~DP83867_PHYCR_RESERVED_MASK;
 259
 260                 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
 261                 if (ret)
 262                         return ret;
 263         }
 264
 265         if ((phydev->interface >= PHY_INTERFACE_MODE_RGMII_ID) &&
 266             (phydev->interface <= PHY_INTERFACE_MODE_RGMII_RXID)) {
 267                 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL);
 268
 269                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
 270                         val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
 271
 272                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
 273                         val |= DP83867_RGMII_TX_CLK_DELAY_EN;
 274
 275                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
 276                         val |= DP83867_RGMII_RX_CLK_DELAY_EN;
 277
 278                 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);
 279
 280                 delay = (dp83867->rx_id_delay |
 281                         (dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
 282
 283                 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL,
 284                               delay);
 285
 286                 if (dp83867->io_impedance >= 0) {
 287                         val = phy_read_mmd(phydev, DP83867_DEVADDR,
 288                                            DP83867_IO_MUX_CFG);
 289
 290                         val &= ~DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
 291                         val |= dp83867->io_impedance &
 292                                DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
 293
 294                         phy_write_mmd(phydev, DP83867_DEVADDR,
 295                                       DP83867_IO_MUX_CFG, val);
 296                 }
 297         }
 298
 299         /* Enable Interrupt output INT_OE in CFG3 register */
 300         if (phy_interrupt_is_valid(phydev)) {
 301                 val = phy_read(phydev, DP83867_CFG3);
 302                 val |= BIT(7);
 303                 phy_write(phydev, DP83867_CFG3, val);
 304         }
 305
 306         if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP)
 307                 dp83867_config_port_mirroring(phydev);
 308
 309         /* Clock output selection if muxing property is set */
 310         if (dp83867->clk_output_sel != DP83867_CLK_O_SEL_REF_CLK) {
 311                 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG);
 312                 val &= ~DP83867_IO_MUX_CFG_CLK_O_SEL_MASK;
 313                 val |= (dp83867->clk_output_sel << DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT);
 314                 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG, val);
 315         }
 316
 317         return 0;
 318 }
 319
 320 static int dp83867_phy_reset(struct phy_device *phydev)
 321 {
 322         int err;
 323
 324         err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET);
 325         if (err < 0)
 326                 return err;
 327
 328         return dp83867_config_init(phydev);
 329 }
 330
 331 static struct phy_driver dp83867_driver[] = {
 332         {
 333                 .phy_id         = DP83867_PHY_ID,
 334                 .phy_id_mask    = 0xfffffff0,
 335                 .name           = "TI DP83867",
 336                 .features       = PHY_GBIT_FEATURES,
 337                 .flags          = PHY_HAS_INTERRUPT,
 338
 339                 .config_init    = dp83867_config_init,
 340                 .soft_reset     = dp83867_phy_reset,
 341
 342                 /* IRQ related */
 343                 .ack_interrupt  = dp83867_ack_interrupt,
 344                 .config_intr    = dp83867_config_intr,
 345
 346                 .suspend        = genphy_suspend,
 347                 .resume         = genphy_resume,
 348         },
 349 };
 350 module_phy_driver(dp83867_driver);
 351
 352 static struct mdio_device_id __maybe_unused dp83867_tbl[] = {
 353         { DP83867_PHY_ID, 0xfffffff0 },
 354         { }
 355 };
 356
 357 MODULE_DEVICE_TABLE(mdio, dp83867_tbl);
 358
 359 MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver");
 360 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
 361 MODULE_LICENSE("GPL");