drivers/net/wireless/adm8211.c

   1
   2 /*
   3  * Linux device driver for ADMtek ADM8211 (IEEE 802.11b MAC/BBP)
   4  *
   5  * Copyright (c) 2003, Jouni Malinen <j@w1.fi>
   6  * Copyright (c) 2004-2007, Michael Wu <flamingice@sourmilk.net>
   7  * Some parts copyright (c) 2003 by David Young <dyoung@pobox.com>
   8  * and used with permission.
   9  *
  10  * Much thanks to Infineon-ADMtek for their support of this driver.
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation. See README and COPYING for
  15  * more details.
  16  */
  17
  18 #include <linux/init.h>
  19 #include <linux/if.h>
  20 #include <linux/skbuff.h>
  21 #include <linux/etherdevice.h>
  22 #include <linux/pci.h>
  23 #include <linux/delay.h>
  24 #include <linux/crc32.h>
  25 #include <linux/eeprom_93cx6.h>
  26 #include <net/mac80211.h>
  27
  28 #include "adm8211.h"
  29
  30 MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
  31 MODULE_AUTHOR("Jouni Malinen <j@w1.fi>");
  32 MODULE_DESCRIPTION("Driver for IEEE 802.11b wireless cards based on ADMtek ADM8211");
  33 MODULE_SUPPORTED_DEVICE("ADM8211");
  34 MODULE_LICENSE("GPL");
  35
  36 static unsigned int tx_ring_size __read_mostly = 16;
  37 static unsigned int rx_ring_size __read_mostly = 16;
  38
  39 module_param(tx_ring_size, uint, 0);
  40 module_param(rx_ring_size, uint, 0);
  41
  42 static struct pci_device_id adm8211_pci_id_table[] __devinitdata = {
  43         /* ADMtek ADM8211 */
  44         { PCI_DEVICE(0x10B7, 0x6000) }, /* 3Com 3CRSHPW796 */
  45         { PCI_DEVICE(0x1200, 0x8201) }, /* ? */
  46         { PCI_DEVICE(0x1317, 0x8201) }, /* ADM8211A */
  47         { PCI_DEVICE(0x1317, 0x8211) }, /* ADM8211B/C */
  48         { 0 }
  49 };
  50
  51 static void adm8211_eeprom_register_read(struct eeprom_93cx6 *eeprom)
  52 {
  53         struct adm8211_priv *priv = eeprom->data;
  54         u32 reg = ADM8211_CSR_READ(SPR);
  55
  56         eeprom->reg_data_in = reg & ADM8211_SPR_SDI;
  57         eeprom->reg_data_out = reg & ADM8211_SPR_SDO;
  58         eeprom->reg_data_clock = reg & ADM8211_SPR_SCLK;
  59         eeprom->reg_chip_select = reg & ADM8211_SPR_SCS;
  60 }
  61
  62 static void adm8211_eeprom_register_write(struct eeprom_93cx6 *eeprom)
  63 {
  64         struct adm8211_priv *priv = eeprom->data;
  65         u32 reg = 0x4000 | ADM8211_SPR_SRS;
  66
  67         if (eeprom->reg_data_in)
  68                 reg |= ADM8211_SPR_SDI;
  69         if (eeprom->reg_data_out)
  70                 reg |= ADM8211_SPR_SDO;
  71         if (eeprom->reg_data_clock)
  72                 reg |= ADM8211_SPR_SCLK;
  73         if (eeprom->reg_chip_select)
  74                 reg |= ADM8211_SPR_SCS;
  75
  76         ADM8211_CSR_WRITE(SPR, reg);
  77         ADM8211_CSR_READ(SPR);          /* eeprom_delay */
  78 }
  79
  80 static int adm8211_read_eeprom(struct ieee80211_hw *dev)
  81 {
  82         struct adm8211_priv *priv = dev->priv;
  83         unsigned int words, i;
  84         struct ieee80211_chan_range chan_range;
  85         u16 cr49;
  86         struct eeprom_93cx6 eeprom = {
  87                 .data           = priv,
  88                 .register_read  = adm8211_eeprom_register_read,
  89                 .register_write = adm8211_eeprom_register_write
  90         };
  91
  92         if (ADM8211_CSR_READ(CSR_TEST0) & ADM8211_CSR_TEST0_EPTYP) {
  93                 /* 256 * 16-bit = 512 bytes */
  94                 eeprom.width = PCI_EEPROM_WIDTH_93C66;
  95                 words = 256;
  96         } else {
  97                 /* 64 * 16-bit = 128 bytes */
  98                 eeprom.width = PCI_EEPROM_WIDTH_93C46;
  99                 words = 64;
 100         }
 101
 102         priv->eeprom_len = words * 2;
 103         priv->eeprom = kmalloc(priv->eeprom_len, GFP_KERNEL);
 104         if (!priv->eeprom)
 105                 return -ENOMEM;
 106
 107         eeprom_93cx6_multiread(&eeprom, 0, (__le16 __force *)priv->eeprom, words);
 108
 109         cr49 = le16_to_cpu(priv->eeprom->cr49);
 110         priv->rf_type = (cr49 >> 3) & 0x7;
 111         switch (priv->rf_type) {
 112         case ADM8211_TYPE_INTERSIL:
 113         case ADM8211_TYPE_RFMD:
 114         case ADM8211_TYPE_MARVEL:
 115         case ADM8211_TYPE_AIROHA:
 116         case ADM8211_TYPE_ADMTEK:
 117                 break;
 118
 119         default:
 120                 if (priv->revid < ADM8211_REV_CA)
 121                         priv->rf_type = ADM8211_TYPE_RFMD;
 122                 else
 123                         priv->rf_type = ADM8211_TYPE_AIROHA;
 124
 125                 printk(KERN_WARNING "%s (adm8211): Unknown RFtype %d\n",
 126                        pci_name(priv->pdev), (cr49 >> 3) & 0x7);
 127         }
 128
 129         priv->bbp_type = cr49 & 0x7;
 130         switch (priv->bbp_type) {
 131         case ADM8211_TYPE_INTERSIL:
 132         case ADM8211_TYPE_RFMD:
 133         case ADM8211_TYPE_MARVEL:
 134         case ADM8211_TYPE_AIROHA:
 135         case ADM8211_TYPE_ADMTEK:
 136                 break;
 137         default:
 138                 if (priv->revid < ADM8211_REV_CA)
 139                         priv->bbp_type = ADM8211_TYPE_RFMD;
 140                 else
 141                         priv->bbp_type = ADM8211_TYPE_ADMTEK;
 142
 143                 printk(KERN_WARNING "%s (adm8211): Unknown BBPtype: %d\n",
 144                        pci_name(priv->pdev), cr49 >> 3);
 145         }
 146
 147         if (priv->eeprom->country_code >= ARRAY_SIZE(cranges)) {
 148                 printk(KERN_WARNING "%s (adm8211): Invalid country code (%d)\n",
 149                        pci_name(priv->pdev), priv->eeprom->country_code);
 150
 151                 chan_range = cranges[2];
 152         } else
 153                 chan_range = cranges[priv->eeprom->country_code];
 154
 155         printk(KERN_DEBUG "%s (adm8211): Channel range: %d - %d\n",
 156                pci_name(priv->pdev), (int)chan_range.min, (int)chan_range.max);
 157
 158         priv->modes[0].num_channels = chan_range.max - chan_range.min + 1;
 159         priv->modes[0].channels = priv->channels;
 160
 161         memcpy(priv->channels, adm8211_channels, sizeof(adm8211_channels));
 162
 163         for (i = 1; i <= ARRAY_SIZE(adm8211_channels); i++)
 164                 if (i >= chan_range.min && i <= chan_range.max)
 165                         priv->channels[i - 1].flag =
 166                                 IEEE80211_CHAN_W_SCAN |
 167                                 IEEE80211_CHAN_W_ACTIVE_SCAN |
 168                                 IEEE80211_CHAN_W_IBSS;
 169
 170         switch (priv->eeprom->specific_bbptype) {
 171         case ADM8211_BBP_RFMD3000:
 172         case ADM8211_BBP_RFMD3002:
 173         case ADM8211_BBP_ADM8011:
 174                 priv->specific_bbptype = priv->eeprom->specific_bbptype;
 175                 break;
 176
 177         default:
 178                 if (priv->revid < ADM8211_REV_CA)
 179                         priv->specific_bbptype = ADM8211_BBP_RFMD3000;
 180                 else
 181                         priv->specific_bbptype = ADM8211_BBP_ADM8011;
 182
 183                 printk(KERN_WARNING "%s (adm8211): Unknown specific BBP: %d\n",
 184                        pci_name(priv->pdev), priv->eeprom->specific_bbptype);
 185         }
 186
 187         switch (priv->eeprom->specific_rftype) {
 188         case ADM8211_RFMD2948:
 189         case ADM8211_RFMD2958:
 190         case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
 191         case ADM8211_MAX2820:
 192         case ADM8211_AL2210L:
 193                 priv->transceiver_type = priv->eeprom->specific_rftype;
 194                 break;
 195
 196         default:
 197                 if (priv->revid == ADM8211_REV_BA)
 198                         priv->transceiver_type = ADM8211_RFMD2958_RF3000_CONTROL_POWER;
 199                 else if (priv->revid == ADM8211_REV_CA)
 200                         priv->transceiver_type = ADM8211_AL2210L;
 201                 else if (priv->revid == ADM8211_REV_AB)
 202                         priv->transceiver_type = ADM8211_RFMD2948;
 203
 204                 printk(KERN_WARNING "%s (adm8211): Unknown transceiver: %d\n",
 205                        pci_name(priv->pdev), priv->eeprom->specific_rftype);
 206
 207                 break;
 208         }
 209
 210         printk(KERN_DEBUG "%s (adm8211): RFtype=%d BBPtype=%d Specific BBP=%d "
 211                "Transceiver=%d\n", pci_name(priv->pdev), priv->rf_type,
 212                priv->bbp_type, priv->specific_bbptype, priv->transceiver_type);
 213
 214         return 0;
 215 }
 216
 217 static inline void adm8211_write_sram(struct ieee80211_hw *dev,
 218                                       u32 addr, u32 data)
 219 {
 220         struct adm8211_priv *priv = dev->priv;
 221
 222         ADM8211_CSR_WRITE(WEPCTL, addr | ADM8211_WEPCTL_TABLE_WR |
 223                           (priv->revid < ADM8211_REV_BA ?
 224                            0 : ADM8211_WEPCTL_SEL_WEPTABLE ));
 225         ADM8211_CSR_READ(WEPCTL);
 226         msleep(1);
 227
 228         ADM8211_CSR_WRITE(WESK, data);
 229         ADM8211_CSR_READ(WESK);
 230         msleep(1);
 231 }
 232
 233 static void adm8211_write_sram_bytes(struct ieee80211_hw *dev,
 234                                      unsigned int addr, u8 *buf,
 235                                      unsigned int len)
 236 {
 237         struct adm8211_priv *priv = dev->priv;
 238         u32 reg = ADM8211_CSR_READ(WEPCTL);
 239         unsigned int i;
 240
 241         if (priv->revid < ADM8211_REV_BA) {
 242                 for (i = 0; i < len; i += 2) {
 243                         u16 val = buf[i] | (buf[i + 1] << 8);
 244                         adm8211_write_sram(dev, addr + i / 2, val);
 245                 }
 246         } else {
 247                 for (i = 0; i < len; i += 4) {
 248                         u32 val = (buf[i + 0] << 0 ) | (buf[i + 1] << 8 ) |
 249                                   (buf[i + 2] << 16) | (buf[i + 3] << 24);
 250                         adm8211_write_sram(dev, addr + i / 4, val);
 251                 }
 252         }
 253
 254         ADM8211_CSR_WRITE(WEPCTL, reg);
 255 }
 256
 257 static void adm8211_clear_sram(struct ieee80211_hw *dev)
 258 {
 259         struct adm8211_priv *priv = dev->priv;
 260         u32 reg = ADM8211_CSR_READ(WEPCTL);
 261         unsigned int addr;
 262
 263         for (addr = 0; addr < ADM8211_SRAM_SIZE; addr++)
 264                 adm8211_write_sram(dev, addr, 0);
 265
 266         ADM8211_CSR_WRITE(WEPCTL, reg);
 267 }
 268
 269 static int adm8211_get_stats(struct ieee80211_hw *dev,
 270                              struct ieee80211_low_level_stats *stats)
 271 {
 272         struct adm8211_priv *priv = dev->priv;
 273
 274         memcpy(stats, &priv->stats, sizeof(*stats));
 275
 276         return 0;
 277 }
 278
 279 static int adm8211_get_tx_stats(struct ieee80211_hw *dev,
 280                                 struct ieee80211_tx_queue_stats *stats)
 281 {
 282         struct adm8211_priv *priv = dev->priv;
 283         struct ieee80211_tx_queue_stats_data *data = &stats->data[0];
 284
 285         data->len = priv->cur_tx - priv->dirty_tx;
 286         data->limit = priv->tx_ring_size - 2;
 287         data->count = priv->dirty_tx;
 288
 289         return 0;
 290 }
 291
 292 static void adm8211_interrupt_tci(struct ieee80211_hw *dev)
 293 {
 294         struct adm8211_priv *priv = dev->priv;
 295         unsigned int dirty_tx;
 296
 297         spin_lock(&priv->lock);
 298
 299         for (dirty_tx = priv->dirty_tx; priv->cur_tx - dirty_tx; dirty_tx++) {
 300                 unsigned int entry = dirty_tx % priv->tx_ring_size;
 301                 u32 status = le32_to_cpu(priv->tx_ring[entry].status);
 302                 struct adm8211_tx_ring_info *info;
 303                 struct sk_buff *skb;
 304
 305                 if (status & TDES0_CONTROL_OWN ||
 306                     !(status & TDES0_CONTROL_DONE))
 307                         break;
 308
 309                 info = &priv->tx_buffers[entry];
 310                 skb = info->skb;
 311
 312                 /* TODO: check TDES0_STATUS_TUF and TDES0_STATUS_TRO */
 313
 314                 pci_unmap_single(priv->pdev, info->mapping,
 315                                  info->skb->len, PCI_DMA_TODEVICE);
 316
 317                 if (info->tx_control.flags & IEEE80211_TXCTL_REQ_TX_STATUS) {
 318                         struct ieee80211_tx_status tx_status = {{0}};
 319                         struct ieee80211_hdr *hdr;
 320                         size_t hdrlen = info->hdrlen;
 321
 322                         skb_pull(skb, sizeof(struct adm8211_tx_hdr));
 323                         hdr = (struct ieee80211_hdr *)skb_push(skb, hdrlen);
 324                         memcpy(hdr, skb->cb, hdrlen);
 325                         memcpy(&tx_status.control, &info->tx_control,
 326                                sizeof(tx_status.control));
 327                         if (!(status & TDES0_STATUS_ES))
 328                                 tx_status.flags |= IEEE80211_TX_STATUS_ACK;
 329                         ieee80211_tx_status_irqsafe(dev, skb, &tx_status);
 330                 } else
 331                         dev_kfree_skb_irq(skb);
 332                 info->skb = NULL;
 333         }
 334
 335         if (priv->cur_tx - dirty_tx < priv->tx_ring_size - 2)
 336                 ieee80211_wake_queue(dev, 0);
 337
 338         priv->dirty_tx = dirty_tx;
 339         spin_unlock(&priv->lock);
 340 }
 341
 342
 343 static void adm8211_interrupt_rci(struct ieee80211_hw *dev)
 344 {
 345         struct adm8211_priv *priv = dev->priv;
 346         unsigned int entry = priv->cur_rx % priv->rx_ring_size;
 347         u32 status;
 348         unsigned int pktlen;
 349         struct sk_buff *skb, *newskb;
 350         unsigned int limit = priv->rx_ring_size;
 351         static const u8 rate_tbl[] = {10, 20, 55, 110, 220};
 352         u8 rssi, rate;
 353
 354         while (!(priv->rx_ring[entry].status & cpu_to_le32(RDES0_STATUS_OWN))) {
 355                 if (!limit--)
 356                         break;
 357
 358                 status = le32_to_cpu(priv->rx_ring[entry].status);
 359                 rate = (status & RDES0_STATUS_RXDR) >> 12;
 360                 rssi = le32_to_cpu(priv->rx_ring[entry].length) &
 361                         RDES1_STATUS_RSSI;
 362
 363                 pktlen = status & RDES0_STATUS_FL;
 364                 if (pktlen > RX_PKT_SIZE) {
 365                         if (net_ratelimit())
 366                                 printk(KERN_DEBUG "%s: frame too long (%d)\n",
 367                                        wiphy_name(dev->wiphy), pktlen);
 368                         pktlen = RX_PKT_SIZE;
 369                 }
 370
 371                 if (!priv->soft_rx_crc && status & RDES0_STATUS_ES) {
 372                         skb = NULL; /* old buffer will be reused */
 373                         /* TODO: update RX error stats */
 374                         /* TODO: check RDES0_STATUS_CRC*E */
 375                 } else if (pktlen < RX_COPY_BREAK) {
 376                         skb = dev_alloc_skb(pktlen);
 377                         if (skb) {
 378                                 pci_dma_sync_single_for_cpu(
 379                                         priv->pdev,
 380                                         priv->rx_buffers[entry].mapping,
 381                                         pktlen, PCI_DMA_FROMDEVICE);
 382                                 memcpy(skb_put(skb, pktlen),
 383                                        skb_tail_pointer(priv->rx_buffers[entry].skb),
 384                                        pktlen);
 385                                 pci_dma_sync_single_for_device(
 386                                         priv->pdev,
 387                                         priv->rx_buffers[entry].mapping,
 388                                         RX_PKT_SIZE, PCI_DMA_FROMDEVICE);
 389                         }
 390                 } else {
 391                         newskb = dev_alloc_skb(RX_PKT_SIZE);
 392                         if (newskb) {
 393                                 skb = priv->rx_buffers[entry].skb;
 394                                 skb_put(skb, pktlen);
 395                                 pci_unmap_single(
 396                                         priv->pdev,
 397                                         priv->rx_buffers[entry].mapping,
 398                                         RX_PKT_SIZE, PCI_DMA_FROMDEVICE);
 399                                 priv->rx_buffers[entry].skb = newskb;
 400                                 priv->rx_buffers[entry].mapping =
 401                                         pci_map_single(priv->pdev,
 402                                                        skb_tail_pointer(newskb),
 403                                                        RX_PKT_SIZE,
 404                                                        PCI_DMA_FROMDEVICE);
 405                         } else {
 406                                 skb = NULL;
 407                                 /* TODO: update rx dropped stats */
 408                         }
 409
 410                         priv->rx_ring[entry].buffer1 =
 411                                 cpu_to_le32(priv->rx_buffers[entry].mapping);
 412                 }
 413
 414                 priv->rx_ring[entry].status = cpu_to_le32(RDES0_STATUS_OWN |
 415                                                           RDES0_STATUS_SQL);
 416                 priv->rx_ring[entry].length =
 417                         cpu_to_le32(RX_PKT_SIZE |
 418                                     (entry == priv->rx_ring_size - 1 ?
 419                                      RDES1_CONTROL_RER : 0));
 420
 421                 if (skb) {
 422                         struct ieee80211_rx_status rx_status = {0};
 423
 424                         if (priv->revid < ADM8211_REV_CA)
 425                                 rx_status.ssi = rssi;
 426                         else
 427                                 rx_status.ssi = 100 - rssi;
 428
 429                         if (rate <= 4)
 430                                 rx_status.rate = rate_tbl[rate];
 431
 432                         rx_status.channel = priv->channel;
 433                         rx_status.freq = adm8211_channels[priv->channel - 1].freq;
 434                         rx_status.phymode = MODE_IEEE80211B;
 435
 436                         ieee80211_rx_irqsafe(dev, skb, &rx_status);
 437                 }
 438
 439                 entry = (++priv->cur_rx) % priv->rx_ring_size;
 440         }
 441
 442         /* TODO: check LPC and update stats? */
 443 }
 444
 445
 446 static irqreturn_t adm8211_interrupt(int irq, void *dev_id)
 447 {
 448 #define ADM8211_INT(x)                                                     \
 449 do {                                                                       \
 450         if (unlikely(stsr & ADM8211_STSR_ ## x))                           \
 451                 printk(KERN_DEBUG "%s: " #x "\n", wiphy_name(dev->wiphy)); \
 452 } while (0)
 453
 454         struct ieee80211_hw *dev = dev_id;
 455         struct adm8211_priv *priv = dev->priv;
 456         u32 stsr = ADM8211_CSR_READ(STSR);
 457         ADM8211_CSR_WRITE(STSR, stsr);
 458         if (stsr == 0xffffffff)
 459                 return IRQ_HANDLED;
 460
 461         if (!(stsr & (ADM8211_STSR_NISS | ADM8211_STSR_AISS)))
 462                 return IRQ_HANDLED;
 463
 464         if (stsr & ADM8211_STSR_RCI)
 465                 adm8211_interrupt_rci(dev);
 466         if (stsr & ADM8211_STSR_TCI)
 467                 adm8211_interrupt_tci(dev);
 468
 469         /*ADM8211_INT(LinkOn);*/
 470         /*ADM8211_INT(LinkOff);*/
 471
 472         ADM8211_INT(PCF);
 473         ADM8211_INT(BCNTC);
 474         ADM8211_INT(GPINT);
 475         ADM8211_INT(ATIMTC);
 476         ADM8211_INT(TSFTF);
 477         ADM8211_INT(TSCZ);
 478         ADM8211_INT(SQL);
 479         ADM8211_INT(WEPTD);
 480         ADM8211_INT(ATIME);
 481         /*ADM8211_INT(TBTT);*/
 482         ADM8211_INT(TEIS);
 483         ADM8211_INT(FBE);
 484         ADM8211_INT(REIS);
 485         ADM8211_INT(GPTT);
 486         ADM8211_INT(RPS);
 487         ADM8211_INT(RDU);
 488         ADM8211_INT(TUF);
 489         /*ADM8211_INT(TRT);*/
 490         /*ADM8211_INT(TLT);*/
 491         /*ADM8211_INT(TDU);*/
 492         ADM8211_INT(TPS);
 493
 494         return IRQ_HANDLED;
 495
 496 #undef ADM8211_INT
 497 }
 498
 499 #define WRITE_SYN(name,v_mask,v_shift,a_mask,a_shift,bits,prewrite,postwrite)\
 500 static void adm8211_rf_write_syn_ ## name (struct ieee80211_hw *dev,         \
 501                                            u16 addr, u32 value) {            \
 502         struct adm8211_priv *priv = dev->priv;                               \
 503         unsigned int i;                                                      \
 504         u32 reg, bitbuf;                                                     \
 505                                                                              \
 506         value &= v_mask;                                                     \
 507         addr &= a_mask;                                                      \
 508         bitbuf = (value << v_shift) | (addr << a_shift);                     \
 509                                                                              \
 510         ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_IF_SELECT_1);                 \
 511         ADM8211_CSR_READ(SYNRF);                                             \
 512         ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_IF_SELECT_0);                 \
 513         ADM8211_CSR_READ(SYNRF);                                             \
 514                                                                              \
 515         if (prewrite) {                                                      \
 516                 ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_WRITE_SYNDATA_0);     \
 517                 ADM8211_CSR_READ(SYNRF);                                     \
 518         }                                                                    \
 519                                                                              \
 520         for (i = 0; i <= bits; i++) {                                        \
 521                 if (bitbuf & (1 << (bits - i)))                              \
 522                         reg = ADM8211_SYNRF_WRITE_SYNDATA_1;                 \
 523                 else                                                         \
 524                         reg = ADM8211_SYNRF_WRITE_SYNDATA_0;                 \
 525                                                                              \
 526                 ADM8211_CSR_WRITE(SYNRF, reg);                               \
 527                 ADM8211_CSR_READ(SYNRF);                                     \
 528                                                                              \
 529                 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_WRITE_CLOCK_1); \
 530                 ADM8211_CSR_READ(SYNRF);                                     \
 531                 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_WRITE_CLOCK_0); \
 532                 ADM8211_CSR_READ(SYNRF);                                     \
 533         }                                                                    \
 534                                                                              \
 535         if (postwrite == 1) {                                                \
 536                 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_IF_SELECT_0);   \
 537                 ADM8211_CSR_READ(SYNRF);                                     \
 538         }                                                                    \
 539         if (postwrite == 2) {                                                \
 540                 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_IF_SELECT_1);   \
 541                 ADM8211_CSR_READ(SYNRF);                                     \
 542         }                                                                    \
 543                                                                              \
 544         ADM8211_CSR_WRITE(SYNRF, 0);                                         \
 545         ADM8211_CSR_READ(SYNRF);                                             \
 546 }
 547
 548 WRITE_SYN(max2820,  0x00FFF, 0, 0x0F, 12, 15, 1, 1)
 549 WRITE_SYN(al2210l,  0xFFFFF, 4, 0x0F,  0, 23, 1, 1)
 550 WRITE_SYN(rfmd2958, 0x3FFFF, 0, 0x1F, 18, 23, 0, 1)
 551 WRITE_SYN(rfmd2948, 0x0FFFF, 4, 0x0F,  0, 21, 0, 2)
 552
 553 #undef WRITE_SYN
 554
 555 static int adm8211_write_bbp(struct ieee80211_hw *dev, u8 addr, u8 data)
 556 {
 557         struct adm8211_priv *priv = dev->priv;
 558         unsigned int timeout;
 559         u32 reg;
 560
 561         timeout = 10;
 562         while (timeout > 0) {
 563                 reg = ADM8211_CSR_READ(BBPCTL);
 564                 if (!(reg & (ADM8211_BBPCTL_WR | ADM8211_BBPCTL_RD)))
 565                         break;
 566                 timeout--;
 567                 msleep(2);
 568         }
 569
 570         if (timeout == 0) {
 571                 printk(KERN_DEBUG "%s: adm8211_write_bbp(%d,%d) failed"
 572                        " prewrite (reg=0x%08x)\n",
 573                        wiphy_name(dev->wiphy), addr, data, reg);
 574                 return -ETIMEDOUT;
 575         }
 576
 577         switch (priv->bbp_type) {
 578         case ADM8211_TYPE_INTERSIL:
 579                 reg = ADM8211_BBPCTL_MMISEL;    /* three wire interface */
 580                 break;
 581         case ADM8211_TYPE_RFMD:
 582                 reg = (0x20 << 24) | ADM8211_BBPCTL_TXCE | ADM8211_BBPCTL_CCAP |
 583                       (0x01 << 18);
 584                 break;
 585         case ADM8211_TYPE_ADMTEK:
 586                 reg = (0x20 << 24) | ADM8211_BBPCTL_TXCE | ADM8211_BBPCTL_CCAP |
 587                       (0x05 << 18);
 588                 break;
 589         }
 590         reg |= ADM8211_BBPCTL_WR | (addr << 8) | data;
 591
 592         ADM8211_CSR_WRITE(BBPCTL, reg);
 593
 594         timeout = 10;
 595         while (timeout > 0) {
 596                 reg = ADM8211_CSR_READ(BBPCTL);
 597                 if (!(reg & ADM8211_BBPCTL_WR))
 598                         break;
 599                 timeout--;
 600                 msleep(2);
 601         }
 602
 603         if (timeout == 0) {
 604                 ADM8211_CSR_WRITE(BBPCTL, ADM8211_CSR_READ(BBPCTL) &
 605                                   ~ADM8211_BBPCTL_WR);
 606                 printk(KERN_DEBUG "%s: adm8211_write_bbp(%d,%d) failed"
 607                        " postwrite (reg=0x%08x)\n",
 608                        wiphy_name(dev->wiphy), addr, data, reg);
 609                 return -ETIMEDOUT;
 610         }
 611
 612         return 0;
 613 }
 614
 615 static int adm8211_rf_set_channel(struct ieee80211_hw *dev, unsigned int chan)
 616 {
 617         static const u32 adm8211_rfmd2958_reg5[] =
 618                 {0x22BD, 0x22D2, 0x22E8, 0x22FE, 0x2314, 0x232A, 0x2340,
 619                  0x2355, 0x236B, 0x2381, 0x2397, 0x23AD, 0x23C2, 0x23F7};
 620         static const u32 adm8211_rfmd2958_reg6[] =
 621                 {0x05D17, 0x3A2E8, 0x2E8BA, 0x22E8B, 0x1745D, 0x0BA2E, 0x00000,
 622                  0x345D1, 0x28BA2, 0x1D174, 0x11745, 0x05D17, 0x3A2E8, 0x11745};
 623
 624         struct adm8211_priv *priv = dev->priv;
 625         u8 ant_power = priv->ant_power > 0x3F ?
 626                 priv->eeprom->antenna_power[chan - 1] : priv->ant_power;
 627         u8 tx_power = priv->tx_power > 0x3F ?
 628                 priv->eeprom->tx_power[chan - 1] : priv->tx_power;
 629         u8 lpf_cutoff = priv->lpf_cutoff == 0xFF ?
 630                 priv->eeprom->lpf_cutoff[chan - 1] : priv->lpf_cutoff;
 631         u8 lnags_thresh = priv->lnags_threshold == 0xFF ?
 632                 priv->eeprom->lnags_threshold[chan - 1] : priv->lnags_threshold;
 633         u32 reg;
 634
 635         ADM8211_IDLE();
 636
 637         /* Program synthesizer to new channel */
 638         switch (priv->transceiver_type) {
 639         case ADM8211_RFMD2958:
 640         case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
 641                 adm8211_rf_write_syn_rfmd2958(dev, 0x00, 0x04007);
 642                 adm8211_rf_write_syn_rfmd2958(dev, 0x02, 0x00033);
 643
 644                 adm8211_rf_write_syn_rfmd2958(dev, 0x05,
 645                         adm8211_rfmd2958_reg5[chan - 1]);
 646                 adm8211_rf_write_syn_rfmd2958(dev, 0x06,
 647                         adm8211_rfmd2958_reg6[chan - 1]);
 648                 break;
 649
 650         case ADM8211_RFMD2948:
 651                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_MAIN_CONF,
 652                                               SI4126_MAIN_XINDIV2);
 653                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_POWERDOWN,
 654                                               SI4126_POWERDOWN_PDIB |
 655                                               SI4126_POWERDOWN_PDRB);
 656                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_PHASE_DET_GAIN, 0);
 657                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_RF2_N_DIV,
 658                                               (chan == 14 ?
 659                                                2110 : (2033 + (chan * 5))));
 660                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_IF_N_DIV, 1496);
 661                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_RF2_R_DIV, 44);
 662                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_IF_R_DIV, 44);
 663                 break;
 664
 665         case ADM8211_MAX2820:
 666                 adm8211_rf_write_syn_max2820(dev, 0x3,
 667                         (chan == 14 ? 0x054 : (0x7 + (chan * 5))));
 668                 break;
 669
 670         case ADM8211_AL2210L:
 671                 adm8211_rf_write_syn_al2210l(dev, 0x0,
 672                         (chan == 14 ? 0x229B4 : (0x22967 + (chan * 5))));
 673                 break;
 674
 675         default:
 676                 printk(KERN_DEBUG "%s: unsupported transceiver type %d\n",
 677                        wiphy_name(dev->wiphy), priv->transceiver_type);
 678                 break;
 679         }
 680
 681         /* write BBP regs */
 682         if (priv->bbp_type == ADM8211_TYPE_RFMD) {
 683
 684         /* SMC 2635W specific? adm8211b doesn't use the 2948 though.. */
 685         /* TODO: remove if SMC 2635W doesn't need this */
 686         if (priv->transceiver_type == ADM8211_RFMD2948) {
 687                 reg = ADM8211_CSR_READ(GPIO);
 688                 reg &= 0xfffc0000;
 689                 reg |= ADM8211_CSR_GPIO_EN0;
 690                 if (chan != 14)
 691                         reg |= ADM8211_CSR_GPIO_O0;
 692                 ADM8211_CSR_WRITE(GPIO, reg);
 693         }
 694
 695         if (priv->transceiver_type == ADM8211_RFMD2958) {
 696                 /* set PCNT2 */
 697                 adm8211_rf_write_syn_rfmd2958(dev, 0x0B, 0x07100);
 698                 /* set PCNT1 P_DESIRED/MID_BIAS */
 699                 reg = le16_to_cpu(priv->eeprom->cr49);
 700                 reg >>= 13;
 701                 reg <<= 15;
 702                 reg |= ant_power << 9;
 703                 adm8211_rf_write_syn_rfmd2958(dev, 0x0A, reg);
 704                 /* set TXRX TX_GAIN */
 705                 adm8211_rf_write_syn_rfmd2958(dev, 0x09, 0x00050 |
 706                         (priv->revid < ADM8211_REV_CA ? tx_power : 0));
 707         } else {
 708                 reg = ADM8211_CSR_READ(PLCPHD);
 709                 reg &= 0xff00ffff;
 710                 reg |= tx_power << 18;
 711                 ADM8211_CSR_WRITE(PLCPHD, reg);
 712         }
 713
 714         ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_SELRF |
 715                           ADM8211_SYNRF_PE1 | ADM8211_SYNRF_PHYRST);
 716         ADM8211_CSR_READ(SYNRF);
 717         msleep(30);
 718
 719         /* RF3000 BBP */
 720         if (priv->transceiver_type != ADM8211_RFMD2958)
 721                 adm8211_write_bbp(dev, RF3000_TX_VAR_GAIN__TX_LEN_EXT,
 722                                   tx_power<<2);
 723         adm8211_write_bbp(dev, RF3000_LOW_GAIN_CALIB, lpf_cutoff);
 724         adm8211_write_bbp(dev, RF3000_HIGH_GAIN_CALIB, lnags_thresh);
 725         adm8211_write_bbp(dev, 0x1c, priv->revid == ADM8211_REV_BA ?
 726                                      priv->eeprom->cr28 : 0);
 727         adm8211_write_bbp(dev, 0x1d, priv->eeprom->cr29);
 728
 729         ADM8211_CSR_WRITE(SYNRF, 0);
 730
 731         /* Nothing to do for ADMtek BBP */
 732         } else if (priv->bbp_type != ADM8211_TYPE_ADMTEK)
 733                 printk(KERN_DEBUG "%s: unsupported BBP type %d\n",
 734                        wiphy_name(dev->wiphy), priv->bbp_type);
 735
 736         ADM8211_RESTORE();
 737
 738         /* update current channel for adhoc (and maybe AP mode) */
 739         reg = ADM8211_CSR_READ(CAP0);
 740         reg &= ~0xF;
 741         reg |= chan;
 742         ADM8211_CSR_WRITE(CAP0, reg);
 743
 744         return 0;
 745 }
 746
 747 static void adm8211_update_mode(struct ieee80211_hw *dev)
 748 {
 749         struct adm8211_priv *priv = dev->priv;
 750
 751         ADM8211_IDLE();
 752
 753         priv->soft_rx_crc = 0;
 754         switch (priv->mode) {
 755         case IEEE80211_IF_TYPE_STA:
 756                 priv->nar &= ~(ADM8211_NAR_PR | ADM8211_NAR_EA);
 757                 priv->nar |= ADM8211_NAR_ST | ADM8211_NAR_SR;
 758                 break;
 759         case IEEE80211_IF_TYPE_IBSS:
 760                 priv->nar &= ~ADM8211_NAR_PR;
 761                 priv->nar |= ADM8211_NAR_EA | ADM8211_NAR_ST | ADM8211_NAR_SR;
 762
 763                 /* don't trust the error bits on rev 0x20 and up in adhoc */
 764                 if (priv->revid >= ADM8211_REV_BA)
 765                         priv->soft_rx_crc = 1;
 766                 break;
 767         case IEEE80211_IF_TYPE_MNTR:
 768                 priv->nar &= ~(ADM8211_NAR_EA | ADM8211_NAR_ST);
 769                 priv->nar |= ADM8211_NAR_PR | ADM8211_NAR_SR;
 770                 break;
 771         }
 772
 773         ADM8211_RESTORE();
 774 }
 775
 776 static void adm8211_hw_init_syn(struct ieee80211_hw *dev)
 777 {
 778         struct adm8211_priv *priv = dev->priv;
 779
 780         switch (priv->transceiver_type) {
 781         case ADM8211_RFMD2958:
 782         case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
 783                 /* comments taken from ADMtek vendor driver */
 784
 785                 /* Reset RF2958 after power on */
 786                 adm8211_rf_write_syn_rfmd2958(dev, 0x1F, 0x00000);
 787                 /* Initialize RF VCO Core Bias to maximum */
 788                 adm8211_rf_write_syn_rfmd2958(dev, 0x0C, 0x3001F);
 789                 /* Initialize IF PLL */
 790                 adm8211_rf_write_syn_rfmd2958(dev, 0x01, 0x29C03);
 791                 /* Initialize IF PLL Coarse Tuning */
 792                 adm8211_rf_write_syn_rfmd2958(dev, 0x03, 0x1FF6F);
 793                 /* Initialize RF PLL */
 794                 adm8211_rf_write_syn_rfmd2958(dev, 0x04, 0x29403);
 795                 /* Initialize RF PLL Coarse Tuning */
 796                 adm8211_rf_write_syn_rfmd2958(dev, 0x07, 0x1456F);
 797                 /* Initialize TX gain and filter BW (R9) */
 798                 adm8211_rf_write_syn_rfmd2958(dev, 0x09,
 799                         (priv->transceiver_type == ADM8211_RFMD2958 ?
 800                          0x10050 : 0x00050));
 801                 /* Initialize CAL register */
 802                 adm8211_rf_write_syn_rfmd2958(dev, 0x08, 0x3FFF8);
 803                 break;
 804
 805         case ADM8211_MAX2820:
 806                 adm8211_rf_write_syn_max2820(dev, 0x1, 0x01E);
 807                 adm8211_rf_write_syn_max2820(dev, 0x2, 0x001);
 808                 adm8211_rf_write_syn_max2820(dev, 0x3, 0x054);
 809                 adm8211_rf_write_syn_max2820(dev, 0x4, 0x310);
 810                 adm8211_rf_write_syn_max2820(dev, 0x5, 0x000);
 811                 break;
 812
 813         case ADM8211_AL2210L:
 814                 adm8211_rf_write_syn_al2210l(dev, 0x0, 0x0196C);
 815                 adm8211_rf_write_syn_al2210l(dev, 0x1, 0x007CB);
 816                 adm8211_rf_write_syn_al2210l(dev, 0x2, 0x3582F);
 817                 adm8211_rf_write_syn_al2210l(dev, 0x3, 0x010A9);
 818                 adm8211_rf_write_syn_al2210l(dev, 0x4, 0x77280);
 819                 adm8211_rf_write_syn_al2210l(dev, 0x5, 0x45641);
 820                 adm8211_rf_write_syn_al2210l(dev, 0x6, 0xEA130);
 821                 adm8211_rf_write_syn_al2210l(dev, 0x7, 0x80000);
 822                 adm8211_rf_write_syn_al2210l(dev, 0x8, 0x7850F);
 823                 adm8211_rf_write_syn_al2210l(dev, 0x9, 0xF900C);
 824                 adm8211_rf_write_syn_al2210l(dev, 0xA, 0x00000);
 825                 adm8211_rf_write_syn_al2210l(dev, 0xB, 0x00000);
 826                 break;
 827
 828         case ADM8211_RFMD2948:
 829         default:
 830                 break;
 831         }
 832 }
 833
 834 static int adm8211_hw_init_bbp(struct ieee80211_hw *dev)
 835 {
 836         struct adm8211_priv *priv = dev->priv;
 837         u32 reg;
 838
 839         /* write addresses */
 840         if (priv->bbp_type == ADM8211_TYPE_INTERSIL) {
 841                 ADM8211_CSR_WRITE(MMIWA,  0x100E0C0A);
 842                 ADM8211_CSR_WRITE(MMIRD0, 0x00007C7E);
 843                 ADM8211_CSR_WRITE(MMIRD1, 0x00100000);
 844         } else if (priv->bbp_type == ADM8211_TYPE_RFMD ||
 845                    priv->bbp_type == ADM8211_TYPE_ADMTEK) {
 846                 /* check specific BBP type */
 847                 switch (priv->specific_bbptype) {
 848                 case ADM8211_BBP_RFMD3000:
 849                 case ADM8211_BBP_RFMD3002:
 850                         ADM8211_CSR_WRITE(MMIWA,  0x00009101);
 851                         ADM8211_CSR_WRITE(MMIRD0, 0x00000301);
 852                         break;
 853
 854                 case ADM8211_BBP_ADM8011:
 855                         ADM8211_CSR_WRITE(MMIWA,  0x00008903);
 856                         ADM8211_CSR_WRITE(MMIRD0, 0x00001716);
 857
 858                         reg = ADM8211_CSR_READ(BBPCTL);
 859                         reg &= ~ADM8211_BBPCTL_TYPE;
 860                         reg |= 0x5 << 18;
 861                         ADM8211_CSR_WRITE(BBPCTL, reg);
 862                         break;
 863                 }
 864
 865                 switch (priv->revid) {
 866                 case ADM8211_REV_CA:
 867                         if (priv->transceiver_type == ADM8211_RFMD2958 ||
 868                             priv->transceiver_type == ADM8211_RFMD2958_RF3000_CONTROL_POWER ||
 869                             priv->transceiver_type == ADM8211_RFMD2948)
 870                                 ADM8211_CSR_WRITE(SYNCTL, 0x1 << 22);
 871                         else if (priv->transceiver_type == ADM8211_MAX2820 ||
 872                                  priv->transceiver_type == ADM8211_AL2210L)
 873                                 ADM8211_CSR_WRITE(SYNCTL, 0x3 << 22);
 874                         break;
 875
 876                 case ADM8211_REV_BA:
 877                         reg  = ADM8211_CSR_READ(MMIRD1);
 878                         reg &= 0x0000FFFF;
 879                         reg |= 0x7e100000;
 880                         ADM8211_CSR_WRITE(MMIRD1, reg);
 881                         break;
 882
 883                 case ADM8211_REV_AB:
 884                 case ADM8211_REV_AF:
 885                 default:
 886                         ADM8211_CSR_WRITE(MMIRD1, 0x7e100000);
 887                         break;
 888                 }
 889
 890                 /* For RFMD */
 891                 ADM8211_CSR_WRITE(MACTEST, 0x800);
 892         }
 893
 894         adm8211_hw_init_syn(dev);
 895
 896         /* Set RF Power control IF pin to PE1+PHYRST# */
 897         ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_SELRF |
 898                           ADM8211_SYNRF_PE1 | ADM8211_SYNRF_PHYRST);
 899         ADM8211_CSR_READ(SYNRF);
 900         msleep(20);
 901
 902         /* write BBP regs */
 903         if (priv->bbp_type == ADM8211_TYPE_RFMD) {
 904                 /* RF3000 BBP */
 905                 /* another set:
 906                  * 11: c8
 907                  * 14: 14
 908                  * 15: 50 (chan 1..13; chan 14: d0)
 909                  * 1c: 00
 910                  * 1d: 84
 911                  */
 912                 adm8211_write_bbp(dev, RF3000_CCA_CTRL, 0x80);
 913                 /* antenna selection: diversity */
 914                 adm8211_write_bbp(dev, RF3000_DIVERSITY__RSSI, 0x80);
 915                 adm8211_write_bbp(dev, RF3000_TX_VAR_GAIN__TX_LEN_EXT, 0x74);
 916                 adm8211_write_bbp(dev, RF3000_LOW_GAIN_CALIB, 0x38);
 917                 adm8211_write_bbp(dev, RF3000_HIGH_GAIN_CALIB, 0x40);
 918
 919                 if (priv->eeprom->major_version < 2) {
 920                         adm8211_write_bbp(dev, 0x1c, 0x00);
 921                         adm8211_write_bbp(dev, 0x1d, 0x80);
 922                 } else {
 923                         if (priv->revid == ADM8211_REV_BA)
 924                                 adm8211_write_bbp(dev, 0x1c, priv->eeprom->cr28);
 925                         else
 926                                 adm8211_write_bbp(dev, 0x1c, 0x00);
 927
 928                         adm8211_write_bbp(dev, 0x1d, priv->eeprom->cr29);
 929                 }
 930         } else if (priv->bbp_type == ADM8211_TYPE_ADMTEK) {
 931                 /* reset baseband */
 932                 adm8211_write_bbp(dev, 0x00, 0xFF);
 933                 /* antenna selection: diversity */
 934                 adm8211_write_bbp(dev, 0x07, 0x0A);
 935
 936                 /* TODO: find documentation for this */
 937                 switch (priv->transceiver_type) {
 938                 case ADM8211_RFMD2958:
 939                 case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
 940                         adm8211_write_bbp(dev, 0x00, 0x00);
 941                         adm8211_write_bbp(dev, 0x01, 0x00);
 942                         adm8211_write_bbp(dev, 0x02, 0x00);
 943                         adm8211_write_bbp(dev, 0x03, 0x00);
 944                         adm8211_write_bbp(dev, 0x06, 0x0f);
 945                         adm8211_write_bbp(dev, 0x09, 0x00);
 946                         adm8211_write_bbp(dev, 0x0a, 0x00);
 947                         adm8211_write_bbp(dev, 0x0b, 0x00);
 948                         adm8211_write_bbp(dev, 0x0c, 0x00);
 949                         adm8211_write_bbp(dev, 0x0f, 0xAA);
 950                         adm8211_write_bbp(dev, 0x10, 0x8c);
 951                         adm8211_write_bbp(dev, 0x11, 0x43);
 952                         adm8211_write_bbp(dev, 0x18, 0x40);
 953                         adm8211_write_bbp(dev, 0x20, 0x23);
 954                         adm8211_write_bbp(dev, 0x21, 0x02);
 955                         adm8211_write_bbp(dev, 0x22, 0x28);
 956                         adm8211_write_bbp(dev, 0x23, 0x30);
 957                         adm8211_write_bbp(dev, 0x24, 0x2d);
 958                         adm8211_write_bbp(dev, 0x28, 0x35);
 959                         adm8211_write_bbp(dev, 0x2a, 0x8c);
 960                         adm8211_write_bbp(dev, 0x2b, 0x81);
 961                         adm8211_write_bbp(dev, 0x2c, 0x44);
 962                         adm8211_write_bbp(dev, 0x2d, 0x0A);
 963                         adm8211_write_bbp(dev, 0x29, 0x40);
 964                         adm8211_write_bbp(dev, 0x60, 0x08);
 965                         adm8211_write_bbp(dev, 0x64, 0x01);
 966                         break;
 967
 968                 case ADM8211_MAX2820:
 969                         adm8211_write_bbp(dev, 0x00, 0x00);
 970                         adm8211_write_bbp(dev, 0x01, 0x00);
 971                         adm8211_write_bbp(dev, 0x02, 0x00);
 972                         adm8211_write_bbp(dev, 0x03, 0x00);
 973                         adm8211_write_bbp(dev, 0x06, 0x0f);
 974                         adm8211_write_bbp(dev, 0x09, 0x05);
 975                         adm8211_write_bbp(dev, 0x0a, 0x02);
 976                         adm8211_write_bbp(dev, 0x0b, 0x00);
 977                         adm8211_write_bbp(dev, 0x0c, 0x0f);
 978                         adm8211_write_bbp(dev, 0x0f, 0x55);
 979                         adm8211_write_bbp(dev, 0x10, 0x8d);
 980                         adm8211_write_bbp(dev, 0x11, 0x43);
 981                         adm8211_write_bbp(dev, 0x18, 0x4a);
 982                         adm8211_write_bbp(dev, 0x20, 0x20);
 983                         adm8211_write_bbp(dev, 0x21, 0x02);
 984                         adm8211_write_bbp(dev, 0x22, 0x23);
 985                         adm8211_write_bbp(dev, 0x23, 0x30);
 986                         adm8211_write_bbp(dev, 0x24, 0x2d);
 987                         adm8211_write_bbp(dev, 0x2a, 0x8c);
 988                         adm8211_write_bbp(dev, 0x2b, 0x81);
 989                         adm8211_write_bbp(dev, 0x2c, 0x44);
 990                         adm8211_write_bbp(dev, 0x29, 0x4a);
 991                         adm8211_write_bbp(dev, 0x60, 0x2b);
 992                         adm8211_write_bbp(dev, 0x64, 0x01);
 993                         break;
 994
 995                 case ADM8211_AL2210L:
 996                         adm8211_write_bbp(dev, 0x00, 0x00);
 997                         adm8211_write_bbp(dev, 0x01, 0x00);
 998                         adm8211_write_bbp(dev, 0x02, 0x00);
 999                         adm8211_write_bbp(dev, 0x03, 0x00);
1000                         adm8211_write_bbp(dev, 0x06, 0x0f);
1001                         adm8211_write_bbp(dev, 0x07, 0x05);
1002                         adm8211_write_bbp(dev, 0x08, 0x03);
1003                         adm8211_write_bbp(dev, 0x09, 0x00);
1004                         adm8211_write_bbp(dev, 0x0a, 0x00);
1005                         adm8211_write_bbp(dev, 0x0b, 0x00);
1006                         adm8211_write_bbp(dev, 0x0c, 0x10);
1007                         adm8211_write_bbp(dev, 0x0f, 0x55);
1008                         adm8211_write_bbp(dev, 0x10, 0x8d);
1009                         adm8211_write_bbp(dev, 0x11, 0x43);
1010                         adm8211_write_bbp(dev, 0x18, 0x4a);
1011                         adm8211_write_bbp(dev, 0x20, 0x20);
1012                         adm8211_write_bbp(dev, 0x21, 0x02);
1013                         adm8211_write_bbp(dev, 0x22, 0x23);
1014                         adm8211_write_bbp(dev, 0x23, 0x30);
1015                         adm8211_write_bbp(dev, 0x24, 0x2d);
1016                         adm8211_write_bbp(dev, 0x2a, 0xaa);
1017                         adm8211_write_bbp(dev, 0x2b, 0x81);
1018                         adm8211_write_bbp(dev, 0x2c, 0x44);
1019                         adm8211_write_bbp(dev, 0x29, 0xfa);
1020                         adm8211_write_bbp(dev, 0x60, 0x2d);
1021                         adm8211_write_bbp(dev, 0x64, 0x01);
1022                         break;
1023
1024                 case ADM8211_RFMD2948:
1025                         break;
1026
1027                 default:
1028                         printk(KERN_DEBUG "%s: unsupported transceiver %d\n",
1029                                wiphy_name(dev->wiphy), priv->transceiver_type);
1030                         break;
1031                 }
1032         } else
1033                 printk(KERN_DEBUG "%s: unsupported BBP %d\n",
1034                        wiphy_name(dev->wiphy), priv->bbp_type);
1035
1036         ADM8211_CSR_WRITE(SYNRF, 0);
1037
1038         /* Set RF CAL control source to MAC control */
1039         reg = ADM8211_CSR_READ(SYNCTL);
1040         reg |= ADM8211_SYNCTL_SELCAL;
1041         ADM8211_CSR_WRITE(SYNCTL, reg);
1042
1043         return 0;
1044 }
1045
1046 /* configures hw beacons/probe responses */
1047 static int adm8211_set_rate(struct ieee80211_hw *dev)
1048 {
1049         struct adm8211_priv *priv = dev->priv;
1050         u32 reg;
1051         int i = 0;
1052         u8 rate_buf[12] = {0};
1053
1054         /* write supported rates */
1055         if (priv->revid != ADM8211_REV_BA) {
1056                 rate_buf[0] = ARRAY_SIZE(adm8211_rates);
1057                 for (i = 0; i < ARRAY_SIZE(adm8211_rates); i++)
1058                         rate_buf[i + 1] = (adm8211_rates[i].rate / 5) | 0x80;
1059         } else {
1060                 /* workaround for rev BA specific bug */
1061                 rate_buf[0] = 0x04;
1062                 rate_buf[1] = 0x82;
1063                 rate_buf[2] = 0x04;
1064                 rate_buf[3] = 0x0b;
1065                 rate_buf[4] = 0x16;
1066         }
1067
1068         adm8211_write_sram_bytes(dev, ADM8211_SRAM_SUPP_RATE, rate_buf,
1069                                  ARRAY_SIZE(adm8211_rates) + 1);
1070
1071         reg = ADM8211_CSR_READ(PLCPHD) & 0x00FFFFFF; /* keep bits 0-23 */
1072         reg |= 1 << 15; /* short preamble */
1073         reg |= 110 << 24;
1074         ADM8211_CSR_WRITE(PLCPHD, reg);
1075
1076         /* MTMLT   = 512 TU (max TX MSDU lifetime)
1077          * BCNTSIG = plcp_signal (beacon, probe resp, and atim TX rate)
1078          * SRTYLIM = 224 (short retry limit, TX header value is default) */
1079         ADM8211_CSR_WRITE(TXLMT, (512 << 16) | (110 << 8) | (224 << 0));
1080
1081         return 0;
1082 }
1083
1084 static void adm8211_hw_init(struct ieee80211_hw *dev)
1085 {
1086         struct adm8211_priv *priv = dev->priv;
1087         u32 reg;
1088         u8 cline;
1089
1090         reg = le32_to_cpu(ADM8211_CSR_READ(PAR));
1091         reg |= ADM8211_PAR_MRLE | ADM8211_PAR_MRME;
1092         reg &= ~(ADM8211_PAR_BAR | ADM8211_PAR_CAL);
1093
1094         if (!pci_set_mwi(priv->pdev)) {
1095                 reg |= 0x1 << 24;
1096                 pci_read_config_byte(priv->pdev, PCI_CACHE_LINE_SIZE, &cline);
1097
1098                 switch (cline) {
1099                 case  0x8: reg |= (0x1 << 14);
1100                            break;
1101                 case 0x16: reg |= (0x2 << 14);
1102                            break;
1103                 case 0x32: reg |= (0x3 << 14);
1104                            break;
1105                   default: reg |= (0x0 << 14);
1106                            break;
1107                 }
1108         }
1109
1110         ADM8211_CSR_WRITE(PAR, reg);
1111
1112         reg = ADM8211_CSR_READ(CSR_TEST1);
1113         reg &= ~(0xF << 28);
1114         reg |= (1 << 28) | (1 << 31);
1115         ADM8211_CSR_WRITE(CSR_TEST1, reg);
1116
1117         /* lose link after 4 lost beacons */
1118         reg = (0x04 << 21) | ADM8211_WCSR_TSFTWE | ADM8211_WCSR_LSOE;
1119         ADM8211_CSR_WRITE(WCSR, reg);
1120
1121         /* Disable APM, enable receive FIFO threshold, and set drain receive
1122          * threshold to store-and-forward */
1123         reg = ADM8211_CSR_READ(CMDR);
1124         reg &= ~(ADM8211_CMDR_APM | ADM8211_CMDR_DRT);
1125         reg |= ADM8211_CMDR_RTE | ADM8211_CMDR_DRT_SF;
1126         ADM8211_CSR_WRITE(CMDR, reg);
1127
1128         adm8211_set_rate(dev);
1129
1130         /* 4-bit values:
1131          * PWR1UP   = 8 * 2 ms
1132          * PWR0PAPE = 8 us or 5 us
1133          * PWR1PAPE = 1 us or 3 us
1134          * PWR0TRSW = 5 us
1135          * PWR1TRSW = 12 us
1136          * PWR0PE2  = 13 us
1137          * PWR1PE2  = 1 us
1138          * PWR0TXPE = 8 or 6 */
1139         if (priv->revid < ADM8211_REV_CA)
1140                 ADM8211_CSR_WRITE(TOFS2, 0x8815cd18);
1141         else
1142                 ADM8211_CSR_WRITE(TOFS2, 0x8535cd16);
1143
1144         /* Enable store and forward for transmit */
1145         priv->nar = ADM8211_NAR_SF | ADM8211_NAR_PB;
1146         ADM8211_CSR_WRITE(NAR, priv->nar);
1147
1148         /* Reset RF */
1149         ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_RADIO);
1150         ADM8211_CSR_READ(SYNRF);
1151         msleep(10);
1152         ADM8211_CSR_WRITE(SYNRF, 0);
1153         ADM8211_CSR_READ(SYNRF);
1154         msleep(5);
1155
1156         /* Set CFP Max Duration to 0x10 TU */
1157         reg = ADM8211_CSR_READ(CFPP);
1158         reg &= ~(0xffff << 8);
1159         reg |= 0x0010 << 8;
1160         ADM8211_CSR_WRITE(CFPP, reg);
1161
1162         /* USCNT = 0x16 (number of system clocks, 22 MHz, in 1us
1163          * TUCNT = 0x3ff - Tu counter 1024 us  */
1164         ADM8211_CSR_WRITE(TOFS0, (0x16 << 24) | 0x3ff);
1165
1166         /* SLOT=20 us, SIFS=110 cycles of 22 MHz (5 us),
1167          * DIFS=50 us, EIFS=100 us */
1168         if (priv->revid < ADM8211_REV_CA)
1169                 ADM8211_CSR_WRITE(IFST, (20 << 23) | (110 << 15) |
1170                                         (50 << 9)  | 100);
1171         else
1172                 ADM8211_CSR_WRITE(IFST, (20 << 23) | (24 << 15) |
1173                                         (50 << 9)  | 100);
1174
1175         /* PCNT = 1 (MAC idle time awake/sleep, unit S)
1176          * RMRD = 2346 * 8 + 1 us (max RX duration)  */
1177         ADM8211_CSR_WRITE(RMD, (1 << 16) | 18769);
1178
1179         /* MART=65535 us, MIRT=256 us, TSFTOFST=0 us */
1180         ADM8211_CSR_WRITE(RSPT, 0xffffff00);
1181
1182         /* Initialize BBP (and SYN) */
1183         adm8211_hw_init_bbp(dev);
1184
1185         /* make sure interrupts are off */
1186         ADM8211_CSR_WRITE(IER, 0);
1187
1188         /* ACK interrupts */
1189         ADM8211_CSR_WRITE(STSR, ADM8211_CSR_READ(STSR));
1190
1191         /* Setup WEP (turns it off for now) */
1192         reg = ADM8211_CSR_READ(MACTEST);
1193         reg &= ~(7 << 20);
1194         ADM8211_CSR_WRITE(MACTEST, reg);
1195
1196         reg = ADM8211_CSR_READ(WEPCTL);
1197         reg &= ~ADM8211_WEPCTL_WEPENABLE;
1198         reg |= ADM8211_WEPCTL_WEPRXBYP;
1199         ADM8211_CSR_WRITE(WEPCTL, reg);
1200
1201         /* Clear the missed-packet counter. */
1202         ADM8211_CSR_READ(LPC);
1203 }
1204
1205 static int adm8211_hw_reset(struct ieee80211_hw *dev)
1206 {
1207         struct adm8211_priv *priv = dev->priv;
1208         u32 reg, tmp;
1209         int timeout = 100;
1210
1211         /* Power-on issue */
1212         /* TODO: check if this is necessary */
1213         ADM8211_CSR_WRITE(FRCTL, 0);
1214
1215         /* Reset the chip */
1216         tmp = ADM8211_CSR_READ(PAR);
1217         ADM8211_CSR_WRITE(PAR, ADM8211_PAR_SWR);
1218
1219         while ((ADM8211_CSR_READ(PAR) & ADM8211_PAR_SWR) && timeout--)
1220                 msleep(50);
1221
1222         if (timeout <= 0)
1223                 return -ETIMEDOUT;
1224
1225         ADM8211_CSR_WRITE(PAR, tmp);
1226
1227         if (priv->revid == ADM8211_REV_BA &&
1228             (priv->transceiver_type == ADM8211_RFMD2958_RF3000_CONTROL_POWER ||
1229              priv->transceiver_type == ADM8211_RFMD2958)) {
1230                 reg = ADM8211_CSR_READ(CSR_TEST1);
1231                 reg |= (1 << 4) | (1 << 5);
1232                 ADM8211_CSR_WRITE(CSR_TEST1, reg);
1233         } else if (priv->revid == ADM8211_REV_CA) {
1234                 reg = ADM8211_CSR_READ(CSR_TEST1);
1235                 reg &= ~((1 << 4) | (1 << 5));
1236                 ADM8211_CSR_WRITE(CSR_TEST1, reg);
1237         }
1238
1239         ADM8211_CSR_WRITE(FRCTL, 0);
1240
1241         reg = ADM8211_CSR_READ(CSR_TEST0);
1242         reg |= ADM8211_CSR_TEST0_EPRLD; /* EEPROM Recall */
1243         ADM8211_CSR_WRITE(CSR_TEST0, reg);
1244
1245         adm8211_clear_sram(dev);
1246
1247         return 0;
1248 }
1249
1250 static u64 adm8211_get_tsft(struct ieee80211_hw *dev)
1251 {
1252         struct adm8211_priv *priv = dev->priv;
1253         u32 tsftl;
1254         u64 tsft;
1255
1256         tsftl = ADM8211_CSR_READ(TSFTL);
1257         tsft = ADM8211_CSR_READ(TSFTH);
1258         tsft <<= 32;
1259         tsft |= tsftl;
1260
1261         return tsft;
1262 }
1263
1264 static void adm8211_set_interval(struct ieee80211_hw *dev,
1265                                  unsigned short bi, unsigned short li)
1266 {
1267         struct adm8211_priv *priv = dev->priv;
1268         u32 reg;
1269
1270         /* BP (beacon interval) = data->beacon_interval
1271          * LI (listen interval) = data->listen_interval (in beacon intervals) */
1272         reg = (bi << 16) | li;
1273         ADM8211_CSR_WRITE(BPLI, reg);
1274 }
1275
1276 static void adm8211_set_bssid(struct ieee80211_hw *dev, const u8 *bssid)
1277 {
1278         struct adm8211_priv *priv = dev->priv;
1279         u32 reg;
1280
1281         ADM8211_CSR_WRITE(BSSID0, le32_to_cpu(*(__le32 *)bssid));
1282         reg = ADM8211_CSR_READ(ABDA1);
1283         reg &= 0x0000ffff;
1284         reg |= (bssid[4] << 16) | (bssid[5] << 24);
1285         ADM8211_CSR_WRITE(ABDA1, reg);
1286 }
1287
1288 static int adm8211_set_ssid(struct ieee80211_hw *dev, u8 *ssid, size_t ssid_len)
1289 {
1290         struct adm8211_priv *priv = dev->priv;
1291         u8 buf[36];
1292
1293         if (ssid_len > 32)
1294                 return -EINVAL;
1295
1296         memset(buf, 0, sizeof(buf));
1297         buf[0] = ssid_len;
1298         memcpy(buf + 1, ssid, ssid_len);
1299         adm8211_write_sram_bytes(dev, ADM8211_SRAM_SSID, buf, 33);
1300         /* TODO: configure beacon for adhoc? */
1301         return 0;
1302 }
1303
1304 static int adm8211_config(struct ieee80211_hw *dev, struct ieee80211_conf *conf)
1305 {
1306         struct adm8211_priv *priv = dev->priv;
1307
1308         if (conf->channel != priv->channel) {
1309                 priv->channel = conf->channel;
1310                 adm8211_rf_set_channel(dev, priv->channel);
1311         }
1312
1313         return 0;
1314 }
1315
1316 static int adm8211_config_interface(struct ieee80211_hw *dev, int if_id,
1317                                     struct ieee80211_if_conf *conf)
1318 {
1319         struct adm8211_priv *priv = dev->priv;
1320
1321         if (memcmp(conf->bssid, priv->bssid, ETH_ALEN)) {
1322                 adm8211_set_bssid(dev, conf->bssid);
1323                 memcpy(priv->bssid, conf->bssid, ETH_ALEN);
1324         }
1325
1326         if (conf->ssid_len != priv->ssid_len ||
1327             memcmp(conf->ssid, priv->ssid, conf->ssid_len)) {
1328                 adm8211_set_ssid(dev, conf->ssid, conf->ssid_len);
1329                 priv->ssid_len = conf->ssid_len;
1330                 memcpy(priv->ssid, conf->ssid, conf->ssid_len);
1331         }
1332
1333         return 0;
1334 }
1335
1336 static void adm8211_configure_filter(struct ieee80211_hw *dev,
1337                                      unsigned int changed_flags,
1338                                      unsigned int *total_flags,
1339                                      int mc_count, struct dev_mc_list *mclist)
1340 {
1341         static const u8 bcast[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
1342         struct adm8211_priv *priv = dev->priv;
1343         unsigned int bit_nr, new_flags;
1344         u32 mc_filter[2];
1345         int i;
1346
1347         new_flags = 0;
1348
1349         if (*total_flags & FIF_PROMISC_IN_BSS) {
1350                 new_flags |= FIF_PROMISC_IN_BSS;
1351                 priv->nar |= ADM8211_NAR_PR;
1352                 priv->nar &= ~ADM8211_NAR_MM;
1353                 mc_filter[1] = mc_filter[0] = ~0;
1354         } else if ((*total_flags & FIF_ALLMULTI) || (mc_count > 32)) {
1355                 new_flags |= FIF_ALLMULTI;
1356                 priv->nar &= ~ADM8211_NAR_PR;
1357                 priv->nar |= ADM8211_NAR_MM;
1358                 mc_filter[1] = mc_filter[0] = ~0;
1359         } else {
1360                 priv->nar &= ~(ADM8211_NAR_MM | ADM8211_NAR_PR);
1361                 mc_filter[1] = mc_filter[0] = 0;
1362                 for (i = 0; i < mc_count; i++) {
1363                         if (!mclist)
1364                                 break;
1365                         bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
1366
1367                         bit_nr &= 0x3F;
1368                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1369                         mclist = mclist->next;
1370                 }
1371         }
1372
1373         ADM8211_IDLE_RX();
1374
1375         ADM8211_CSR_WRITE(MAR0, mc_filter[0]);
1376         ADM8211_CSR_WRITE(MAR1, mc_filter[1]);
1377         ADM8211_CSR_READ(NAR);
1378
1379         if (priv->nar & ADM8211_NAR_PR)
1380                 dev->flags |= IEEE80211_HW_RX_INCLUDES_FCS;
1381         else
1382                 dev->flags &= ~IEEE80211_HW_RX_INCLUDES_FCS;
1383
1384         if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
1385                 adm8211_set_bssid(dev, bcast);
1386         else
1387                 adm8211_set_bssid(dev, priv->bssid);
1388
1389         ADM8211_RESTORE();
1390
1391         *total_flags = new_flags;
1392 }
1393
1394 static int adm8211_add_interface(struct ieee80211_hw *dev,
1395                                  struct ieee80211_if_init_conf *conf)
1396 {
1397         struct adm8211_priv *priv = dev->priv;
1398         if (priv->mode != IEEE80211_IF_TYPE_MNTR)
1399                 return -EOPNOTSUPP;
1400
1401         switch (conf->type) {
1402         case IEEE80211_IF_TYPE_STA:
1403                 priv->mode = conf->type;
1404                 break;
1405         default:
1406                 return -EOPNOTSUPP;
1407         }
1408
1409         ADM8211_IDLE();
1410
1411         ADM8211_CSR_WRITE(PAR0, le32_to_cpu(*(__le32 *)conf->mac_addr));
1412         ADM8211_CSR_WRITE(PAR1, le16_to_cpu(*(__le16 *)(conf->mac_addr + 4)));
1413
1414         adm8211_update_mode(dev);
1415
1416         ADM8211_RESTORE();
1417
1418         return 0;
1419 }
1420
1421 static void adm8211_remove_interface(struct ieee80211_hw *dev,
1422                                      struct ieee80211_if_init_conf *conf)
1423 {
1424         struct adm8211_priv *priv = dev->priv;
1425         priv->mode = IEEE80211_IF_TYPE_MNTR;
1426 }
1427
1428 static int adm8211_init_rings(struct ieee80211_hw *dev)
1429 {
1430         struct adm8211_priv *priv = dev->priv;
1431         struct adm8211_desc *desc = NULL;
1432         struct adm8211_rx_ring_info *rx_info;
1433         struct adm8211_tx_ring_info *tx_info;
1434         unsigned int i;
1435
1436         for (i = 0; i < priv->rx_ring_size; i++) {
1437                 desc = &priv->rx_ring[i];
1438                 desc->status = 0;
1439                 desc->length = cpu_to_le32(RX_PKT_SIZE);
1440                 priv->rx_buffers[i].skb = NULL;
1441         }
1442         /* Mark the end of RX ring; hw returns to base address after this
1443          * descriptor */
1444         desc->length |= cpu_to_le32(RDES1_CONTROL_RER);
1445
1446         for (i = 0; i < priv->rx_ring_size; i++) {
1447                 desc = &priv->rx_ring[i];
1448                 rx_info = &priv->rx_buffers[i];
1449
1450                 rx_info->skb = dev_alloc_skb(RX_PKT_SIZE);
1451                 if (rx_info->skb == NULL)
1452                         break;
1453                 rx_info->mapping = pci_map_single(priv->pdev,
1454                                                   skb_tail_pointer(rx_info->skb),
1455                                                   RX_PKT_SIZE,
1456                                                   PCI_DMA_FROMDEVICE);
1457                 desc->buffer1 = cpu_to_le32(rx_info->mapping);
1458                 desc->status = cpu_to_le32(RDES0_STATUS_OWN | RDES0_STATUS_SQL);
1459         }
1460
1461         /* Setup TX ring. TX buffers descriptors will be filled in as needed */
1462         for (i = 0; i < priv->tx_ring_size; i++) {
1463                 desc = &priv->tx_ring[i];
1464                 tx_info = &priv->tx_buffers[i];
1465
1466                 tx_info->skb = NULL;
1467                 tx_info->mapping = 0;
1468                 desc->status = 0;
1469         }
1470         desc->length = cpu_to_le32(TDES1_CONTROL_TER);
1471
1472         priv->cur_rx = priv->cur_tx = priv->dirty_tx = 0;
1473         ADM8211_CSR_WRITE(RDB, priv->rx_ring_dma);
1474         ADM8211_CSR_WRITE(TDBD, priv->tx_ring_dma);
1475
1476         return 0;
1477 }
1478
1479 static void adm8211_free_rings(struct ieee80211_hw *dev)
1480 {
1481         struct adm8211_priv *priv = dev->priv;
1482         unsigned int i;
1483
1484         for (i = 0; i < priv->rx_ring_size; i++) {
1485                 if (!priv->rx_buffers[i].skb)
1486                         continue;
1487
1488                 pci_unmap_single(
1489                         priv->pdev,
1490                         priv->rx_buffers[i].mapping,
1491                         RX_PKT_SIZE, PCI_DMA_FROMDEVICE);
1492
1493                 dev_kfree_skb(priv->rx_buffers[i].skb);
1494         }
1495
1496         for (i = 0; i < priv->tx_ring_size; i++) {
1497                 if (!priv->tx_buffers[i].skb)
1498                         continue;
1499
1500                 pci_unmap_single(priv->pdev,
1501                                  priv->tx_buffers[i].mapping,
1502                                  priv->tx_buffers[i].skb->len,
1503                                  PCI_DMA_TODEVICE);
1504
1505                 dev_kfree_skb(priv->tx_buffers[i].skb);
1506         }
1507 }
1508
1509 static int adm8211_start(struct ieee80211_hw *dev)
1510 {
1511         struct adm8211_priv *priv = dev->priv;
1512         int retval;
1513
1514         /* Power up MAC and RF chips */
1515         retval = adm8211_hw_reset(dev);
1516         if (retval) {
1517                 printk(KERN_ERR "%s: hardware reset failed\n",
1518                        wiphy_name(dev->wiphy));
1519                 goto fail;
1520         }
1521
1522         retval = adm8211_init_rings(dev);
1523         if (retval) {
1524                 printk(KERN_ERR "%s: failed to initialize rings\n",
1525                        wiphy_name(dev->wiphy));
1526                 goto fail;
1527         }
1528
1529         /* Init hardware */
1530         adm8211_hw_init(dev);
1531         adm8211_rf_set_channel(dev, priv->channel);
1532
1533         retval = request_irq(priv->pdev->irq, &adm8211_interrupt,
1534                              IRQF_SHARED, "adm8211", dev);
1535         if (retval) {
1536                 printk(KERN_ERR "%s: failed to register IRQ handler\n",
1537                        wiphy_name(dev->wiphy));
1538                 goto fail;
1539         }
1540
1541         ADM8211_CSR_WRITE(IER, ADM8211_IER_NIE | ADM8211_IER_AIE |
1542                                ADM8211_IER_RCIE | ADM8211_IER_TCIE |
1543                                ADM8211_IER_TDUIE | ADM8211_IER_GPTIE);
1544         adm8211_update_mode(dev);
1545         ADM8211_CSR_WRITE(RDR, 0);
1546
1547         adm8211_set_interval(dev, 100, 10);
1548         return 0;
1549
1550 fail:
1551         return retval;
1552 }
1553
1554 static void adm8211_stop(struct ieee80211_hw *dev)
1555 {
1556         struct adm8211_priv *priv = dev->priv;
1557
1558         priv->nar = 0;
1559         ADM8211_CSR_WRITE(NAR, 0);
1560         ADM8211_CSR_WRITE(IER, 0);
1561         ADM8211_CSR_READ(NAR);
1562
1563         free_irq(priv->pdev->irq, dev);
1564
1565         adm8211_free_rings(dev);
1566 }
1567
1568 static void adm8211_calc_durations(int *dur, int *plcp, size_t payload_len, int len,
1569                                    int plcp_signal, int short_preamble)
1570 {
1571         /* Alternative calculation from NetBSD: */
1572
1573 /* IEEE 802.11b durations for DSSS PHY in microseconds */
1574 #define IEEE80211_DUR_DS_LONG_PREAMBLE  144
1575 #define IEEE80211_DUR_DS_SHORT_PREAMBLE 72
1576 #define IEEE80211_DUR_DS_FAST_PLCPHDR   24
1577 #define IEEE80211_DUR_DS_SLOW_PLCPHDR   48
1578 #define IEEE80211_DUR_DS_SLOW_ACK       112
1579 #define IEEE80211_DUR_DS_FAST_ACK       56
1580 #define IEEE80211_DUR_DS_SLOW_CTS       112
1581 #define IEEE80211_DUR_DS_FAST_CTS       56
1582 #define IEEE80211_DUR_DS_SLOT           20
1583 #define IEEE80211_DUR_DS_SIFS           10
1584
1585         int remainder;
1586
1587         *dur = (80 * (24 + payload_len) + plcp_signal - 1)
1588                 / plcp_signal;
1589
1590         if (plcp_signal <= PLCP_SIGNAL_2M)
1591                 /* 1-2Mbps WLAN: send ACK/CTS at 1Mbps */
1592                 *dur += 3 * (IEEE80211_DUR_DS_SIFS +
1593                              IEEE80211_DUR_DS_SHORT_PREAMBLE +
1594                              IEEE80211_DUR_DS_FAST_PLCPHDR) +
1595                              IEEE80211_DUR_DS_SLOW_CTS + IEEE80211_DUR_DS_SLOW_ACK;
1596         else
1597                 /* 5-11Mbps WLAN: send ACK/CTS at 2Mbps */
1598                 *dur += 3 * (IEEE80211_DUR_DS_SIFS +
1599                              IEEE80211_DUR_DS_SHORT_PREAMBLE +
1600                              IEEE80211_DUR_DS_FAST_PLCPHDR) +
1601                              IEEE80211_DUR_DS_FAST_CTS + IEEE80211_DUR_DS_FAST_ACK;
1602
1603         /* lengthen duration if long preamble */
1604         if (!short_preamble)
1605                 *dur += 3 * (IEEE80211_DUR_DS_LONG_PREAMBLE -
1606                              IEEE80211_DUR_DS_SHORT_PREAMBLE) +
1607                         3 * (IEEE80211_DUR_DS_SLOW_PLCPHDR -
1608                              IEEE80211_DUR_DS_FAST_PLCPHDR);
1609
1610
1611         *plcp = (80 * len) / plcp_signal;
1612         remainder = (80 * len) % plcp_signal;
1613         if (plcp_signal == PLCP_SIGNAL_11M &&
1614             remainder <= 30 && remainder > 0)
1615                 *plcp = (*plcp | 0x8000) + 1;
1616         else if (remainder)
1617                 (*plcp)++;
1618 }
1619
1620 /* Transmit skb w/adm8211_tx_hdr (802.11 header created by hardware) */
1621 static void adm8211_tx_raw(struct ieee80211_hw *dev, struct sk_buff *skb,
1622                            u16 plcp_signal,
1623                            struct ieee80211_tx_control *control,
1624                            size_t hdrlen)
1625 {
1626         struct adm8211_priv *priv = dev->priv;
1627         unsigned long flags;
1628         dma_addr_t mapping;
1629         unsigned int entry;
1630         u32 flag;
1631
1632         mapping = pci_map_single(priv->pdev, skb->data, skb->len,
1633                                  PCI_DMA_TODEVICE);
1634
1635         spin_lock_irqsave(&priv->lock, flags);
1636
1637         if (priv->cur_tx - priv->dirty_tx == priv->tx_ring_size / 2)
1638                 flag = TDES1_CONTROL_IC | TDES1_CONTROL_LS | TDES1_CONTROL_FS;
1639         else
1640                 flag = TDES1_CONTROL_LS | TDES1_CONTROL_FS;
1641
1642         if (priv->cur_tx - priv->dirty_tx == priv->tx_ring_size - 2)
1643                 ieee80211_stop_queue(dev, 0);
1644
1645         entry = priv->cur_tx % priv->tx_ring_size;
1646
1647         priv->tx_buffers[entry].skb = skb;
1648         priv->tx_buffers[entry].mapping = mapping;
1649         memcpy(&priv->tx_buffers[entry].tx_control, control, sizeof(*control));
1650         priv->tx_buffers[entry].hdrlen = hdrlen;
1651         priv->tx_ring[entry].buffer1 = cpu_to_le32(mapping);
1652
1653         if (entry == priv->tx_ring_size - 1)
1654                 flag |= TDES1_CONTROL_TER;
1655         priv->tx_ring[entry].length = cpu_to_le32(flag | skb->len);
1656
1657         /* Set TX rate (SIGNAL field in PLCP PPDU format) */
1658         flag = TDES0_CONTROL_OWN | (plcp_signal << 20) | 8 /* ? */;
1659         priv->tx_ring[entry].status = cpu_to_le32(flag);
1660
1661         priv->cur_tx++;
1662
1663         spin_unlock_irqrestore(&priv->lock, flags);
1664
1665         /* Trigger transmit poll */
1666         ADM8211_CSR_WRITE(TDR, 0);
1667 }
1668
1669 /* Put adm8211_tx_hdr on skb and transmit */
1670 static int adm8211_tx(struct ieee80211_hw *dev, struct sk_buff *skb,
1671                       struct ieee80211_tx_control *control)
1672 {
1673         struct adm8211_tx_hdr *txhdr;
1674         u16 fc;
1675         size_t payload_len, hdrlen;
1676         int plcp, dur, len, plcp_signal, short_preamble;
1677         struct ieee80211_hdr *hdr;
1678
1679         if (control->tx_rate < 0) {
1680                 short_preamble = 1;
1681                 plcp_signal = -control->tx_rate;
1682         } else {
1683                 short_preamble = 0;
1684                 plcp_signal = control->tx_rate;
1685         }
1686
1687         hdr = (struct ieee80211_hdr *)skb->data;
1688         fc = le16_to_cpu(hdr->frame_control) & ~IEEE80211_FCTL_PROTECTED;
1689         hdrlen = ieee80211_get_hdrlen(fc);
1690         memcpy(skb->cb, skb->data, hdrlen);
1691         hdr = (struct ieee80211_hdr *)skb->cb;
1692         skb_pull(skb, hdrlen);
1693         payload_len = skb->len;
1694
1695         txhdr = (struct adm8211_tx_hdr *) skb_push(skb, sizeof(*txhdr));
1696         memset(txhdr, 0, sizeof(*txhdr));
1697         memcpy(txhdr->da, ieee80211_get_DA(hdr), ETH_ALEN);
1698         txhdr->signal = plcp_signal;
1699         txhdr->frame_body_size = cpu_to_le16(payload_len);
1700         txhdr->frame_control = hdr->frame_control;
1701
1702         len = hdrlen + payload_len + FCS_LEN;
1703         if (fc & IEEE80211_FCTL_PROTECTED)
1704                 len += 8;
1705
1706         txhdr->frag = cpu_to_le16(0x0FFF);
1707         adm8211_calc_durations(&dur, &plcp, payload_len,
1708                                len, plcp_signal, short_preamble);
1709         txhdr->plcp_frag_head_len = cpu_to_le16(plcp);
1710         txhdr->plcp_frag_tail_len = cpu_to_le16(plcp);
1711         txhdr->dur_frag_head = cpu_to_le16(dur);
1712         txhdr->dur_frag_tail = cpu_to_le16(dur);
1713
1714         txhdr->header_control = cpu_to_le16(ADM8211_TXHDRCTL_ENABLE_EXTEND_HEADER);
1715
1716         if (short_preamble)
1717                 txhdr->header_control |= cpu_to_le16(ADM8211_TXHDRCTL_SHORT_PREAMBLE);
1718
1719         if (control->flags & IEEE80211_TXCTL_USE_RTS_CTS)
1720                 txhdr->header_control |= cpu_to_le16(ADM8211_TXHDRCTL_ENABLE_RTS);
1721
1722         if (fc & IEEE80211_FCTL_PROTECTED)
1723                 txhdr->header_control |= cpu_to_le16(ADM8211_TXHDRCTL_ENABLE_WEP_ENGINE);
1724
1725         txhdr->retry_limit = control->retry_limit;
1726
1727         adm8211_tx_raw(dev, skb, plcp_signal, control, hdrlen);
1728
1729         return NETDEV_TX_OK;
1730 }
1731
1732 static int adm8211_alloc_rings(struct ieee80211_hw *dev)
1733 {
1734         struct adm8211_priv *priv = dev->priv;
1735         unsigned int ring_size;
1736
1737         priv->rx_buffers = kmalloc(sizeof(*priv->rx_buffers) * priv->rx_ring_size +
1738                                    sizeof(*priv->tx_buffers) * priv->tx_ring_size, GFP_KERNEL);
1739         if (!priv->rx_buffers)
1740                 return -ENOMEM;
1741
1742         priv->tx_buffers = (void *)priv->rx_buffers +
1743                            sizeof(*priv->rx_buffers) * priv->rx_ring_size;
1744
1745         /* Allocate TX/RX descriptors */
1746         ring_size = sizeof(struct adm8211_desc) * priv->rx_ring_size +
1747                     sizeof(struct adm8211_desc) * priv->tx_ring_size;
1748         priv->rx_ring = pci_alloc_consistent(priv->pdev, ring_size,
1749                                              &priv->rx_ring_dma);
1750
1751         if (!priv->rx_ring) {
1752                 kfree(priv->rx_buffers);
1753                 priv->rx_buffers = NULL;
1754                 priv->tx_buffers = NULL;
1755                 return -ENOMEM;
1756         }
1757
1758         priv->tx_ring = (struct adm8211_desc *)(priv->rx_ring +
1759                                                 priv->rx_ring_size);
1760         priv->tx_ring_dma = priv->rx_ring_dma +
1761                             sizeof(struct adm8211_desc) * priv->rx_ring_size;
1762
1763         return 0;
1764 }
1765
1766 static const struct ieee80211_ops adm8211_ops = {
1767         .tx                     = adm8211_tx,
1768         .start                  = adm8211_start,
1769         .stop                   = adm8211_stop,
1770         .add_interface          = adm8211_add_interface,
1771         .remove_interface       = adm8211_remove_interface,
1772         .config                 = adm8211_config,
1773         .config_interface       = adm8211_config_interface,
1774         .configure_filter       = adm8211_configure_filter,
1775         .get_stats              = adm8211_get_stats,
1776         .get_tx_stats           = adm8211_get_tx_stats,
1777         .get_tsf                = adm8211_get_tsft
1778 };
1779
1780 static int __devinit adm8211_probe(struct pci_dev *pdev,
1781                                    const struct pci_device_id *id)
1782 {
1783         struct ieee80211_hw *dev;
1784         struct adm8211_priv *priv;
1785         unsigned long mem_addr, mem_len;
1786         unsigned int io_addr, io_len;
1787         int err;
1788         u32 reg;
1789         u8 perm_addr[ETH_ALEN];
1790         DECLARE_MAC_BUF(mac);
1791
1792         err = pci_enable_device(pdev);
1793         if (err) {
1794                 printk(KERN_ERR "%s (adm8211): Cannot enable new PCI device\n",
1795                        pci_name(pdev));
1796                 return err;
1797         }
1798
1799         io_addr = pci_resource_start(pdev, 0);
1800         io_len = pci_resource_len(pdev, 0);
1801         mem_addr = pci_resource_start(pdev, 1);
1802         mem_len = pci_resource_len(pdev, 1);
1803         if (io_len < 256 || mem_len < 1024) {
1804                 printk(KERN_ERR "%s (adm8211): Too short PCI resources\n",
1805                        pci_name(pdev));
1806                 goto err_disable_pdev;
1807         }
1808
1809
1810         /* check signature */
1811         pci_read_config_dword(pdev, 0x80 /* CR32 */, &reg);
1812         if (reg != ADM8211_SIG1 && reg != ADM8211_SIG2) {
1813                 printk(KERN_ERR "%s (adm8211): Invalid signature (0x%x)\n",
1814                        pci_name(pdev), reg);
1815                 goto err_disable_pdev;
1816         }
1817
1818         err = pci_request_regions(pdev, "adm8211");
1819         if (err) {
1820                 printk(KERN_ERR "%s (adm8211): Cannot obtain PCI resources\n",
1821                        pci_name(pdev));
1822                 return err; /* someone else grabbed it? don't disable it */
1823         }
1824
1825         if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) ||
1826             pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) {
1827                 printk(KERN_ERR "%s (adm8211): No suitable DMA available\n",
1828                        pci_name(pdev));
1829                 goto err_free_reg;
1830         }
1831
1832         pci_set_master(pdev);
1833
1834         dev = ieee80211_alloc_hw(sizeof(*priv), &adm8211_ops);
1835         if (!dev) {
1836                 printk(KERN_ERR "%s (adm8211): ieee80211 alloc failed\n",
1837                        pci_name(pdev));
1838                 err = -ENOMEM;
1839                 goto err_free_reg;
1840         }
1841         priv = dev->priv;
1842         priv->pdev = pdev;
1843
1844         spin_lock_init(&priv->lock);
1845
1846         SET_IEEE80211_DEV(dev, &pdev->dev);
1847
1848         pci_set_drvdata(pdev, dev);
1849
1850         priv->map = pci_iomap(pdev, 1, mem_len);
1851         if (!priv->map)
1852                 priv->map = pci_iomap(pdev, 0, io_len);
1853
1854         if (!priv->map) {
1855                 printk(KERN_ERR "%s (adm8211): Cannot map device memory\n",
1856                        pci_name(pdev));
1857                 goto err_free_dev;
1858         }
1859
1860         priv->rx_ring_size = rx_ring_size;
1861         priv->tx_ring_size = tx_ring_size;
1862
1863         if (adm8211_alloc_rings(dev)) {
1864                 printk(KERN_ERR "%s (adm8211): Cannot allocate TX/RX ring\n",
1865                        pci_name(pdev));
1866                 goto err_iounmap;
1867         }
1868
1869         pci_read_config_byte(pdev, PCI_CLASS_REVISION, &priv->revid);
1870
1871         *(u32 *)perm_addr = le32_to_cpu((__force __le32)ADM8211_CSR_READ(PAR0));
1872         *(u16 *)&perm_addr[4] =
1873                 le16_to_cpu((__force __le16)ADM8211_CSR_READ(PAR1) & 0xFFFF);
1874
1875         if (!is_valid_ether_addr(perm_addr)) {
1876                 printk(KERN_WARNING "%s (adm8211): Invalid hwaddr in EEPROM!\n",
1877                        pci_name(pdev));
1878                 random_ether_addr(perm_addr);
1879         }
1880         SET_IEEE80211_PERM_ADDR(dev, perm_addr);
1881
1882         dev->extra_tx_headroom = sizeof(struct adm8211_tx_hdr);
1883         dev->flags = IEEE80211_HW_DEFAULT_REG_DOMAIN_CONFIGURED;
1884         /* IEEE80211_HW_RX_INCLUDES_FCS in promisc mode */
1885
1886         dev->channel_change_time = 1000;
1887         dev->max_rssi = 100;    /* FIXME: find better value */
1888
1889         priv->modes[0].mode = MODE_IEEE80211B;
1890         /* channel info filled in by adm8211_read_eeprom */
1891         memcpy(priv->rates, adm8211_rates, sizeof(adm8211_rates));
1892         priv->modes[0].num_rates = ARRAY_SIZE(adm8211_rates);
1893         priv->modes[0].rates = priv->rates;
1894
1895         dev->queues = 1; /* ADM8211C supports more, maybe ADM8211B too */
1896
1897         priv->retry_limit = 3;
1898         priv->ant_power = 0x40;
1899         priv->tx_power = 0x40;
1900         priv->lpf_cutoff = 0xFF;
1901         priv->lnags_threshold = 0xFF;
1902         priv->mode = IEEE80211_IF_TYPE_MNTR;
1903
1904         /* Power-on issue. EEPROM won't read correctly without */
1905         if (priv->revid >= ADM8211_REV_BA) {
1906                 ADM8211_CSR_WRITE(FRCTL, 0);
1907                 ADM8211_CSR_READ(FRCTL);
1908                 ADM8211_CSR_WRITE(FRCTL, 1);
1909                 ADM8211_CSR_READ(FRCTL);
1910                 msleep(100);
1911         }
1912
1913         err = adm8211_read_eeprom(dev);
1914         if (err) {
1915                 printk(KERN_ERR "%s (adm8211): Can't alloc eeprom buffer\n",
1916                        pci_name(pdev));
1917                 goto err_free_desc;
1918         }
1919
1920         priv->channel = priv->modes[0].channels[0].chan;
1921
1922         err = ieee80211_register_hwmode(dev, &priv->modes[0]);
1923         if (err) {
1924                 printk(KERN_ERR "%s (adm8211): Can't register hwmode\n",
1925                        pci_name(pdev));
1926                 goto err_free_desc;
1927         }
1928
1929         err = ieee80211_register_hw(dev);
1930         if (err) {
1931                 printk(KERN_ERR "%s (adm8211): Cannot register device\n",
1932                        pci_name(pdev));
1933                 goto err_free_desc;
1934         }
1935
1936         printk(KERN_INFO "%s: hwaddr %s, Rev 0x%02x\n",
1937                wiphy_name(dev->wiphy), print_mac(mac, dev->wiphy->perm_addr),
1938                priv->revid);
1939
1940         return 0;
1941
1942  err_free_desc:
1943         pci_free_consistent(pdev,
1944                             sizeof(struct adm8211_desc) * priv->rx_ring_size +
1945                             sizeof(struct adm8211_desc) * priv->tx_ring_size,
1946                             priv->rx_ring, priv->rx_ring_dma);
1947         kfree(priv->rx_buffers);
1948
1949  err_iounmap:
1950         pci_iounmap(pdev, priv->map);
1951
1952  err_free_dev:
1953         pci_set_drvdata(pdev, NULL);
1954         ieee80211_free_hw(dev);
1955
1956  err_free_reg:
1957         pci_release_regions(pdev);
1958
1959  err_disable_pdev:
1960         pci_disable_device(pdev);
1961         return err;
1962 }
1963
1964
1965 static void __devexit adm8211_remove(struct pci_dev *pdev)
1966 {
1967         struct ieee80211_hw *dev = pci_get_drvdata(pdev);
1968         struct adm8211_priv *priv;
1969
1970         if (!dev)
1971                 return;
1972
1973         ieee80211_unregister_hw(dev);
1974
1975         priv = dev->priv;
1976
1977         pci_free_consistent(pdev,
1978                             sizeof(struct adm8211_desc) * priv->rx_ring_size +
1979                             sizeof(struct adm8211_desc) * priv->tx_ring_size,
1980                             priv->rx_ring, priv->rx_ring_dma);
1981
1982         kfree(priv->rx_buffers);
1983         kfree(priv->eeprom);
1984         pci_iounmap(pdev, priv->map);
1985         pci_release_regions(pdev);
1986         pci_disable_device(pdev);
1987         ieee80211_free_hw(dev);
1988 }
1989
1990
1991 #ifdef CONFIG_PM
1992 static int adm8211_suspend(struct pci_dev *pdev, pm_message_t state)
1993 {
1994         struct ieee80211_hw *dev = pci_get_drvdata(pdev);
1995         struct adm8211_priv *priv = dev->priv;
1996
1997         if (priv->mode != IEEE80211_IF_TYPE_MNTR) {
1998                 ieee80211_stop_queues(dev);
1999                 adm8211_stop(dev);
2000         }
2001
2002         pci_save_state(pdev);
2003         pci_set_power_state(pdev, pci_choose_state(pdev, state));
2004         return 0;
2005 }
2006
2007 static int adm8211_resume(struct pci_dev *pdev)
2008 {
2009         struct ieee80211_hw *dev = pci_get_drvdata(pdev);
2010         struct adm8211_priv *priv = dev->priv;
2011
2012         pci_set_power_state(pdev, PCI_D0);
2013         pci_restore_state(pdev);
2014
2015         if (priv->mode != IEEE80211_IF_TYPE_MNTR) {
2016                 adm8211_start(dev);
2017                 ieee80211_start_queues(dev);
2018         }
2019
2020         return 0;
2021 }
2022 #endif /* CONFIG_PM */
2023
2024
2025 MODULE_DEVICE_TABLE(pci, adm8211_pci_id_table);
2026
2027 /* TODO: implement enable_wake */
2028 static struct pci_driver adm8211_driver = {
2029         .name           = "adm8211",
2030         .id_table       = adm8211_pci_id_table,
2031         .probe          = adm8211_probe,
2032         .remove         = __devexit_p(adm8211_remove),
2033 #ifdef CONFIG_PM
2034         .suspend        = adm8211_suspend,
2035         .resume         = adm8211_resume,
2036 #endif /* CONFIG_PM */
2037 };
2038
2039
2040
2041 static int __init adm8211_init(void)
2042 {
2043         return pci_register_driver(&adm8211_driver);
2044 }
2045
2046
2047 static void __exit adm8211_exit(void)
2048 {
2049         pci_unregister_driver(&adm8211_driver);
2050 }
2051
2052
2053 module_init(adm8211_init);
2054 module_exit(adm8211_exit);