2 * File: drivers/spi/bfin5xx_spi.c
4 * Bryan Wu <bryan.wu@analog.com>
6 * Luke Yang (Analog Devices Inc.)
8 * Created: March. 10th 2006
9 * Description: SPI controller driver for Blackfin BF5xx
10 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 * March 10, 2006 bfin5xx_spi.c Created. (Luke Yang)
14 * August 7, 2006 added full duplex mode (Axel Weiss & Luke Yang)
15 * July 17, 2007 add support for BF54x SPI0 controller (Bryan Wu)
16 * July 30, 2007 add platfrom_resource interface to support multi-port
17 * SPI controller (Bryan Wu)
19 * Copyright 2004-2007 Analog Devices Inc.
21 * This program is free software ; you can redistribute it and/or modify
22 * it under the terms of the GNU General Public License as published by
23 * the Free Software Foundation ; either version 2, or (at your option)
26 * This program is distributed in the hope that it will be useful,
27 * but WITHOUT ANY WARRANTY ; without even the implied warranty of
28 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
29 * GNU General Public License for more details.
31 * You should have received a copy of the GNU General Public License
32 * along with this program ; see the file COPYING.
33 * If not, write to the Free Software Foundation,
34 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
37 #include <linux/init.h>
38 #include <linux/module.h>
39 #include <linux/delay.h>
40 #include <linux/device.h>
42 #include <linux/ioport.h>
43 #include <linux/irq.h>
44 #include <linux/errno.h>
45 #include <linux/interrupt.h>
46 #include <linux/platform_device.h>
47 #include <linux/dma-mapping.h>
48 #include <linux/spi/spi.h>
49 #include <linux/workqueue.h>
52 #include <asm/portmux.h>
53 #include <asm/bfin5xx_spi.h>
55 #define DRV_NAME "bfin-spi"
56 #define DRV_AUTHOR "Bryan Wu, Luke Yang"
57 #define DRV_DESC "Blackfin BF5xx on-chip SPI Contoller Driver"
58 #define DRV_VERSION "1.0"
60 MODULE_AUTHOR(DRV_AUTHOR);
61 MODULE_DESCRIPTION(DRV_DESC);
62 MODULE_LICENSE("GPL");
64 #define IS_DMA_ALIGNED(x) (((u32)(x)&0x07)==0)
66 static u32 spi_dma_ch;
67 static u32 spi_regs_base;
69 #define DEFINE_SPI_REG(reg, off) \
70 static inline u16 read_##reg(void) \
71 { return bfin_read16(spi_regs_base + off); } \
72 static inline void write_##reg(u16 v) \
73 {bfin_write16(spi_regs_base + off, v); }
75 DEFINE_SPI_REG(CTRL, 0x00)
76 DEFINE_SPI_REG(FLAG, 0x04)
77 DEFINE_SPI_REG(STAT, 0x08)
78 DEFINE_SPI_REG(TDBR, 0x0C)
79 DEFINE_SPI_REG(RDBR, 0x10)
80 DEFINE_SPI_REG(BAUD, 0x14)
81 DEFINE_SPI_REG(SHAW, 0x18)
82 #define START_STATE ((void*)0)
83 #define RUNNING_STATE ((void*)1)
84 #define DONE_STATE ((void*)2)
85 #define ERROR_STATE ((void*)-1)
86 #define QUEUE_RUNNING 0
87 #define QUEUE_STOPPED 1
91 /* Driver model hookup */
92 struct platform_device *pdev;
94 /* SPI framework hookup */
95 struct spi_master *master;
98 struct bfin5xx_spi_master *master_info;
100 /* Driver message queue */
101 struct workqueue_struct *workqueue;
102 struct work_struct pump_messages;
104 struct list_head queue;
108 /* Message Transfer pump */
109 struct tasklet_struct pump_transfers;
111 /* Current message transfer state info */
112 struct spi_message *cur_msg;
113 struct spi_transfer *cur_transfer;
114 struct chip_data *cur_chip;
128 void (*write) (struct driver_data *);
129 void (*read) (struct driver_data *);
130 void (*duplex) (struct driver_data *);
140 u8 width; /* 0 or 1 */
142 u8 bits_per_word; /* 8 or 16 */
143 u8 cs_change_per_word;
145 void (*write) (struct driver_data *);
146 void (*read) (struct driver_data *);
147 void (*duplex) (struct driver_data *);
150 static void bfin_spi_enable(struct driver_data *drv_data)
155 write_CTRL(cr | BIT_CTL_ENABLE);
158 static void bfin_spi_disable(struct driver_data *drv_data)
163 write_CTRL(cr & (~BIT_CTL_ENABLE));
166 /* Caculate the SPI_BAUD register value based on input HZ */
167 static u16 hz_to_spi_baud(u32 speed_hz)
169 u_long sclk = get_sclk();
170 u16 spi_baud = (sclk / (2 * speed_hz));
172 if ((sclk % (2 * speed_hz)) > 0)
178 static int flush(struct driver_data *drv_data)
180 unsigned long limit = loops_per_jiffy << 1;
182 /* wait for stop and clear stat */
183 while (!(read_STAT() & BIT_STAT_SPIF) && limit--)
186 write_STAT(BIT_STAT_CLR);
191 /* Chip select operation functions for cs_change flag */
192 static void cs_active(struct chip_data *chip)
194 u16 flag = read_FLAG();
197 flag &= ~(chip->flag << 8);
202 static void cs_deactive(struct chip_data *chip)
204 u16 flag = read_FLAG();
206 flag |= (chip->flag << 8);
211 #define MAX_SPI_SSEL 7
213 /* stop controller and re-config current chip*/
214 static int restore_state(struct driver_data *drv_data)
216 struct chip_data *chip = drv_data->cur_chip;
219 /* Clear status and disable clock */
220 write_STAT(BIT_STAT_CLR);
221 bfin_spi_disable(drv_data);
222 dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");
224 /* Load the registers */
225 write_CTRL(chip->ctl_reg);
226 write_BAUD(chip->baud);
230 dev_dbg(&drv_data->pdev->dev,
231 ": request chip select number %d failed\n",
232 chip->chip_select_num);
237 /* used to kick off transfer in rx mode */
238 static unsigned short dummy_read(void)
245 static void null_writer(struct driver_data *drv_data)
247 u8 n_bytes = drv_data->n_bytes;
249 while (drv_data->tx < drv_data->tx_end) {
251 while ((read_STAT() & BIT_STAT_TXS))
253 drv_data->tx += n_bytes;
257 static void null_reader(struct driver_data *drv_data)
259 u8 n_bytes = drv_data->n_bytes;
262 while (drv_data->rx < drv_data->rx_end) {
263 while (!(read_STAT() & BIT_STAT_RXS))
266 drv_data->rx += n_bytes;
270 static void u8_writer(struct driver_data *drv_data)
272 dev_dbg(&drv_data->pdev->dev,
273 "cr8-s is 0x%x\n", read_STAT());
274 while (drv_data->tx < drv_data->tx_end) {
275 write_TDBR(*(u8 *) (drv_data->tx));
276 while (read_STAT() & BIT_STAT_TXS)
281 /* poll for SPI completion before returning */
282 while (!(read_STAT() & BIT_STAT_SPIF))
286 static void u8_cs_chg_writer(struct driver_data *drv_data)
288 struct chip_data *chip = drv_data->cur_chip;
290 while (drv_data->tx < drv_data->tx_end) {
293 write_TDBR(*(u8 *) (drv_data->tx));
294 while (read_STAT() & BIT_STAT_TXS)
296 while (!(read_STAT() & BIT_STAT_SPIF))
300 if (chip->cs_chg_udelay)
301 udelay(chip->cs_chg_udelay);
308 static void u8_reader(struct driver_data *drv_data)
310 dev_dbg(&drv_data->pdev->dev,
311 "cr-8 is 0x%x\n", read_STAT());
313 /* clear TDBR buffer before read(else it will be shifted out) */
317 while (drv_data->rx < drv_data->rx_end - 1) {
318 while (!(read_STAT() & BIT_STAT_RXS))
320 *(u8 *) (drv_data->rx) = read_RDBR();
324 while (!(read_STAT() & BIT_STAT_RXS))
326 *(u8 *) (drv_data->rx) = read_SHAW();
330 static void u8_cs_chg_reader(struct driver_data *drv_data)
332 struct chip_data *chip = drv_data->cur_chip;
334 while (drv_data->rx < drv_data->rx_end) {
337 read_RDBR(); /* kick off */
338 while (!(read_STAT() & BIT_STAT_RXS))
340 while (!(read_STAT() & BIT_STAT_SPIF))
342 *(u8 *) (drv_data->rx) = read_SHAW();
345 if (chip->cs_chg_udelay)
346 udelay(chip->cs_chg_udelay);
353 static void u8_duplex(struct driver_data *drv_data)
355 /* in duplex mode, clk is triggered by writing of TDBR */
356 while (drv_data->rx < drv_data->rx_end) {
357 write_TDBR(*(u8 *) (drv_data->tx));
358 while (!(read_STAT() & BIT_STAT_SPIF))
360 while (!(read_STAT() & BIT_STAT_RXS))
362 *(u8 *) (drv_data->rx) = read_RDBR();
368 static void u8_cs_chg_duplex(struct driver_data *drv_data)
370 struct chip_data *chip = drv_data->cur_chip;
372 while (drv_data->rx < drv_data->rx_end) {
376 write_TDBR(*(u8 *) (drv_data->tx));
377 while (!(read_STAT() & BIT_STAT_SPIF))
379 while (!(read_STAT() & BIT_STAT_RXS))
381 *(u8 *) (drv_data->rx) = read_RDBR();
384 if (chip->cs_chg_udelay)
385 udelay(chip->cs_chg_udelay);
392 static void u16_writer(struct driver_data *drv_data)
394 dev_dbg(&drv_data->pdev->dev,
395 "cr16 is 0x%x\n", read_STAT());
397 while (drv_data->tx < drv_data->tx_end) {
398 write_TDBR(*(u16 *) (drv_data->tx));
399 while ((read_STAT() & BIT_STAT_TXS))
404 /* poll for SPI completion before returning */
405 while (!(read_STAT() & BIT_STAT_SPIF))
409 static void u16_cs_chg_writer(struct driver_data *drv_data)
411 struct chip_data *chip = drv_data->cur_chip;
413 while (drv_data->tx < drv_data->tx_end) {
416 write_TDBR(*(u16 *) (drv_data->tx));
417 while ((read_STAT() & BIT_STAT_TXS))
419 while (!(read_STAT() & BIT_STAT_SPIF))
423 if (chip->cs_chg_udelay)
424 udelay(chip->cs_chg_udelay);
430 static void u16_reader(struct driver_data *drv_data)
432 dev_dbg(&drv_data->pdev->dev,
433 "cr-16 is 0x%x\n", read_STAT());
436 while (drv_data->rx < (drv_data->rx_end - 2)) {
437 while (!(read_STAT() & BIT_STAT_RXS))
439 *(u16 *) (drv_data->rx) = read_RDBR();
443 while (!(read_STAT() & BIT_STAT_RXS))
445 *(u16 *) (drv_data->rx) = read_SHAW();
449 static void u16_cs_chg_reader(struct driver_data *drv_data)
451 struct chip_data *chip = drv_data->cur_chip;
453 while (drv_data->rx < drv_data->rx_end) {
456 read_RDBR(); /* kick off */
457 while (!(read_STAT() & BIT_STAT_RXS))
459 while (!(read_STAT() & BIT_STAT_SPIF))
461 *(u16 *) (drv_data->rx) = read_SHAW();
464 if (chip->cs_chg_udelay)
465 udelay(chip->cs_chg_udelay);
471 static void u16_duplex(struct driver_data *drv_data)
473 /* in duplex mode, clk is triggered by writing of TDBR */
474 while (drv_data->tx < drv_data->tx_end) {
475 write_TDBR(*(u16 *) (drv_data->tx));
476 while (!(read_STAT() & BIT_STAT_SPIF))
478 while (!(read_STAT() & BIT_STAT_RXS))
480 *(u16 *) (drv_data->rx) = read_RDBR();
486 static void u16_cs_chg_duplex(struct driver_data *drv_data)
488 struct chip_data *chip = drv_data->cur_chip;
490 while (drv_data->tx < drv_data->tx_end) {
493 write_TDBR(*(u16 *) (drv_data->tx));
494 while (!(read_STAT() & BIT_STAT_SPIF))
496 while (!(read_STAT() & BIT_STAT_RXS))
498 *(u16 *) (drv_data->rx) = read_RDBR();
501 if (chip->cs_chg_udelay)
502 udelay(chip->cs_chg_udelay);
509 /* test if ther is more transfer to be done */
510 static void *next_transfer(struct driver_data *drv_data)
512 struct spi_message *msg = drv_data->cur_msg;
513 struct spi_transfer *trans = drv_data->cur_transfer;
515 /* Move to next transfer */
516 if (trans->transfer_list.next != &msg->transfers) {
517 drv_data->cur_transfer =
518 list_entry(trans->transfer_list.next,
519 struct spi_transfer, transfer_list);
520 return RUNNING_STATE;
526 * caller already set message->status;
527 * dma and pio irqs are blocked give finished message back
529 static void giveback(struct driver_data *drv_data)
531 struct chip_data *chip = drv_data->cur_chip;
532 struct spi_transfer *last_transfer;
534 struct spi_message *msg;
536 spin_lock_irqsave(&drv_data->lock, flags);
537 msg = drv_data->cur_msg;
538 drv_data->cur_msg = NULL;
539 drv_data->cur_transfer = NULL;
540 drv_data->cur_chip = NULL;
541 queue_work(drv_data->workqueue, &drv_data->pump_messages);
542 spin_unlock_irqrestore(&drv_data->lock, flags);
544 last_transfer = list_entry(msg->transfers.prev,
545 struct spi_transfer, transfer_list);
549 /* disable chip select signal. And not stop spi in autobuffer mode */
550 if (drv_data->tx_dma != 0xFFFF) {
552 bfin_spi_disable(drv_data);
555 if (!drv_data->cs_change)
559 msg->complete(msg->context);
562 static irqreturn_t dma_irq_handler(int irq, void *dev_id)
564 struct driver_data *drv_data = (struct driver_data *)dev_id;
565 struct spi_message *msg = drv_data->cur_msg;
566 struct chip_data *chip = drv_data->cur_chip;
568 dev_dbg(&drv_data->pdev->dev, "in dma_irq_handler\n");
569 clear_dma_irqstat(spi_dma_ch);
571 /* Wait for DMA to complete */
572 while (get_dma_curr_irqstat(spi_dma_ch) & DMA_RUN)
576 * wait for the last transaction shifted out. HRM states:
577 * at this point there may still be data in the SPI DMA FIFO waiting
578 * to be transmitted ... software needs to poll TXS in the SPI_STAT
579 * register until it goes low for 2 successive reads
581 if (drv_data->tx != NULL) {
582 while ((read_STAT() & TXS) ||
587 while (!(read_STAT() & SPIF))
590 bfin_spi_disable(drv_data);
592 msg->actual_length += drv_data->len_in_bytes;
594 if (drv_data->cs_change)
597 /* Move to next transfer */
598 msg->state = next_transfer(drv_data);
600 /* Schedule transfer tasklet */
601 tasklet_schedule(&drv_data->pump_transfers);
603 /* free the irq handler before next transfer */
604 dev_dbg(&drv_data->pdev->dev,
605 "disable dma channel irq%d\n",
607 dma_disable_irq(spi_dma_ch);
612 static void pump_transfers(unsigned long data)
614 struct driver_data *drv_data = (struct driver_data *)data;
615 struct spi_message *message = NULL;
616 struct spi_transfer *transfer = NULL;
617 struct spi_transfer *previous = NULL;
618 struct chip_data *chip = NULL;
620 u16 cr, dma_width, dma_config;
621 u32 tranf_success = 1;
623 /* Get current state information */
624 message = drv_data->cur_msg;
625 transfer = drv_data->cur_transfer;
626 chip = drv_data->cur_chip;
628 * if msg is error or done, report it back using complete() callback
631 /* Handle for abort */
632 if (message->state == ERROR_STATE) {
633 message->status = -EIO;
638 /* Handle end of message */
639 if (message->state == DONE_STATE) {
645 /* Delay if requested at end of transfer */
646 if (message->state == RUNNING_STATE) {
647 previous = list_entry(transfer->transfer_list.prev,
648 struct spi_transfer, transfer_list);
649 if (previous->delay_usecs)
650 udelay(previous->delay_usecs);
653 /* Setup the transfer state based on the type of transfer */
654 if (flush(drv_data) == 0) {
655 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
656 message->status = -EIO;
661 if (transfer->tx_buf != NULL) {
662 drv_data->tx = (void *)transfer->tx_buf;
663 drv_data->tx_end = drv_data->tx + transfer->len;
664 dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n",
665 transfer->tx_buf, drv_data->tx_end);
670 if (transfer->rx_buf != NULL) {
671 drv_data->rx = transfer->rx_buf;
672 drv_data->rx_end = drv_data->rx + transfer->len;
673 dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n",
674 transfer->rx_buf, drv_data->rx_end);
679 drv_data->rx_dma = transfer->rx_dma;
680 drv_data->tx_dma = transfer->tx_dma;
681 drv_data->len_in_bytes = transfer->len;
682 drv_data->cs_change = transfer->cs_change;
685 if (width == CFG_SPI_WORDSIZE16) {
686 drv_data->len = (transfer->len) >> 1;
688 drv_data->len = transfer->len;
690 drv_data->write = drv_data->tx ? chip->write : null_writer;
691 drv_data->read = drv_data->rx ? chip->read : null_reader;
692 drv_data->duplex = chip->duplex ? chip->duplex : null_writer;
693 dev_dbg(&drv_data->pdev->dev, "transfer: ",
694 "drv_data->write is %p, chip->write is %p, null_wr is %p\n",
695 drv_data->write, chip->write, null_writer);
697 /* speed and width has been set on per message */
698 message->state = RUNNING_STATE;
701 /* restore spi status for each spi transfer */
702 if (transfer->speed_hz) {
703 write_BAUD(hz_to_spi_baud(transfer->speed_hz));
705 write_BAUD(chip->baud);
709 dev_dbg(&drv_data->pdev->dev,
710 "now pumping a transfer: width is %d, len is %d\n",
711 width, transfer->len);
714 * Try to map dma buffer and do a dma transfer if
715 * successful use different way to r/w according to
716 * drv_data->cur_chip->enable_dma
718 if (drv_data->cur_chip->enable_dma && drv_data->len > 6) {
720 write_STAT(BIT_STAT_CLR);
721 disable_dma(spi_dma_ch);
722 clear_dma_irqstat(spi_dma_ch);
723 bfin_spi_disable(drv_data);
725 /* config dma channel */
726 dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n");
727 if (width == CFG_SPI_WORDSIZE16) {
728 set_dma_x_count(spi_dma_ch, drv_data->len);
729 set_dma_x_modify(spi_dma_ch, 2);
730 dma_width = WDSIZE_16;
732 set_dma_x_count(spi_dma_ch, drv_data->len);
733 set_dma_x_modify(spi_dma_ch, 1);
734 dma_width = WDSIZE_8;
737 /* set transfer width,direction. And enable spi */
738 cr = (read_CTRL() & (~BIT_CTL_TIMOD));
740 /* dirty hack for autobuffer DMA mode */
741 if (drv_data->tx_dma == 0xFFFF) {
742 dev_dbg(&drv_data->pdev->dev,
743 "doing autobuffer DMA out.\n");
745 /* no irq in autobuffer mode */
747 (DMAFLOW_AUTO | RESTART | dma_width | DI_EN);
748 set_dma_config(spi_dma_ch, dma_config);
749 set_dma_start_addr(spi_dma_ch,
750 (unsigned long)drv_data->tx);
751 enable_dma(spi_dma_ch);
752 write_CTRL(cr | CFG_SPI_DMAWRITE | (width << 8) |
753 (CFG_SPI_ENABLE << 14));
755 /* just return here, there can only be one transfer in this mode */
761 /* In dma mode, rx or tx must be NULL in one transfer */
762 if (drv_data->rx != NULL) {
763 /* set transfer mode, and enable SPI */
764 dev_dbg(&drv_data->pdev->dev, "doing DMA in.\n");
766 /* disable SPI before write to TDBR */
767 write_CTRL(cr & ~BIT_CTL_ENABLE);
769 /* clear tx reg soformer data is not shifted out */
772 set_dma_x_count(spi_dma_ch, drv_data->len);
775 dma_enable_irq(spi_dma_ch);
776 dma_config = (WNR | RESTART | dma_width | DI_EN);
777 set_dma_config(spi_dma_ch, dma_config);
778 set_dma_start_addr(spi_dma_ch,
779 (unsigned long)drv_data->rx);
780 enable_dma(spi_dma_ch);
783 CFG_SPI_DMAREAD | (width << 8) | (CFG_SPI_ENABLE <<
785 /* set transfer mode, and enable SPI */
787 } else if (drv_data->tx != NULL) {
788 dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n");
791 dma_enable_irq(spi_dma_ch);
792 dma_config = (RESTART | dma_width | DI_EN);
793 set_dma_config(spi_dma_ch, dma_config);
794 set_dma_start_addr(spi_dma_ch,
795 (unsigned long)drv_data->tx);
796 enable_dma(spi_dma_ch);
798 write_CTRL(cr | CFG_SPI_DMAWRITE | (width << 8) |
799 (CFG_SPI_ENABLE << 14));
803 /* IO mode write then read */
804 dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
806 write_STAT(BIT_STAT_CLR);
808 if (drv_data->tx != NULL && drv_data->rx != NULL) {
809 /* full duplex mode */
810 BUG_ON((drv_data->tx_end - drv_data->tx) !=
811 (drv_data->rx_end - drv_data->rx));
812 cr = (read_CTRL() & (~BIT_CTL_TIMOD));
813 cr |= CFG_SPI_WRITE | (width << 8) |
814 (CFG_SPI_ENABLE << 14);
815 dev_dbg(&drv_data->pdev->dev,
816 "IO duplex: cr is 0x%x\n", cr);
820 drv_data->duplex(drv_data);
822 if (drv_data->tx != drv_data->tx_end)
824 } else if (drv_data->tx != NULL) {
825 /* write only half duplex */
826 cr = (read_CTRL() & (~BIT_CTL_TIMOD));
827 cr |= CFG_SPI_WRITE | (width << 8) |
828 (CFG_SPI_ENABLE << 14);
829 dev_dbg(&drv_data->pdev->dev,
830 "IO write: cr is 0x%x\n", cr);
834 drv_data->write(drv_data);
836 if (drv_data->tx != drv_data->tx_end)
838 } else if (drv_data->rx != NULL) {
839 /* read only half duplex */
840 cr = (read_CTRL() & (~BIT_CTL_TIMOD));
841 cr |= CFG_SPI_READ | (width << 8) |
842 (CFG_SPI_ENABLE << 14);
843 dev_dbg(&drv_data->pdev->dev,
844 "IO read: cr is 0x%x\n", cr);
848 drv_data->read(drv_data);
849 if (drv_data->rx != drv_data->rx_end)
853 if (!tranf_success) {
854 dev_dbg(&drv_data->pdev->dev,
855 "IO write error!\n");
856 message->state = ERROR_STATE;
858 /* Update total byte transfered */
859 message->actual_length += drv_data->len;
861 if (drv_data->cs_change)
864 /* Move to next transfer of this msg */
865 message->state = next_transfer(drv_data);
868 /* Schedule next transfer tasklet */
869 tasklet_schedule(&drv_data->pump_transfers);
874 /* pop a msg from queue and kick off real transfer */
875 static void pump_messages(struct work_struct *work)
877 struct driver_data *drv_data;
880 drv_data = container_of(work, struct driver_data, pump_messages);
882 /* Lock queue and check for queue work */
883 spin_lock_irqsave(&drv_data->lock, flags);
884 if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
885 /* pumper kicked off but no work to do */
887 spin_unlock_irqrestore(&drv_data->lock, flags);
891 /* Make sure we are not already running a message */
892 if (drv_data->cur_msg) {
893 spin_unlock_irqrestore(&drv_data->lock, flags);
897 /* Extract head of queue */
898 drv_data->cur_msg = list_entry(drv_data->queue.next,
899 struct spi_message, queue);
901 /* Setup the SSP using the per chip configuration */
902 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
903 if (restore_state(drv_data)) {
904 spin_unlock_irqrestore(&drv_data->lock, flags);
908 list_del_init(&drv_data->cur_msg->queue);
910 /* Initial message state */
911 drv_data->cur_msg->state = START_STATE;
912 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
913 struct spi_transfer, transfer_list);
915 dev_dbg(&drv_data->pdev->dev, "got a message to pump, "
916 "state is set to: baud %d, flag 0x%x, ctl 0x%x\n",
917 drv_data->cur_chip->baud, drv_data->cur_chip->flag,
918 drv_data->cur_chip->ctl_reg);
920 dev_dbg(&drv_data->pdev->dev,
921 "the first transfer len is %d\n",
922 drv_data->cur_transfer->len);
924 /* Mark as busy and launch transfers */
925 tasklet_schedule(&drv_data->pump_transfers);
928 spin_unlock_irqrestore(&drv_data->lock, flags);
932 * got a msg to transfer, queue it in drv_data->queue.
933 * And kick off message pumper
935 static int transfer(struct spi_device *spi, struct spi_message *msg)
937 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
940 spin_lock_irqsave(&drv_data->lock, flags);
942 if (drv_data->run == QUEUE_STOPPED) {
943 spin_unlock_irqrestore(&drv_data->lock, flags);
947 msg->actual_length = 0;
948 msg->status = -EINPROGRESS;
949 msg->state = START_STATE;
951 dev_dbg(&spi->dev, "adding an msg in transfer() \n");
952 list_add_tail(&msg->queue, &drv_data->queue);
954 if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
955 queue_work(drv_data->workqueue, &drv_data->pump_messages);
957 spin_unlock_irqrestore(&drv_data->lock, flags);
962 #define MAX_SPI_SSEL 7
964 static u16 ssel[3][MAX_SPI_SSEL] = {
965 {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3,
966 P_SPI0_SSEL4, P_SPI0_SSEL5,
967 P_SPI0_SSEL6, P_SPI0_SSEL7},
969 {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3,
970 P_SPI1_SSEL4, P_SPI1_SSEL5,
971 P_SPI1_SSEL6, P_SPI1_SSEL7},
973 {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3,
974 P_SPI2_SSEL4, P_SPI2_SSEL5,
975 P_SPI2_SSEL6, P_SPI2_SSEL7},
978 /* first setup for new devices */
979 static int setup(struct spi_device *spi)
981 struct bfin5xx_spi_chip *chip_info = NULL;
982 struct chip_data *chip;
983 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
986 /* Abort device setup if requested features are not supported */
987 if (spi->mode & ~(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST)) {
988 dev_err(&spi->dev, "requested mode not fully supported\n");
992 /* Zero (the default) here means 8 bits */
993 if (!spi->bits_per_word)
994 spi->bits_per_word = 8;
996 if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
999 /* Only alloc (or use chip_info) on first setup */
1000 chip = spi_get_ctldata(spi);
1002 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1006 chip->enable_dma = 0;
1007 chip_info = spi->controller_data;
1010 /* chip_info isn't always needed */
1012 /* Make sure people stop trying to set fields via ctl_reg
1013 * when they should actually be using common SPI framework.
1014 * Currently we let through: WOM EMISO PSSE GM SZ TIMOD.
1015 * Not sure if a user actually needs/uses any of these,
1016 * but let's assume (for now) they do.
1018 if (chip_info->ctl_reg & (SPE|MSTR|CPOL|CPHA|LSBF|SIZE)) {
1019 dev_err(&spi->dev, "do not set bits in ctl_reg "
1020 "that the SPI framework manages\n");
1024 chip->enable_dma = chip_info->enable_dma != 0
1025 && drv_data->master_info->enable_dma;
1026 chip->ctl_reg = chip_info->ctl_reg;
1027 chip->bits_per_word = chip_info->bits_per_word;
1028 chip->cs_change_per_word = chip_info->cs_change_per_word;
1029 chip->cs_chg_udelay = chip_info->cs_chg_udelay;
1032 /* translate common spi framework into our register */
1033 if (spi->mode & SPI_CPOL)
1034 chip->ctl_reg |= CPOL;
1035 if (spi->mode & SPI_CPHA)
1036 chip->ctl_reg |= CPHA;
1037 if (spi->mode & SPI_LSB_FIRST)
1038 chip->ctl_reg |= LSBF;
1039 /* we dont support running in slave mode (yet?) */
1040 chip->ctl_reg |= MSTR;
1043 * if any one SPI chip is registered and wants DMA, request the
1044 * DMA channel for it
1046 if (chip->enable_dma && !dma_requested) {
1047 /* register dma irq handler */
1048 if (request_dma(spi_dma_ch, "BF53x_SPI_DMA") < 0) {
1050 "Unable to request BlackFin SPI DMA channel\n");
1053 if (set_dma_callback(spi_dma_ch, (void *)dma_irq_handler,
1055 dev_dbg(&spi->dev, "Unable to set dma callback\n");
1058 dma_disable_irq(spi_dma_ch);
1063 * Notice: for blackfin, the speed_hz is the value of register
1064 * SPI_BAUD, not the real baudrate
1066 chip->baud = hz_to_spi_baud(spi->max_speed_hz);
1067 spi_flg = ~(1 << (spi->chip_select));
1068 chip->flag = ((u16) spi_flg << 8) | (1 << (spi->chip_select));
1069 chip->chip_select_num = spi->chip_select;
1071 switch (chip->bits_per_word) {
1074 chip->width = CFG_SPI_WORDSIZE8;
1075 chip->read = chip->cs_change_per_word ?
1076 u8_cs_chg_reader : u8_reader;
1077 chip->write = chip->cs_change_per_word ?
1078 u8_cs_chg_writer : u8_writer;
1079 chip->duplex = chip->cs_change_per_word ?
1080 u8_cs_chg_duplex : u8_duplex;
1085 chip->width = CFG_SPI_WORDSIZE16;
1086 chip->read = chip->cs_change_per_word ?
1087 u16_cs_chg_reader : u16_reader;
1088 chip->write = chip->cs_change_per_word ?
1089 u16_cs_chg_writer : u16_writer;
1090 chip->duplex = chip->cs_change_per_word ?
1091 u16_cs_chg_duplex : u16_duplex;
1095 dev_err(&spi->dev, "%d bits_per_word is not supported\n",
1096 chip->bits_per_word);
1101 dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n",
1102 spi->modalias, chip->width, chip->enable_dma);
1103 dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
1104 chip->ctl_reg, chip->flag);
1106 spi_set_ctldata(spi, chip);
1108 dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num);
1109 if ((chip->chip_select_num > 0)
1110 && (chip->chip_select_num <= spi->master->num_chipselect))
1111 peripheral_request(ssel[spi->master->bus_num]
1112 [chip->chip_select_num-1], DRV_NAME);
1118 * callback for spi framework.
1119 * clean driver specific data
1121 static void cleanup(struct spi_device *spi)
1123 struct chip_data *chip = spi_get_ctldata(spi);
1125 if ((chip->chip_select_num > 0)
1126 && (chip->chip_select_num <= spi->master->num_chipselect))
1127 peripheral_free(ssel[spi->master->bus_num]
1128 [chip->chip_select_num-1]);
1133 static inline int init_queue(struct driver_data *drv_data)
1135 INIT_LIST_HEAD(&drv_data->queue);
1136 spin_lock_init(&drv_data->lock);
1138 drv_data->run = QUEUE_STOPPED;
1141 /* init transfer tasklet */
1142 tasklet_init(&drv_data->pump_transfers,
1143 pump_transfers, (unsigned long)drv_data);
1145 /* init messages workqueue */
1146 INIT_WORK(&drv_data->pump_messages, pump_messages);
1147 drv_data->workqueue =
1148 create_singlethread_workqueue(drv_data->master->dev.parent->bus_id);
1149 if (drv_data->workqueue == NULL)
1155 static inline int start_queue(struct driver_data *drv_data)
1157 unsigned long flags;
1159 spin_lock_irqsave(&drv_data->lock, flags);
1161 if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1162 spin_unlock_irqrestore(&drv_data->lock, flags);
1166 drv_data->run = QUEUE_RUNNING;
1167 drv_data->cur_msg = NULL;
1168 drv_data->cur_transfer = NULL;
1169 drv_data->cur_chip = NULL;
1170 spin_unlock_irqrestore(&drv_data->lock, flags);
1172 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1177 static inline int stop_queue(struct driver_data *drv_data)
1179 unsigned long flags;
1180 unsigned limit = 500;
1183 spin_lock_irqsave(&drv_data->lock, flags);
1186 * This is a bit lame, but is optimized for the common execution path.
1187 * A wait_queue on the drv_data->busy could be used, but then the common
1188 * execution path (pump_messages) would be required to call wake_up or
1189 * friends on every SPI message. Do this instead
1191 drv_data->run = QUEUE_STOPPED;
1192 while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1193 spin_unlock_irqrestore(&drv_data->lock, flags);
1195 spin_lock_irqsave(&drv_data->lock, flags);
1198 if (!list_empty(&drv_data->queue) || drv_data->busy)
1201 spin_unlock_irqrestore(&drv_data->lock, flags);
1206 static inline int destroy_queue(struct driver_data *drv_data)
1210 status = stop_queue(drv_data);
1214 destroy_workqueue(drv_data->workqueue);
1219 static int setup_pin_mux(int action, int bus_num)
1222 u16 pin_req[3][4] = {
1223 {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
1224 {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
1225 {P_SPI2_SCK, P_SPI2_MISO, P_SPI2_MOSI, 0},
1229 if (peripheral_request_list(pin_req[bus_num], DRV_NAME))
1232 peripheral_free_list(pin_req[bus_num]);
1238 static int __init bfin5xx_spi_probe(struct platform_device *pdev)
1240 struct device *dev = &pdev->dev;
1241 struct bfin5xx_spi_master *platform_info;
1242 struct spi_master *master;
1243 struct driver_data *drv_data = 0;
1244 struct resource *res;
1247 platform_info = dev->platform_data;
1249 /* Allocate master with space for drv_data */
1250 master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1252 dev_err(&pdev->dev, "can not alloc spi_master\n");
1256 drv_data = spi_master_get_devdata(master);
1257 drv_data->master = master;
1258 drv_data->master_info = platform_info;
1259 drv_data->pdev = pdev;
1261 master->bus_num = pdev->id;
1262 master->num_chipselect = platform_info->num_chipselect;
1263 master->cleanup = cleanup;
1264 master->setup = setup;
1265 master->transfer = transfer;
1267 /* Find and map our resources */
1268 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1270 dev_err(dev, "Cannot get IORESOURCE_MEM\n");
1272 goto out_error_get_res;
1275 spi_regs_base = (u32) ioremap(res->start, (res->end - res->start)+1);
1276 if (!spi_regs_base) {
1277 dev_err(dev, "Cannot map IO\n");
1279 goto out_error_ioremap;
1282 spi_dma_ch = platform_get_irq(pdev, 0);
1283 if (spi_dma_ch < 0) {
1284 dev_err(dev, "No DMA channel specified\n");
1286 goto out_error_no_dma_ch;
1289 /* Initial and start queue */
1290 status = init_queue(drv_data);
1292 dev_err(dev, "problem initializing queue\n");
1293 goto out_error_queue_alloc;
1296 status = start_queue(drv_data);
1298 dev_err(dev, "problem starting queue\n");
1299 goto out_error_queue_alloc;
1302 /* Register with the SPI framework */
1303 platform_set_drvdata(pdev, drv_data);
1304 status = spi_register_master(master);
1306 dev_err(dev, "problem registering spi master\n");
1307 goto out_error_queue_alloc;
1310 if (setup_pin_mux(1, master->bus_num)) {
1311 dev_err(&pdev->dev, ": Requesting Peripherals failed\n");
1315 dev_info(dev, "%s, Version %s, regs_base @ 0x%08x\n",
1316 DRV_DESC, DRV_VERSION, spi_regs_base);
1319 out_error_queue_alloc:
1320 destroy_queue(drv_data);
1321 out_error_no_dma_ch:
1322 iounmap((void *) spi_regs_base);
1326 spi_master_put(master);
1331 /* stop hardware and remove the driver */
1332 static int __devexit bfin5xx_spi_remove(struct platform_device *pdev)
1334 struct driver_data *drv_data = platform_get_drvdata(pdev);
1340 /* Remove the queue */
1341 status = destroy_queue(drv_data);
1345 /* Disable the SSP at the peripheral and SOC level */
1346 bfin_spi_disable(drv_data);
1349 if (drv_data->master_info->enable_dma) {
1350 if (dma_channel_active(spi_dma_ch))
1351 free_dma(spi_dma_ch);
1354 /* Disconnect from the SPI framework */
1355 spi_unregister_master(drv_data->master);
1357 setup_pin_mux(0, drv_data->master->bus_num);
1359 /* Prevent double remove */
1360 platform_set_drvdata(pdev, NULL);
1366 static int bfin5xx_spi_suspend(struct platform_device *pdev, pm_message_t state)
1368 struct driver_data *drv_data = platform_get_drvdata(pdev);
1371 status = stop_queue(drv_data);
1376 bfin_spi_disable(drv_data);
1381 static int bfin5xx_spi_resume(struct platform_device *pdev)
1383 struct driver_data *drv_data = platform_get_drvdata(pdev);
1386 /* Enable the SPI interface */
1387 bfin_spi_enable(drv_data);
1389 /* Start the queue running */
1390 status = start_queue(drv_data);
1392 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1399 #define bfin5xx_spi_suspend NULL
1400 #define bfin5xx_spi_resume NULL
1401 #endif /* CONFIG_PM */
1403 MODULE_ALIAS("bfin-spi-master"); /* for platform bus hotplug */
1404 static struct platform_driver bfin5xx_spi_driver = {
1407 .owner = THIS_MODULE,
1409 .suspend = bfin5xx_spi_suspend,
1410 .resume = bfin5xx_spi_resume,
1411 .remove = __devexit_p(bfin5xx_spi_remove),
1414 static int __init bfin5xx_spi_init(void)
1416 return platform_driver_probe(&bfin5xx_spi_driver, bfin5xx_spi_probe);
1418 module_init(bfin5xx_spi_init);
1420 static void __exit bfin5xx_spi_exit(void)
1422 platform_driver_unregister(&bfin5xx_spi_driver);
1424 module_exit(bfin5xx_spi_exit);