1 // SPDX-License-Identifier: GPL-2.0
3 * This file is subject to the terms and conditions of the GNU General Public
4 * License. See the file "COPYING" in the main directory of this archive
7 * Derived from many drivers using generic_serial interface.
9 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
11 * Serial driver for BCM63xx integrated UART.
13 * Hardware flow control was _not_ tested since I only have RX/TX on
17 #if defined(CONFIG_SERIAL_BCM63XX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21 #include <linux/kernel.h>
22 #include <linux/platform_device.h>
23 #include <linux/init.h>
24 #include <linux/delay.h>
25 #include <linux/module.h>
26 #include <linux/console.h>
27 #include <linux/clk.h>
28 #include <linux/tty.h>
29 #include <linux/tty_flip.h>
30 #include <linux/sysrq.h>
31 #include <linux/serial.h>
32 #include <linux/serial_core.h>
33 #include <linux/serial_bcm63xx.h>
37 #define BCM63XX_NR_UARTS 2
39 static struct uart_port ports[BCM63XX_NR_UARTS];
42 * rx interrupt mask / stat
46 * - rx fifo above threshold
47 * - rx fifo not empty for too long
49 #define UART_RX_INT_MASK (UART_IR_MASK(UART_IR_RXOVER) | \
50 UART_IR_MASK(UART_IR_RXTHRESH) | \
51 UART_IR_MASK(UART_IR_RXTIMEOUT))
53 #define UART_RX_INT_STAT (UART_IR_STAT(UART_IR_RXOVER) | \
54 UART_IR_STAT(UART_IR_RXTHRESH) | \
55 UART_IR_STAT(UART_IR_RXTIMEOUT))
58 * tx interrupt mask / stat
62 * - tx fifo below threshold
64 #define UART_TX_INT_MASK (UART_IR_MASK(UART_IR_TXEMPTY) | \
65 UART_IR_MASK(UART_IR_TXTRESH))
67 #define UART_TX_INT_STAT (UART_IR_STAT(UART_IR_TXEMPTY) | \
68 UART_IR_STAT(UART_IR_TXTRESH))
71 * external input interrupt
73 * mask: any edge on CTS, DCD
75 #define UART_EXTINP_INT_MASK (UART_EXTINP_IRMASK(UART_EXTINP_IR_CTS) | \
76 UART_EXTINP_IRMASK(UART_EXTINP_IR_DCD))
79 * handy uart register accessor
81 static inline unsigned int bcm_uart_readl(struct uart_port *port,
84 return __raw_readl(port->membase + offset);
87 static inline void bcm_uart_writel(struct uart_port *port,
88 unsigned int value, unsigned int offset)
90 __raw_writel(value, port->membase + offset);
94 * serial core request to check if uart tx fifo is empty
96 static unsigned int bcm_uart_tx_empty(struct uart_port *port)
100 val = bcm_uart_readl(port, UART_IR_REG);
101 return (val & UART_IR_STAT(UART_IR_TXEMPTY)) ? 1 : 0;
105 * serial core request to set RTS and DTR pin state and loopback mode
107 static void bcm_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
111 val = bcm_uart_readl(port, UART_MCTL_REG);
112 val &= ~(UART_MCTL_DTR_MASK | UART_MCTL_RTS_MASK);
113 /* invert of written value is reflected on the pin */
114 if (!(mctrl & TIOCM_DTR))
115 val |= UART_MCTL_DTR_MASK;
116 if (!(mctrl & TIOCM_RTS))
117 val |= UART_MCTL_RTS_MASK;
118 bcm_uart_writel(port, val, UART_MCTL_REG);
120 val = bcm_uart_readl(port, UART_CTL_REG);
121 if (mctrl & TIOCM_LOOP)
122 val |= UART_CTL_LOOPBACK_MASK;
124 val &= ~UART_CTL_LOOPBACK_MASK;
125 bcm_uart_writel(port, val, UART_CTL_REG);
129 * serial core request to return RI, CTS, DCD and DSR pin state
131 static unsigned int bcm_uart_get_mctrl(struct uart_port *port)
133 unsigned int val, mctrl;
136 val = bcm_uart_readl(port, UART_EXTINP_REG);
137 if (val & UART_EXTINP_RI_MASK)
139 if (val & UART_EXTINP_CTS_MASK)
141 if (val & UART_EXTINP_DCD_MASK)
143 if (val & UART_EXTINP_DSR_MASK)
149 * serial core request to disable tx ASAP (used for flow control)
151 static void bcm_uart_stop_tx(struct uart_port *port)
155 val = bcm_uart_readl(port, UART_CTL_REG);
156 val &= ~(UART_CTL_TXEN_MASK);
157 bcm_uart_writel(port, val, UART_CTL_REG);
159 val = bcm_uart_readl(port, UART_IR_REG);
160 val &= ~UART_TX_INT_MASK;
161 bcm_uart_writel(port, val, UART_IR_REG);
165 * serial core request to (re)enable tx
167 static void bcm_uart_start_tx(struct uart_port *port)
171 val = bcm_uart_readl(port, UART_IR_REG);
172 val |= UART_TX_INT_MASK;
173 bcm_uart_writel(port, val, UART_IR_REG);
175 val = bcm_uart_readl(port, UART_CTL_REG);
176 val |= UART_CTL_TXEN_MASK;
177 bcm_uart_writel(port, val, UART_CTL_REG);
181 * serial core request to stop rx, called before port shutdown
183 static void bcm_uart_stop_rx(struct uart_port *port)
187 val = bcm_uart_readl(port, UART_IR_REG);
188 val &= ~UART_RX_INT_MASK;
189 bcm_uart_writel(port, val, UART_IR_REG);
193 * serial core request to enable modem status interrupt reporting
195 static void bcm_uart_enable_ms(struct uart_port *port)
199 val = bcm_uart_readl(port, UART_IR_REG);
200 val |= UART_IR_MASK(UART_IR_EXTIP);
201 bcm_uart_writel(port, val, UART_IR_REG);
205 * serial core request to start/stop emitting break char
207 static void bcm_uart_break_ctl(struct uart_port *port, int ctl)
212 spin_lock_irqsave(&port->lock, flags);
214 val = bcm_uart_readl(port, UART_CTL_REG);
216 val |= UART_CTL_XMITBRK_MASK;
218 val &= ~UART_CTL_XMITBRK_MASK;
219 bcm_uart_writel(port, val, UART_CTL_REG);
221 spin_unlock_irqrestore(&port->lock, flags);
225 * return port type in string format
227 static const char *bcm_uart_type(struct uart_port *port)
229 return (port->type == PORT_BCM63XX) ? "bcm63xx_uart" : NULL;
233 * read all chars in rx fifo and send them to core
235 static void bcm_uart_do_rx(struct uart_port *port)
237 struct tty_port *tty_port = &port->state->port;
238 unsigned int max_count;
240 /* limit number of char read in interrupt, should not be
241 * higher than fifo size anyway since we're much faster than
245 unsigned int iestat, c, cstat;
248 /* get overrun/fifo empty information from ier
250 iestat = bcm_uart_readl(port, UART_IR_REG);
252 if (unlikely(iestat & UART_IR_STAT(UART_IR_RXOVER))) {
255 /* fifo reset is required to clear
257 val = bcm_uart_readl(port, UART_CTL_REG);
258 val |= UART_CTL_RSTRXFIFO_MASK;
259 bcm_uart_writel(port, val, UART_CTL_REG);
261 port->icount.overrun++;
262 tty_insert_flip_char(tty_port, 0, TTY_OVERRUN);
265 if (!(iestat & UART_IR_STAT(UART_IR_RXNOTEMPTY)))
268 cstat = c = bcm_uart_readl(port, UART_FIFO_REG);
273 if (unlikely((cstat & UART_FIFO_ANYERR_MASK))) {
275 if (cstat & UART_FIFO_BRKDET_MASK) {
277 if (uart_handle_break(port))
281 if (cstat & UART_FIFO_PARERR_MASK)
282 port->icount.parity++;
283 if (cstat & UART_FIFO_FRAMEERR_MASK)
284 port->icount.frame++;
286 /* update flag wrt read_status_mask */
287 cstat &= port->read_status_mask;
288 if (cstat & UART_FIFO_BRKDET_MASK)
290 if (cstat & UART_FIFO_FRAMEERR_MASK)
292 if (cstat & UART_FIFO_PARERR_MASK)
296 if (uart_handle_sysrq_char(port, c))
300 if ((cstat & port->ignore_status_mask) == 0)
301 tty_insert_flip_char(tty_port, c, flag);
303 } while (--max_count);
305 spin_unlock(&port->lock);
306 tty_flip_buffer_push(tty_port);
307 spin_lock(&port->lock);
311 * fill tx fifo with chars to send, stop when fifo is about to be full
312 * or when all chars have been sent.
314 static void bcm_uart_do_tx(struct uart_port *port)
316 struct circ_buf *xmit;
317 unsigned int val, max_count;
320 bcm_uart_writel(port, port->x_char, UART_FIFO_REG);
326 if (uart_tx_stopped(port)) {
327 bcm_uart_stop_tx(port);
331 xmit = &port->state->xmit;
332 if (uart_circ_empty(xmit))
335 val = bcm_uart_readl(port, UART_MCTL_REG);
336 val = (val & UART_MCTL_TXFIFOFILL_MASK) >> UART_MCTL_TXFIFOFILL_SHIFT;
337 max_count = port->fifosize - val;
339 while (max_count--) {
342 c = xmit->buf[xmit->tail];
343 bcm_uart_writel(port, c, UART_FIFO_REG);
344 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
346 if (uart_circ_empty(xmit))
350 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
351 uart_write_wakeup(port);
353 if (uart_circ_empty(xmit))
358 /* nothing to send, disable transmit interrupt */
359 val = bcm_uart_readl(port, UART_IR_REG);
360 val &= ~UART_TX_INT_MASK;
361 bcm_uart_writel(port, val, UART_IR_REG);
366 * process uart interrupt
368 static irqreturn_t bcm_uart_interrupt(int irq, void *dev_id)
370 struct uart_port *port;
371 unsigned int irqstat;
374 spin_lock(&port->lock);
376 irqstat = bcm_uart_readl(port, UART_IR_REG);
377 if (irqstat & UART_RX_INT_STAT)
378 bcm_uart_do_rx(port);
380 if (irqstat & UART_TX_INT_STAT)
381 bcm_uart_do_tx(port);
383 if (irqstat & UART_IR_MASK(UART_IR_EXTIP)) {
386 estat = bcm_uart_readl(port, UART_EXTINP_REG);
387 if (estat & UART_EXTINP_IRSTAT(UART_EXTINP_IR_CTS))
388 uart_handle_cts_change(port,
389 estat & UART_EXTINP_CTS_MASK);
390 if (estat & UART_EXTINP_IRSTAT(UART_EXTINP_IR_DCD))
391 uart_handle_dcd_change(port,
392 estat & UART_EXTINP_DCD_MASK);
395 spin_unlock(&port->lock);
400 * enable rx & tx operation on uart
402 static void bcm_uart_enable(struct uart_port *port)
406 val = bcm_uart_readl(port, UART_CTL_REG);
407 val |= (UART_CTL_BRGEN_MASK | UART_CTL_TXEN_MASK | UART_CTL_RXEN_MASK);
408 bcm_uart_writel(port, val, UART_CTL_REG);
412 * disable rx & tx operation on uart
414 static void bcm_uart_disable(struct uart_port *port)
418 val = bcm_uart_readl(port, UART_CTL_REG);
419 val &= ~(UART_CTL_BRGEN_MASK | UART_CTL_TXEN_MASK |
421 bcm_uart_writel(port, val, UART_CTL_REG);
425 * clear all unread data in rx fifo and unsent data in tx fifo
427 static void bcm_uart_flush(struct uart_port *port)
431 /* empty rx and tx fifo */
432 val = bcm_uart_readl(port, UART_CTL_REG);
433 val |= UART_CTL_RSTRXFIFO_MASK | UART_CTL_RSTTXFIFO_MASK;
434 bcm_uart_writel(port, val, UART_CTL_REG);
436 /* read any pending char to make sure all irq status are
438 (void)bcm_uart_readl(port, UART_FIFO_REG);
442 * serial core request to initialize uart and start rx operation
444 static int bcm_uart_startup(struct uart_port *port)
449 /* mask all irq and flush port */
450 bcm_uart_disable(port);
451 bcm_uart_writel(port, 0, UART_IR_REG);
452 bcm_uart_flush(port);
454 /* clear any pending external input interrupt */
455 (void)bcm_uart_readl(port, UART_EXTINP_REG);
457 /* set rx/tx fifo thresh to fifo half size */
458 val = bcm_uart_readl(port, UART_MCTL_REG);
459 val &= ~(UART_MCTL_RXFIFOTHRESH_MASK | UART_MCTL_TXFIFOTHRESH_MASK);
460 val |= (port->fifosize / 2) << UART_MCTL_RXFIFOTHRESH_SHIFT;
461 val |= (port->fifosize / 2) << UART_MCTL_TXFIFOTHRESH_SHIFT;
462 bcm_uart_writel(port, val, UART_MCTL_REG);
464 /* set rx fifo timeout to 1 char time */
465 val = bcm_uart_readl(port, UART_CTL_REG);
466 val &= ~UART_CTL_RXTMOUTCNT_MASK;
467 val |= 1 << UART_CTL_RXTMOUTCNT_SHIFT;
468 bcm_uart_writel(port, val, UART_CTL_REG);
470 /* report any edge on dcd and cts */
471 val = UART_EXTINP_INT_MASK;
472 val |= UART_EXTINP_DCD_NOSENSE_MASK;
473 val |= UART_EXTINP_CTS_NOSENSE_MASK;
474 bcm_uart_writel(port, val, UART_EXTINP_REG);
476 /* register irq and enable rx interrupts */
477 ret = request_irq(port->irq, bcm_uart_interrupt, 0,
478 dev_name(port->dev), port);
481 bcm_uart_writel(port, UART_RX_INT_MASK, UART_IR_REG);
482 bcm_uart_enable(port);
487 * serial core request to flush & disable uart
489 static void bcm_uart_shutdown(struct uart_port *port)
493 spin_lock_irqsave(&port->lock, flags);
494 bcm_uart_writel(port, 0, UART_IR_REG);
495 spin_unlock_irqrestore(&port->lock, flags);
497 bcm_uart_disable(port);
498 bcm_uart_flush(port);
499 free_irq(port->irq, port);
503 * serial core request to change current uart setting
505 static void bcm_uart_set_termios(struct uart_port *port,
506 struct ktermios *new,
507 struct ktermios *old)
509 unsigned int ctl, baud, quot, ier;
513 spin_lock_irqsave(&port->lock, flags);
515 /* Drain the hot tub fully before we power it off for the winter. */
516 for (tries = 3; !bcm_uart_tx_empty(port) && tries; tries--)
519 /* disable uart while changing speed */
520 bcm_uart_disable(port);
521 bcm_uart_flush(port);
523 /* update Control register */
524 ctl = bcm_uart_readl(port, UART_CTL_REG);
525 ctl &= ~UART_CTL_BITSPERSYM_MASK;
527 switch (new->c_cflag & CSIZE) {
529 ctl |= (0 << UART_CTL_BITSPERSYM_SHIFT);
532 ctl |= (1 << UART_CTL_BITSPERSYM_SHIFT);
535 ctl |= (2 << UART_CTL_BITSPERSYM_SHIFT);
538 ctl |= (3 << UART_CTL_BITSPERSYM_SHIFT);
542 ctl &= ~UART_CTL_STOPBITS_MASK;
543 if (new->c_cflag & CSTOPB)
544 ctl |= UART_CTL_STOPBITS_2;
546 ctl |= UART_CTL_STOPBITS_1;
548 ctl &= ~(UART_CTL_RXPAREN_MASK | UART_CTL_TXPAREN_MASK);
549 if (new->c_cflag & PARENB)
550 ctl |= (UART_CTL_RXPAREN_MASK | UART_CTL_TXPAREN_MASK);
551 ctl &= ~(UART_CTL_RXPAREVEN_MASK | UART_CTL_TXPAREVEN_MASK);
552 if (new->c_cflag & PARODD)
553 ctl |= (UART_CTL_RXPAREVEN_MASK | UART_CTL_TXPAREVEN_MASK);
554 bcm_uart_writel(port, ctl, UART_CTL_REG);
556 /* update Baudword register */
557 baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
558 quot = uart_get_divisor(port, baud) - 1;
559 bcm_uart_writel(port, quot, UART_BAUD_REG);
561 /* update Interrupt register */
562 ier = bcm_uart_readl(port, UART_IR_REG);
564 ier &= ~UART_IR_MASK(UART_IR_EXTIP);
565 if (UART_ENABLE_MS(port, new->c_cflag))
566 ier |= UART_IR_MASK(UART_IR_EXTIP);
568 bcm_uart_writel(port, ier, UART_IR_REG);
570 /* update read/ignore mask */
571 port->read_status_mask = UART_FIFO_VALID_MASK;
572 if (new->c_iflag & INPCK) {
573 port->read_status_mask |= UART_FIFO_FRAMEERR_MASK;
574 port->read_status_mask |= UART_FIFO_PARERR_MASK;
576 if (new->c_iflag & (IGNBRK | BRKINT))
577 port->read_status_mask |= UART_FIFO_BRKDET_MASK;
579 port->ignore_status_mask = 0;
580 if (new->c_iflag & IGNPAR)
581 port->ignore_status_mask |= UART_FIFO_PARERR_MASK;
582 if (new->c_iflag & IGNBRK)
583 port->ignore_status_mask |= UART_FIFO_BRKDET_MASK;
584 if (!(new->c_cflag & CREAD))
585 port->ignore_status_mask |= UART_FIFO_VALID_MASK;
587 uart_update_timeout(port, new->c_cflag, baud);
588 bcm_uart_enable(port);
589 spin_unlock_irqrestore(&port->lock, flags);
593 * serial core request to claim uart iomem
595 static int bcm_uart_request_port(struct uart_port *port)
597 /* UARTs always present */
602 * serial core request to release uart iomem
604 static void bcm_uart_release_port(struct uart_port *port)
606 /* Nothing to release ... */
610 * serial core request to do any port required autoconfiguration
612 static void bcm_uart_config_port(struct uart_port *port, int flags)
614 if (flags & UART_CONFIG_TYPE) {
615 if (bcm_uart_request_port(port))
617 port->type = PORT_BCM63XX;
622 * serial core request to check that port information in serinfo are
625 static int bcm_uart_verify_port(struct uart_port *port,
626 struct serial_struct *serinfo)
628 if (port->type != PORT_BCM63XX)
630 if (port->irq != serinfo->irq)
632 if (port->iotype != serinfo->io_type)
634 if (port->mapbase != (unsigned long)serinfo->iomem_base)
639 /* serial core callbacks */
640 static const struct uart_ops bcm_uart_ops = {
641 .tx_empty = bcm_uart_tx_empty,
642 .get_mctrl = bcm_uart_get_mctrl,
643 .set_mctrl = bcm_uart_set_mctrl,
644 .start_tx = bcm_uart_start_tx,
645 .stop_tx = bcm_uart_stop_tx,
646 .stop_rx = bcm_uart_stop_rx,
647 .enable_ms = bcm_uart_enable_ms,
648 .break_ctl = bcm_uart_break_ctl,
649 .startup = bcm_uart_startup,
650 .shutdown = bcm_uart_shutdown,
651 .set_termios = bcm_uart_set_termios,
652 .type = bcm_uart_type,
653 .release_port = bcm_uart_release_port,
654 .request_port = bcm_uart_request_port,
655 .config_port = bcm_uart_config_port,
656 .verify_port = bcm_uart_verify_port,
661 #ifdef CONFIG_SERIAL_BCM63XX_CONSOLE
662 static void wait_for_xmitr(struct uart_port *port)
666 /* Wait up to 10ms for the character(s) to be sent. */
671 val = bcm_uart_readl(port, UART_IR_REG);
672 if (val & UART_IR_STAT(UART_IR_TXEMPTY))
677 /* Wait up to 1s for flow control if necessary */
678 if (port->flags & UPF_CONS_FLOW) {
683 val = bcm_uart_readl(port, UART_EXTINP_REG);
684 if (val & UART_EXTINP_CTS_MASK)
694 static void bcm_console_putchar(struct uart_port *port, int ch)
696 wait_for_xmitr(port);
697 bcm_uart_writel(port, ch, UART_FIFO_REG);
701 * console core request to output given string
703 static void bcm_console_write(struct console *co, const char *s,
706 struct uart_port *port;
710 port = &ports[co->index];
712 local_irq_save(flags);
714 /* bcm_uart_interrupt() already took the lock */
716 } else if (oops_in_progress) {
717 locked = spin_trylock(&port->lock);
719 spin_lock(&port->lock);
723 /* call helper to deal with \r\n */
724 uart_console_write(port, s, count, bcm_console_putchar);
726 /* and wait for char to be transmitted */
727 wait_for_xmitr(port);
730 spin_unlock(&port->lock);
731 local_irq_restore(flags);
735 * console core request to setup given console, find matching uart
738 static int bcm_console_setup(struct console *co, char *options)
740 struct uart_port *port;
746 if (co->index < 0 || co->index >= BCM63XX_NR_UARTS)
748 port = &ports[co->index];
752 uart_parse_options(options, &baud, &parity, &bits, &flow);
754 return uart_set_options(port, co, baud, parity, bits, flow);
757 static struct uart_driver bcm_uart_driver;
759 static struct console bcm63xx_console = {
761 .write = bcm_console_write,
762 .device = uart_console_device,
763 .setup = bcm_console_setup,
764 .flags = CON_PRINTBUFFER,
766 .data = &bcm_uart_driver,
769 static int __init bcm63xx_console_init(void)
771 register_console(&bcm63xx_console);
775 console_initcall(bcm63xx_console_init);
777 static void bcm_early_write(struct console *con, const char *s, unsigned n)
779 struct earlycon_device *dev = con->data;
781 uart_console_write(&dev->port, s, n, bcm_console_putchar);
782 wait_for_xmitr(&dev->port);
785 static int __init bcm_early_console_setup(struct earlycon_device *device,
788 if (!device->port.membase)
791 device->con->write = bcm_early_write;
795 OF_EARLYCON_DECLARE(bcm63xx_uart, "brcm,bcm6345-uart", bcm_early_console_setup);
797 #define BCM63XX_CONSOLE (&bcm63xx_console)
799 #define BCM63XX_CONSOLE NULL
800 #endif /* CONFIG_SERIAL_BCM63XX_CONSOLE */
802 static struct uart_driver bcm_uart_driver = {
803 .owner = THIS_MODULE,
804 .driver_name = "bcm63xx_uart",
808 .nr = BCM63XX_NR_UARTS,
809 .cons = BCM63XX_CONSOLE,
813 * platform driver probe/remove callback
815 static int bcm_uart_probe(struct platform_device *pdev)
817 struct resource *res_mem, *res_irq;
818 struct uart_port *port;
822 if (pdev->dev.of_node) {
823 pdev->id = of_alias_get_id(pdev->dev.of_node, "serial");
826 pdev->id = of_alias_get_id(pdev->dev.of_node, "uart");
829 if (pdev->id < 0 || pdev->id >= BCM63XX_NR_UARTS)
832 port = &ports[pdev->id];
835 memset(port, 0, sizeof(*port));
837 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
841 port->mapbase = res_mem->start;
842 port->membase = devm_ioremap_resource(&pdev->dev, res_mem);
843 if (IS_ERR(port->membase))
844 return PTR_ERR(port->membase);
846 res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
850 clk = pdev->dev.of_node ? of_clk_get(pdev->dev.of_node, 0) :
851 clk_get(&pdev->dev, "periph");
855 port->iotype = UPIO_MEM;
856 port->irq = res_irq->start;
857 port->ops = &bcm_uart_ops;
858 port->flags = UPF_BOOT_AUTOCONF;
859 port->dev = &pdev->dev;
861 port->uartclk = clk_get_rate(clk) / 2;
862 port->line = pdev->id;
865 ret = uart_add_one_port(&bcm_uart_driver, port);
867 ports[pdev->id].membase = NULL;
870 platform_set_drvdata(pdev, port);
874 static int bcm_uart_remove(struct platform_device *pdev)
876 struct uart_port *port;
878 port = platform_get_drvdata(pdev);
879 uart_remove_one_port(&bcm_uart_driver, port);
880 /* mark port as free */
881 ports[pdev->id].membase = NULL;
885 static const struct of_device_id bcm63xx_of_match[] = {
886 { .compatible = "brcm,bcm6345-uart" },
889 MODULE_DEVICE_TABLE(of, bcm63xx_of_match);
892 * platform driver stuff
894 static struct platform_driver bcm_uart_platform_driver = {
895 .probe = bcm_uart_probe,
896 .remove = bcm_uart_remove,
898 .name = "bcm63xx_uart",
899 .of_match_table = bcm63xx_of_match,
903 static int __init bcm_uart_init(void)
907 ret = uart_register_driver(&bcm_uart_driver);
911 ret = platform_driver_register(&bcm_uart_platform_driver);
913 uart_unregister_driver(&bcm_uart_driver);
918 static void __exit bcm_uart_exit(void)
920 platform_driver_unregister(&bcm_uart_platform_driver);
921 uart_unregister_driver(&bcm_uart_driver);
924 module_init(bcm_uart_init);
925 module_exit(bcm_uart_exit);
927 MODULE_AUTHOR("Maxime Bizon <mbizon@freebox.fr>");
928 MODULE_DESCRIPTION("Broadcom 63xx integrated uart driver");
929 MODULE_LICENSE("GPL");