4 Copyright 2008, 2009 Michel Pollet <buserror@gmail.com>
6 This file is part of simavr.
8 simavr is free software: you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation, either version 3 of the License, or
11 (at your option) any later version.
13 simavr is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with simavr. If not, see <http://www.gnu.org/licenses/>.
23 #ifndef __I2C_EEPROM_H___
24 #define __I2C_EEPROM_H___
29 * This is a generic i2c eeprom; it can be up to 4096 bytes, and can work
31 * 1) ONE slave address, and either one or two bytes sent on i2c to specify
32 * the byte to read/write.
33 * So a transaction looks like:
34 * <i2c address> [<byte offset MSB>] <byte offset LSB> [<data>]
35 * 2) Multiple slave address to specify the high byte offset value, and one
37 * So a transaction looks like:
38 * <i2c address; x low bits used as byte offset> <byte offset LSB> [<data>]
40 * these two modes seem to cover many eeproms
42 typedef struct i2c_eeprom_t {
43 avr_irq_t * irq; // irq list
48 uint8_t selected; // selected address
49 int index; // byte index in current transaction
51 uint16_t reg_addr; // read/write address register
52 int size; // also implies the address size, one or two byte
57 * Initializes an eeprom.
59 * The address is the TWI/i2c address base, for example 0xa0 -- the 7 MSB are
60 * relevant, the bit zero is always meant as the "read write" bit.
61 * The "mask" parameter specifies which bits should be matched as a slave;
62 * if you want to have a peripheral that handle read and write, use '1'; if you
63 * want to also match several addresses on the bus, specify these bits on the
66 * Address 0xa1 mask 0x00 will match address 0xa0 in READ only
67 * Address 0xa0 mask 0x01 will match address 0xa0 in read AND write mode
68 * Address 0xa0 mask 0x03 will match 0xa0 0xa2 in read and write mode
70 * The "data" is optional, data is initialized as 0xff like a normal eeprom.
82 * Attach the eeprom to the AVR's TWI master code,
83 * pass AVR_IOCTL_TWI_GETIRQ(0) for example as i2c_irq_base
89 uint32_t i2c_irq_base );
91 #endif /* __I2C_EEPROM_H___ */