2 \author Travis Goodspeed
3 \brief Chipcon 8051 debugging.
7 //This is like SPI, except that you read or write, not both.
9 /* N.B. The READ verb performs a write of all (any) supplied data,
10 then reads a single byte reply from the target. The WRITE verb
22 //! Handles a chipcon command.
23 void cc_handle_fn( uint8_t const app,
27 // define the jtag app's app_t
28 app_t const chipcon_app = {
40 "\tThe CHIPCON app adds support for debugging the chipcon\n"
44 /* Concerning clock rates, the maximimum clock rates are defined on
45 page 4 of the spec. They vary, but are roughly 30MHz. Raising
46 this clock rate might allow for clock glitching, but the GoodFET
47 isn't sufficient fast for that. Perhaps a 200MHz ARM or an FPGA in
52 //MISO and MOSI are the same pin, direction changes.
59 //This could be more accurate.
60 //Does it ever need to be?
62 //#define CCDELAY(x) delay(x)
65 #define SETMOSI SPIOUT|=MOSI
66 #define CLRMOSI SPIOUT&=~MOSI
67 #define SETCLK SPIOUT|=SCK
68 #define CLRCLK SPIOUT&=~SCK
69 #define READMISO (SPIIN&MISO?1:0)
71 #define CCWRITE SPIDIR|=MOSI
72 #define CCREAD SPIDIR&=~MISO
74 //! Set up the pins for CC mode. Does not init debugger.
82 /* 33 cycle critical region
83 0000000e <ccdebuginit>:
84 e: f2 d0 0d 00 bis.b #13, &0x0031 ;5 cycles
86 14: f2 c2 31 00 bic.b #8, &0x0031 ;4 cycles
87 18: d2 c3 31 00 bic.b #1, &0x0031 ;4
88 1c: f2 e2 31 00 xor.b #8, &0x0031 ;4
89 20: f2 e2 31 00 xor.b #8, &0x0031 ;4
90 24: f2 e2 31 00 xor.b #8, &0x0031 ;4
91 28: f2 e2 31 00 xor.b #8, &0x0031 ;4
92 2c: d2 d3 31 00 bis.b #1, &0x0031 ;4
97 //! Initialize the debugger
99 //Port output BUT NOT DIRECTION is set at start.
100 SPIOUT|=MOSI+SCK+RST;
102 //delay(30); //So the beginning is ready for glitching.
104 //Two positive debug clock pulses while !RST is low.
105 //Take RST low, pulse twice, then high.
119 SPIOUT^=SCK; //Unnecessary.
127 //! Read and write a CC bit.
128 unsigned char cctrans8(unsigned char byte){
130 //This function came from the SPI Wikipedia article.
133 for (bit = 0; bit < 8; bit++) {
134 /* write MOSI on trailing edge of previous clock */
141 /* half a clock cycle before leading/rising edge */
145 /* half a clock cycle before trailing/falling edge */
148 /* read MISO on trailing edge */
156 //! Send a command from txbytes.
157 void cccmd(unsigned char len){
161 cctrans8(cmddata[i]);
164 //! Fetch a reply, usually 1 byte.
165 void ccread(unsigned char len){
169 cmddata[i]=cctrans8(0);
172 //! Handles a chipcon command.
173 void cc_handle_fn( uint8_t const app,
177 //Always init. Might help with buggy lines.
181 int blocklen, blockadr;
184 //CC_PEEK and CC_POKE will come later.
186 cmddata[0]=cc_peekirambyte(cmddata[0]);
190 cmddata[0]=cc_pokeirambyte(cmddata[0],cmddata[1]);
193 case READ: //Write a command and return 1-byte reply.
199 case WRITE: //Write a command with no reply.
203 case START://enter debugger
207 case STOP://exit debugger
208 //Take RST low, then high.
221 case CC_MASS_ERASE_FLASH:
226 cc_wr_config(cmddata[0]);
239 //no break, return status
244 case CC_SET_HW_BRKPNT:
245 cc_set_hw_brkpnt(cmddataword[0]);
264 case CC_STEP_REPLACE:
265 txdata(app,NOK,0);//TODO add me
268 cmddataword[0]=cc_get_chip_id();
274 case CC_READ_CODE_MEMORY:
275 cmddata[0]=cc_peekcodebyte(cmddataword[0]);
278 case CC_READ_XDATA_MEMORY:
282 blocklen=cmddataword[1];
283 blockadr=cmddataword[0];
285 //Return that many bytes.
286 for(i=0;i<blocklen;i++)
287 cmddata[i]=cc_peekdatabyte(blockadr+i);
288 txdata(app,verb,blocklen);
291 case CC_WRITE_XDATA_MEMORY:
292 cmddata[0]=cc_pokedatabyte(cmddataword[0], cmddata[2]);
296 cc_set_pc(cmddatalong[0]);
299 case CC_WRITE_FLASH_PAGE:
300 cc_write_flash_page(cmddatalong[0]);
303 case CC_WIPEFLASHBUFFER:
304 for(i=0xf000;i<0xf800;i++)
305 cc_pokedatabyte(i,0xFF);
310 case CC_PROGRAM_FLASH:
312 debugstr("This Chipcon command is not yet implemented.");
313 txdata(app,NOK,0);//TODO implement me.
318 //! Set the Chipcon's Program Counter
319 void cc_set_pc(u32 adr){
320 cmddata[0]=0x02; //SetPC
321 cmddata[1]=((adr>>8)&0xff); //HIBYTE
322 cmddata[2]=adr&0xff; //LOBYTE
327 //! Erase all of a Chipcon's memory.
328 void cc_chip_erase(){
329 cmddata[0]=CCCMD_CHIP_ERASE; //0x14
333 //! Write the configuration byte.
334 void cc_wr_config(unsigned char config){
335 cmddata[0]=CCCMD_WR_CONFIG; //0x1D
345 //debugstr("Locking chip.");
346 cc_wr_config(1);//Select Info Flash
347 if(!(cc_rd_config()&1))
348 debugstr("Config forgotten!");
352 cc_pokedatabyte(0xf000+i,0);
353 cc_write_flash_page(0);
354 if(cc_peekcodebyte(0))
355 debugstr("Failed to clear info flash byte.");
359 debugstr("Stuck in info flash mode!");
362 //! Read the configuration byte.
363 unsigned char cc_rd_config(){
364 cmddata[0]=CCCMD_RD_CONFIG; //0x24
371 //! Read the status register
372 unsigned char cc_read_status(){
373 cmddata[0]=CCCMD_READ_STATUS; //0x3f
379 //! Read the CHIP ID bytes.
380 unsigned short cc_get_chip_id(){
381 cmddata[0]=CCCMD_GET_CHIP_ID; //0x68
386 //Find the flash word size.
392 //debugstr("2 bytes/flash word");
393 flash_word_size=0x02;
396 //debugstr("Warning: Guessing flash word size.");
401 //debugstr("4 bytes/flash word");
402 flash_word_size=0x04;
407 return cmddataword[0];
410 //! Populates flash buffer in xdata.
411 void cc_write_flash_buffer(u8 *data, u16 len){
412 cc_write_xdata(0xf000, data, len);
414 //! Populates flash buffer in xdata.
415 void cc_write_xdata(u16 adr, u8 *data, u16 len){
417 for(i=0; i<len; i++){
418 cc_pokedatabyte(adr+i,
424 //32-bit words, 2KB pages
425 //0x20 0x00 for CC2430, CC1110
426 #define HIBYTE_WORDS_PER_FLASH_PAGE 0x02
427 #define LOBYTE_WORDS_PER_FLASH_PAGE 0x00
429 /** Ugh, this varies by chip.
433 //#define FLASHPAGE_SIZE 0x400
434 #define MAXFLASHPAGE_SIZE 0x800
435 #define MINFLASHPAGE_SIZE 0x400
438 //32 bit words on CC2430
439 //16 bit words on CC1110
440 //#define FLASH_WORD_SIZE 0x2
441 u8 flash_word_size = 0; //0x02;
444 /* Flash Write Timing
451 32 | 0x2A (Modula.si)
455 const u8 flash_routine[] = {
459 0x00,//#imm=((address >> 8) / FLASH_WORD_SIZE) & 0x7E,
461 //0x75, 0xAB, 0x23, //Set FWT per clock
462 0x75, 0xAC, 0x00, // MOV FADDRL, #00;
464 0x75, 0xAE, 0x01, // MOV FLC, #01H; // ERASE
465 // ; Wait for flash erase to complete
466 0xE5, 0xAE, // eraseWaitLoop: MOV A, FLC;
467 0x20, 0xE7, 0xFB, // JB ACC_BUSY, eraseWaitLoop;
469 /* End erase page. */
470 // ; Initialize the data pointer
471 0x90, 0xF0, 0x00, // MOV DPTR, #0F000H;
473 0x7F, HIBYTE_WORDS_PER_FLASH_PAGE, // MOV R7, #imm;
474 0x7E, LOBYTE_WORDS_PER_FLASH_PAGE, // MOV R6, #imm;
475 0x75, 0xAE, 0x02, // MOV FLC, #02H; // WRITE
478 0x7D, 0xde /*FLASH_WORD_SIZE*/, // writeLoop: MOV R5, #imm;
479 0xE0, // writeWordLoop: MOVX A, @DPTR;
481 0xF5, 0xAF, // MOV FWDATA, A;
482 0xDD, 0xFA, // DJNZ R5, writeWordLoop;
483 // ; Wait for completion
484 0xE5, 0xAE, // writeWaitLoop: MOV A, FLC;
485 0x20, 0xE6, 0xFB, // JB ACC_SWBSY, writeWaitLoop;
486 0xDE, 0xF1, // DJNZ R6, writeLoop;
487 0xDF, 0xEF, // DJNZ R7, writeLoop;
488 // ; Done, fake a breakpoint
493 //! Copies flash buffer to flash.
494 void cc_write_flash_page(u32 adr){
495 //Assumes that page has already been written to XDATA 0xF000
496 //debugstr("Flashing 2kb at 0xF000 to given adr.");
498 if(adr&(MINFLASHPAGE_SIZE-1)){
499 debugstr("Flash page address is not on a page boundary. Aborting.");
503 if(flash_word_size!=2 && flash_word_size!=4){
504 debugstr("Flash word size is wrong, aborting write to");
510 //WRITE_XDATA_MEMORY(IN: 0xF000 + FLASH_PAGE_SIZE, sizeof(routine), routine);
511 cc_write_xdata(0xF000+MAXFLASHPAGE_SIZE,
512 (u8*) flash_routine, sizeof(flash_routine));
513 //Patch routine's third byte with
514 //((address >> 8) / FLASH_WORD_SIZE) & 0x7E
515 cc_pokedatabyte(0xF000+MAXFLASHPAGE_SIZE+2,
516 ((adr>>8)/flash_word_size)&0x7E);
517 //Patch routine to define FLASH_WORD_SIZE
518 if(flash_routine[25]!=0xde)
519 debugstr("Ugly patching code failing in chipcon.c");
520 cc_pokedatabyte(0xF000+MAXFLASHPAGE_SIZE+25,
523 //debugstr("Wrote flash routine.");
525 //MOV MEMCTR, (bank * 16) + 1;
530 //debugstr("Loaded bank info.");
532 cc_set_pc(0xf000+MAXFLASHPAGE_SIZE);//execute code fragment
535 //debugstr("Executing.");
538 while(!(cc_read_status()&CC_STATUS_CPUHALTED)){
539 PLEDOUT^=PLEDPIN;//blink LED while flashing
543 //debugstr("Done flashing.");
545 PLEDOUT&=~PLEDPIN;//clear LED
549 unsigned short cc_get_pc(){
550 cmddata[0]=CCCMD_GET_PC; //0x28
555 return cmddataword[0];
558 //! Set a hardware breakpoint.
559 void cc_set_hw_brkpnt(unsigned short adr){
560 debugstr("FIXME: This certainly won't work.");
570 cmddata[0]=CCCMD_HALT; //0x44
577 cmddata[0]=CCCMD_RESUME; //0x4C
584 //! Step an instruction
585 void cc_step_instr(){
586 cmddata[0]=CCCMD_STEP_INSTR; //0x5C
592 //! Debug an instruction.
593 void cc_debug_instr(unsigned char len){
594 //Bottom two bits of command indicate length.
595 unsigned char cmd=CCCMD_DEBUG_INSTR+(len&0x3); //0x54+len
597 cctrans8(cmd); //Second command code
598 cccmd(len&0x3); //Command itself.
603 //! Debug an instruction, for local use.
604 unsigned char cc_debug(unsigned char len,
608 unsigned char cmd=CCCMD_DEBUG_INSTR+(len&0x3);//0x54+len
618 return cctrans8(0x00);
621 //! Fetch a byte of code memory.
622 unsigned char cc_peekcodebyte(unsigned long adr){
623 /** See page 9 of SWRA124 */
624 unsigned char bank=adr>>15,
630 //MOV MEMCTR, (bank*16)+1
631 cc_debug(3, 0x75, 0xC7, (bank<<4) + 1);
633 cc_debug(3, 0x90, hb, lb);
637 cc_debug(2, 0xE4, 0, 0);
639 toret=cc_debug(3, 0x93, 0, 0);
641 //cc_debug(1, 0xA3, 0, 0);
647 //! Set a byte of data memory.
648 unsigned char cc_pokedatabyte(unsigned int adr,
655 cc_debug(3, 0x90, hb, lb);
657 cc_debug(2, 0x74, val, 0);
659 cc_debug(1, 0xF0, 0, 0);
663 DEBUG_INSTR(IN: 0x90, HIBYTE(address), LOBYTE(address), OUT: Discard);
664 for (n = 0; n < count; n++) {
665 DEBUG_INSTR(IN: 0x74, inputArray[n], OUT: Discard);
666 DEBUG_INSTR(IN: 0xF0, OUT: Discard);
667 DEBUG_INSTR(IN: 0xA3, OUT: Discard);
672 //! Fetch a byte of data memory.
673 unsigned char cc_peekdatabyte(unsigned int adr){
679 cc_debug(3, 0x90, hb, lb);
681 //Must be 2, perhaps for clocking?
682 return cc_debug(3, 0xE0, 0, 0);
686 //! Fetch a byte of IRAM.
687 u8 cc_peekirambyte(u8 adr){
689 cc_debug(2, 0xE4, 0, 0);
691 return cc_debug(3, 0xE5, adr, 0);
694 //! Write a byte of IRAM.
695 u8 cc_pokeirambyte(u8 adr, u8 val){
697 cc_debug(2, 0xE4, 0, 0);
699 return cc_debug(3, 0x75, adr, val);
700 //return cc_debug(3, 0x75, val, adr);