2 \author Travis Goodspeed
3 \brief Chipcon 8051 debugging.
7 //This is like SPI, except that you read or write, not both.
9 /* N.B. The READ verb performs a write of all (any) supplied data,
10 then reads a single byte reply from the target. The WRITE verb
23 /* Concerning clock rates, the maximimum clock rates are defined on
24 page 4 of the spec. They vary, but are roughly 30MHz. Raising
25 this clock rate might allow for clock glitching, but the GoodFET
26 isn't sufficient fast for that. Perhaps a 200MHz ARM or an FPGA in
31 //MISO and MOSI are the same pin, direction changes.
37 //This could be more accurate.
38 //Does it ever need to be?
40 //#define CCDELAY(x) delay(x)
43 #define SETMOSI P5OUT|=MOSI
44 #define CLRMOSI P5OUT&=~MOSI
45 #define SETCLK P5OUT|=SCK
46 #define CLRCLK P5OUT&=~SCK
47 #define READMISO (P5IN&MISO?1:0)
49 #define CCWRITE P5DIR|=MOSI
50 #define CCREAD P5DIR&=~MISO
52 //! Set up the pins for CC mode. Does not init debugger.
56 //P5DIR&=~MISO; //MOSI is MISO
62 //! Initialize the debugger
64 delay(30); //So the beginning is ready for glitching.
66 //Two positive debug clock pulses while !RST is low.
67 //Take RST low, pulse twice, then high.
72 //pulse twice, old code.
88 P5OUT^=SCK; //Unnecessary.
95 //! Read and write a CC bit.
96 unsigned char cctrans8(unsigned char byte){
98 //This function came from the SPI Wikipedia article.
101 for (bit = 0; bit < 8; bit++) {
102 /* write MOSI on trailing edge of previous clock */
109 /* half a clock cycle before leading/rising edge */
113 /* half a clock cycle before trailing/falling edge */
116 /* read MISO on trailing edge */
124 //! Send a command from txbytes.
125 void cccmd(unsigned char len){
129 cctrans8(cmddata[i]);
132 //! Fetch a reply, usually 1 byte.
133 void ccread(unsigned char len){
137 cmddata[i]=cctrans8(0);
140 //! Handles a monitor command.
141 void cchandle(unsigned char app,
144 //Always init. Might help with buggy lines.
150 //CC_PEEK and CC_POKE will come later.
152 cmddata[0]=cc_peekirambyte(cmddata[0]);
156 cmddata[0]=cc_pokeirambyte(cmddata[0],cmddata[1]);
159 case READ: //Write a command and return 1-byte reply.
166 case WRITE: //Write a command with no reply.
170 case START://enter debugger
175 case STOP://exit debugger
176 //Take RST low, then high.
193 cc_wr_config(cmddata[0]);
206 //no break, return status
211 case CC_SET_HW_BRKPNT:
212 cc_set_hw_brkpnt(cmddataword[0]);
231 case CC_STEP_REPLACE:
232 txdata(app,NOK,0);//TODO add me
235 cmddataword[0]=cc_get_chip_id();
241 case CC_READ_CODE_MEMORY:
242 cmddata[0]=cc_peekcodebyte(cmddataword[0]);
245 case CC_READ_XDATA_MEMORY:
246 cmddata[0]=cc_peekdatabyte(cmddataword[0]);
249 case CC_WRITE_XDATA_MEMORY:
250 cmddata[0]=cc_pokedatabyte(cmddataword[0], cmddata[2]);
254 cc_set_pc(cmddatalong[0]);
257 case CC_WRITE_FLASH_PAGE:
258 cc_write_flash_page(cmddatalong[0]);
261 case CC_WIPEFLASHBUFFER:
262 for(i=0xf000;i<0xf800;i++)
263 cc_pokedatabyte(i,0xFF);
266 case CC_MASS_ERASE_FLASH:
268 case CC_PROGRAM_FLASH:
269 debugstr("This Chipcon command is not yet implemented.");
270 txdata(app,NOK,0);//TODO implement me.
275 //! Set the Chipcon's Program Counter
276 void cc_set_pc(u32 adr){
277 cmddata[0]=0x02; //SetPC
278 cmddata[1]=((adr>>8)&0xff); //HIBYTE
279 cmddata[2]=adr&0xff; //LOBYTE
284 //! Erase all of a Chipcon's memory.
285 void cc_chip_erase(){
286 cmddata[0]=CCCMD_CHIP_ERASE; //0x14
290 //! Write the configuration byte.
291 void cc_wr_config(unsigned char config){
292 cmddata[0]=CCCMD_WR_CONFIG; //0x1D
302 //debugstr("Locking chip.");
303 cc_wr_config(1);//Select Info Flash
304 if(!(cc_rd_config()&1))
305 debugstr("Config forgotten!");
309 cc_pokedatabyte(0xf000+i,0);
310 cc_write_flash_page(0);
311 if(cc_peekcodebyte(0))
312 debugstr("Failed to clear info flash byte.");
316 debugstr("Stuck in info flash mode!");
319 //! Read the configuration byte.
320 unsigned char cc_rd_config(){
321 cmddata[0]=CCCMD_RD_CONFIG; //0x24
328 //! Read the status register
329 unsigned char cc_read_status(){
330 cmddata[0]=CCCMD_READ_STATUS; //0x3f
336 //! Read the CHIP ID bytes.
337 unsigned short cc_get_chip_id(){
338 cmddata[0]=CCCMD_GET_CHIP_ID; //0x68
343 //Find the flash word size.
348 flash_word_size=0x02;
349 //debugstr("2 bytes/flash word");
352 debugstr("Warning: Guessing flash word size.");
355 //debugstr("4 bytes/flash word");
356 flash_word_size=0x04;
361 return cmddataword[0];
364 //! Populates flash buffer in xdata.
365 void cc_write_flash_buffer(u8 *data, u16 len){
366 cc_write_xdata(0xf000, data, len);
368 //! Populates flash buffer in xdata.
369 void cc_write_xdata(u16 adr, u8 *data, u16 len){
371 for(i=0; i<len; i++){
372 cc_pokedatabyte(adr+i,
378 //32-bit words, 2KB pages
379 //0x20 0x00 for CC2430, CC1110
380 #define HIBYTE_WORDS_PER_FLASH_PAGE 0x02
381 #define LOBYTE_WORDS_PER_FLASH_PAGE 0x00
383 /** Ugh, this varies by chip.
387 //#define FLASHPAGE_SIZE 0x400
388 #define MAXFLASHPAGE_SIZE 0x800
389 #define MINFLASHPAGE_SIZE 0x400
392 //32 bit words on CC2430
393 //16 bit words on CC1110
394 //#define FLASH_WORD_SIZE 0x2
395 u8 flash_word_size = 0; //0x02;
398 /* Flash Write Timing
405 32 | 0x2A (Modula.si)
409 const u8 flash_routine[] = {
413 0x00,//#imm=((address >> 8) / FLASH_WORD_SIZE) & 0x7E,
415 //0x75, 0xAB, 0x23, //Set FWT per clock
416 0x75, 0xAC, 0x00, // MOV FADDRL, #00;
418 0x75, 0xAE, 0x01, // MOV FLC, #01H; // ERASE
419 // ; Wait for flash erase to complete
420 0xE5, 0xAE, // eraseWaitLoop: MOV A, FLC;
421 0x20, 0xE7, 0xFB, // JB ACC_BUSY, eraseWaitLoop;
423 /* End erase page. */
424 // ; Initialize the data pointer
425 0x90, 0xF0, 0x00, // MOV DPTR, #0F000H;
427 0x7F, HIBYTE_WORDS_PER_FLASH_PAGE, // MOV R7, #imm;
428 0x7E, LOBYTE_WORDS_PER_FLASH_PAGE, // MOV R6, #imm;
429 0x75, 0xAE, 0x02, // MOV FLC, #02H; // WRITE
432 0x7D, 0xde /*FLASH_WORD_SIZE*/, // writeLoop: MOV R5, #imm;
433 0xE0, // writeWordLoop: MOVX A, @DPTR;
435 0xF5, 0xAF, // MOV FWDATA, A;
436 0xDD, 0xFA, // DJNZ R5, writeWordLoop;
437 // ; Wait for completion
438 0xE5, 0xAE, // writeWaitLoop: MOV A, FLC;
439 0x20, 0xE6, 0xFB, // JB ACC_SWBSY, writeWaitLoop;
440 0xDE, 0xF1, // DJNZ R6, writeLoop;
441 0xDF, 0xEF, // DJNZ R7, writeLoop;
442 // ; Done, fake a breakpoint
447 //! Copies flash buffer to flash.
448 void cc_write_flash_page(u32 adr){
449 //Assumes that page has already been written to XDATA 0xF000
450 //debugstr("Flashing 2kb at 0xF000 to given adr.");
452 if(adr&(MINFLASHPAGE_SIZE-1)){
453 debugstr("Flash page address is not on a page boundary. Aborting.");
457 if(flash_word_size==0){
458 debugstr("Flash word size is wrong.");
463 //WRITE_XDATA_MEMORY(IN: 0xF000 + FLASH_PAGE_SIZE, sizeof(routine), routine);
464 cc_write_xdata(0xF000+MAXFLASHPAGE_SIZE,
465 (u8*) flash_routine, sizeof(flash_routine));
466 //Patch routine's third byte with
467 //((address >> 8) / FLASH_WORD_SIZE) & 0x7E
468 cc_pokedatabyte(0xF000+MAXFLASHPAGE_SIZE+2,
469 ((adr>>8)/flash_word_size)&0x7E);
470 //Patch routine to define FLASH_WORD_SIZE
471 if(flash_routine[25]!=0xde)
472 debugstr("Ugly patching code failing in chipcon.c");
473 cc_pokedatabyte(0xF000+MAXFLASHPAGE_SIZE+25,
476 //debugstr("Wrote flash routine.");
479 //MOV MEMCTR, (bank * 16) + 1;
484 //debugstr("Loaded bank info.");
486 cc_set_pc(0xf000+MAXFLASHPAGE_SIZE);//execute code fragment
489 //debugstr("Executing.");
492 while(!(cc_read_status()&CC_STATUS_CPUHALTED)){
493 P1OUT^=1;//blink LED while flashing
497 //debugstr("Done flashing.");
499 P1OUT&=~1;//clear LED
503 unsigned short cc_get_pc(){
504 cmddata[0]=CCCMD_GET_PC; //0x28
509 return cmddataword[0];
512 //! Set a hardware breakpoint.
513 void cc_set_hw_brkpnt(unsigned short adr){
514 debugstr("FIXME: This certainly won't work.");
524 cmddata[0]=CCCMD_HALT; //0x44
531 cmddata[0]=CCCMD_RESUME; //0x4C
538 //! Step an instruction
539 void cc_step_instr(){
540 cmddata[0]=CCCMD_STEP_INSTR; //0x5C
546 //! Debug an instruction.
547 void cc_debug_instr(unsigned char len){
548 //Bottom two bits of command indicate length.
549 unsigned char cmd=CCCMD_DEBUG_INSTR+(len&0x3); //0x54+len
551 cctrans8(cmd); //Second command code
552 cccmd(len&0x3); //Command itself.
557 //! Debug an instruction, for local use.
558 unsigned char cc_debug(unsigned char len,
562 unsigned char cmd=CCCMD_DEBUG_INSTR+(len&0x3);//0x54+len
572 return cctrans8(0x00);
575 //! Fetch a byte of code memory.
576 unsigned char cc_peekcodebyte(unsigned long adr){
577 /** See page 9 of SWRA124 */
578 unsigned char bank=adr>>15,
584 //MOV MEMCTR, (bank*16)+1
585 cc_debug(3, 0x75, 0xC7, (bank<<4) + 1);
587 cc_debug(3, 0x90, hb, lb);
591 cc_debug(2, 0xE4, 0, 0);
593 toret=cc_debug(3, 0x93, 0, 0);
595 //cc_debug(1, 0xA3, 0, 0);
601 //! Set a byte of data memory.
602 unsigned char cc_pokedatabyte(unsigned int adr,
609 cc_debug(3, 0x90, hb, lb);
611 cc_debug(2, 0x74, val, 0);
613 cc_debug(1, 0xF0, 0, 0);
617 DEBUG_INSTR(IN: 0x90, HIBYTE(address), LOBYTE(address), OUT: Discard);
618 for (n = 0; n < count; n++) {
619 DEBUG_INSTR(IN: 0x74, inputArray[n], OUT: Discard);
620 DEBUG_INSTR(IN: 0xF0, OUT: Discard);
621 DEBUG_INSTR(IN: 0xA3, OUT: Discard);
626 //! Fetch a byte of data memory.
627 unsigned char cc_peekdatabyte(unsigned int adr){
633 cc_debug(3, 0x90, hb, lb);
635 //Must be 2, perhaps for clocking?
636 return cc_debug(3, 0xE0, 0, 0);
640 //! Fetch a byte of IRAM.
641 u8 cc_peekirambyte(u8 adr){
643 cc_debug(2, 0xE4, 0, 0);
645 return cc_debug(3, 0xE5, adr, 0);
648 //! Write a byte of IRAM.
649 u8 cc_pokeirambyte(u8 adr, u8 val){
651 cc_debug(2, 0xE4, 0, 0);
653 return cc_debug(3, 0x75, adr, val);
654 //return cc_debug(3, 0x75, val, adr);