2 \author Travis Goodspeed
3 \brief Chipcon 8051 debugging.
7 //This is like SPI, except that you read or write, not both.
9 /* N.B. The READ verb performs a write of all (any) supplied data,
10 then reads a single byte reply from the target. The WRITE verb
23 /* Concerning clock rates, the maximimum clock rates are defined on
24 page 4 of the spec. They vary, but are roughly 30MHz. Raising
25 this clock rate might allow for clock glitching, but the GoodFET
26 isn't sufficient fast for that. Perhaps a 200MHz ARM or an FPGA in
31 //MISO and MOSI are the same pin, direction changes.
37 //This could be more accurate.
38 //Does it ever need to be?
40 //#define CCDELAY(x) delay(x)
43 #define SETMOSI P5OUT|=MOSI
44 #define CLRMOSI P5OUT&=~MOSI
45 #define SETCLK P5OUT|=SCK
46 #define CLRCLK P5OUT&=~SCK
47 #define READMISO (P5IN&MISO?1:0)
49 #define CCWRITE P5DIR|=MOSI
50 #define CCREAD P5DIR&=~MISO
52 //! Set up the pins for CC mode. Does not init debugger.
60 /* 33 cycle critical region
61 0000000e <ccdebuginit>:
62 e: f2 d0 0d 00 bis.b #13, &0x0031 ;5 cycles
64 14: f2 c2 31 00 bic.b #8, &0x0031 ;4 cycles
65 18: d2 c3 31 00 bic.b #1, &0x0031 ;4
66 1c: f2 e2 31 00 xor.b #8, &0x0031 ;4
67 20: f2 e2 31 00 xor.b #8, &0x0031 ;4
68 24: f2 e2 31 00 xor.b #8, &0x0031 ;4
69 28: f2 e2 31 00 xor.b #8, &0x0031 ;4
70 2c: d2 d3 31 00 bis.b #1, &0x0031 ;4
75 //! Initialize the debugger
77 //Port output BUT NOT DIRECTION is set at start.
80 //delay(30); //So the beginning is ready for glitching.
82 //Two positive debug clock pulses while !RST is low.
83 //Take RST low, pulse twice, then high.
91 P5OUT^=SCK; //Unnecessary.
98 //! Read and write a CC bit.
99 unsigned char cctrans8(unsigned char byte){
101 //This function came from the SPI Wikipedia article.
104 for (bit = 0; bit < 8; bit++) {
105 /* write MOSI on trailing edge of previous clock */
112 /* half a clock cycle before leading/rising edge */
116 /* half a clock cycle before trailing/falling edge */
119 /* read MISO on trailing edge */
127 //! Send a command from txbytes.
128 void cccmd(unsigned char len){
132 cctrans8(cmddata[i]);
135 //! Fetch a reply, usually 1 byte.
136 void ccread(unsigned char len){
140 cmddata[i]=cctrans8(0);
143 //! Handles a monitor command.
144 void cchandle(unsigned char app,
147 //Always init. Might help with buggy lines.
153 //CC_PEEK and CC_POKE will come later.
155 cmddata[0]=cc_peekirambyte(cmddata[0]);
159 cmddata[0]=cc_pokeirambyte(cmddata[0],cmddata[1]);
162 case READ: //Write a command and return 1-byte reply.
168 case WRITE: //Write a command with no reply.
172 case START://enter debugger
176 case STOP://exit debugger
177 //Take RST low, then high.
194 cc_wr_config(cmddata[0]);
207 //no break, return status
212 case CC_SET_HW_BRKPNT:
213 cc_set_hw_brkpnt(cmddataword[0]);
232 case CC_STEP_REPLACE:
233 txdata(app,NOK,0);//TODO add me
236 cmddataword[0]=cc_get_chip_id();
242 case CC_READ_CODE_MEMORY:
243 cmddata[0]=cc_peekcodebyte(cmddataword[0]);
246 case CC_READ_XDATA_MEMORY:
247 cmddata[0]=cc_peekdatabyte(cmddataword[0]);
250 case CC_WRITE_XDATA_MEMORY:
251 cmddata[0]=cc_pokedatabyte(cmddataword[0], cmddata[2]);
255 cc_set_pc(cmddatalong[0]);
258 case CC_WRITE_FLASH_PAGE:
259 cc_write_flash_page(cmddatalong[0]);
262 case CC_WIPEFLASHBUFFER:
263 for(i=0xf000;i<0xf800;i++)
264 cc_pokedatabyte(i,0xFF);
267 case CC_MASS_ERASE_FLASH:
269 case CC_PROGRAM_FLASH:
270 debugstr("This Chipcon command is not yet implemented.");
271 txdata(app,NOK,0);//TODO implement me.
276 //! Set the Chipcon's Program Counter
277 void cc_set_pc(u32 adr){
278 cmddata[0]=0x02; //SetPC
279 cmddata[1]=((adr>>8)&0xff); //HIBYTE
280 cmddata[2]=adr&0xff; //LOBYTE
285 //! Erase all of a Chipcon's memory.
286 void cc_chip_erase(){
287 cmddata[0]=CCCMD_CHIP_ERASE; //0x14
291 //! Write the configuration byte.
292 void cc_wr_config(unsigned char config){
293 cmddata[0]=CCCMD_WR_CONFIG; //0x1D
303 //debugstr("Locking chip.");
304 cc_wr_config(1);//Select Info Flash
305 if(!(cc_rd_config()&1))
306 debugstr("Config forgotten!");
310 cc_pokedatabyte(0xf000+i,0);
311 cc_write_flash_page(0);
312 if(cc_peekcodebyte(0))
313 debugstr("Failed to clear info flash byte.");
317 debugstr("Stuck in info flash mode!");
320 //! Read the configuration byte.
321 unsigned char cc_rd_config(){
322 cmddata[0]=CCCMD_RD_CONFIG; //0x24
329 //! Read the status register
330 unsigned char cc_read_status(){
331 cmddata[0]=CCCMD_READ_STATUS; //0x3f
337 //! Read the CHIP ID bytes.
338 unsigned short cc_get_chip_id(){
339 cmddata[0]=CCCMD_GET_CHIP_ID; //0x68
344 //Find the flash word size.
350 //debugstr("2 bytes/flash word");
351 flash_word_size=0x02;
354 //debugstr("Warning: Guessing flash word size.");
359 //debugstr("4 bytes/flash word");
360 flash_word_size=0x04;
365 return cmddataword[0];
368 //! Populates flash buffer in xdata.
369 void cc_write_flash_buffer(u8 *data, u16 len){
370 cc_write_xdata(0xf000, data, len);
372 //! Populates flash buffer in xdata.
373 void cc_write_xdata(u16 adr, u8 *data, u16 len){
375 for(i=0; i<len; i++){
376 cc_pokedatabyte(adr+i,
382 //32-bit words, 2KB pages
383 //0x20 0x00 for CC2430, CC1110
384 #define HIBYTE_WORDS_PER_FLASH_PAGE 0x02
385 #define LOBYTE_WORDS_PER_FLASH_PAGE 0x00
387 /** Ugh, this varies by chip.
391 //#define FLASHPAGE_SIZE 0x400
392 #define MAXFLASHPAGE_SIZE 0x800
393 #define MINFLASHPAGE_SIZE 0x400
396 //32 bit words on CC2430
397 //16 bit words on CC1110
398 //#define FLASH_WORD_SIZE 0x2
399 u8 flash_word_size = 0; //0x02;
402 /* Flash Write Timing
409 32 | 0x2A (Modula.si)
413 const u8 flash_routine[] = {
417 0x00,//#imm=((address >> 8) / FLASH_WORD_SIZE) & 0x7E,
419 //0x75, 0xAB, 0x23, //Set FWT per clock
420 0x75, 0xAC, 0x00, // MOV FADDRL, #00;
422 0x75, 0xAE, 0x01, // MOV FLC, #01H; // ERASE
423 // ; Wait for flash erase to complete
424 0xE5, 0xAE, // eraseWaitLoop: MOV A, FLC;
425 0x20, 0xE7, 0xFB, // JB ACC_BUSY, eraseWaitLoop;
427 /* End erase page. */
428 // ; Initialize the data pointer
429 0x90, 0xF0, 0x00, // MOV DPTR, #0F000H;
431 0x7F, HIBYTE_WORDS_PER_FLASH_PAGE, // MOV R7, #imm;
432 0x7E, LOBYTE_WORDS_PER_FLASH_PAGE, // MOV R6, #imm;
433 0x75, 0xAE, 0x02, // MOV FLC, #02H; // WRITE
436 0x7D, 0xde /*FLASH_WORD_SIZE*/, // writeLoop: MOV R5, #imm;
437 0xE0, // writeWordLoop: MOVX A, @DPTR;
439 0xF5, 0xAF, // MOV FWDATA, A;
440 0xDD, 0xFA, // DJNZ R5, writeWordLoop;
441 // ; Wait for completion
442 0xE5, 0xAE, // writeWaitLoop: MOV A, FLC;
443 0x20, 0xE6, 0xFB, // JB ACC_SWBSY, writeWaitLoop;
444 0xDE, 0xF1, // DJNZ R6, writeLoop;
445 0xDF, 0xEF, // DJNZ R7, writeLoop;
446 // ; Done, fake a breakpoint
451 //! Copies flash buffer to flash.
452 void cc_write_flash_page(u32 adr){
453 //Assumes that page has already been written to XDATA 0xF000
454 //debugstr("Flashing 2kb at 0xF000 to given adr.");
456 if(adr&(MINFLASHPAGE_SIZE-1)){
457 debugstr("Flash page address is not on a page boundary. Aborting.");
461 if(flash_word_size!=2 && flash_word_size!=4){
462 debugstr("Flash word size is wrong, aborting write to");
468 //WRITE_XDATA_MEMORY(IN: 0xF000 + FLASH_PAGE_SIZE, sizeof(routine), routine);
469 cc_write_xdata(0xF000+MAXFLASHPAGE_SIZE,
470 (u8*) flash_routine, sizeof(flash_routine));
471 //Patch routine's third byte with
472 //((address >> 8) / FLASH_WORD_SIZE) & 0x7E
473 cc_pokedatabyte(0xF000+MAXFLASHPAGE_SIZE+2,
474 ((adr>>8)/flash_word_size)&0x7E);
475 //Patch routine to define FLASH_WORD_SIZE
476 if(flash_routine[25]!=0xde)
477 debugstr("Ugly patching code failing in chipcon.c");
478 cc_pokedatabyte(0xF000+MAXFLASHPAGE_SIZE+25,
481 //debugstr("Wrote flash routine.");
483 //MOV MEMCTR, (bank * 16) + 1;
488 //debugstr("Loaded bank info.");
490 cc_set_pc(0xf000+MAXFLASHPAGE_SIZE);//execute code fragment
493 //debugstr("Executing.");
496 while(!(cc_read_status()&CC_STATUS_CPUHALTED)){
497 PLEDOUT^=PLEDPIN;//blink LED while flashing
501 //debugstr("Done flashing.");
503 PLEDOUT&=~PLEDPIN;//clear LED
507 unsigned short cc_get_pc(){
508 cmddata[0]=CCCMD_GET_PC; //0x28
513 return cmddataword[0];
516 //! Set a hardware breakpoint.
517 void cc_set_hw_brkpnt(unsigned short adr){
518 debugstr("FIXME: This certainly won't work.");
528 cmddata[0]=CCCMD_HALT; //0x44
535 cmddata[0]=CCCMD_RESUME; //0x4C
542 //! Step an instruction
543 void cc_step_instr(){
544 cmddata[0]=CCCMD_STEP_INSTR; //0x5C
550 //! Debug an instruction.
551 void cc_debug_instr(unsigned char len){
552 //Bottom two bits of command indicate length.
553 unsigned char cmd=CCCMD_DEBUG_INSTR+(len&0x3); //0x54+len
555 cctrans8(cmd); //Second command code
556 cccmd(len&0x3); //Command itself.
561 //! Debug an instruction, for local use.
562 unsigned char cc_debug(unsigned char len,
566 unsigned char cmd=CCCMD_DEBUG_INSTR+(len&0x3);//0x54+len
576 return cctrans8(0x00);
579 //! Fetch a byte of code memory.
580 unsigned char cc_peekcodebyte(unsigned long adr){
581 /** See page 9 of SWRA124 */
582 unsigned char bank=adr>>15,
588 //MOV MEMCTR, (bank*16)+1
589 cc_debug(3, 0x75, 0xC7, (bank<<4) + 1);
591 cc_debug(3, 0x90, hb, lb);
595 cc_debug(2, 0xE4, 0, 0);
597 toret=cc_debug(3, 0x93, 0, 0);
599 //cc_debug(1, 0xA3, 0, 0);
605 //! Set a byte of data memory.
606 unsigned char cc_pokedatabyte(unsigned int adr,
613 cc_debug(3, 0x90, hb, lb);
615 cc_debug(2, 0x74, val, 0);
617 cc_debug(1, 0xF0, 0, 0);
621 DEBUG_INSTR(IN: 0x90, HIBYTE(address), LOBYTE(address), OUT: Discard);
622 for (n = 0; n < count; n++) {
623 DEBUG_INSTR(IN: 0x74, inputArray[n], OUT: Discard);
624 DEBUG_INSTR(IN: 0xF0, OUT: Discard);
625 DEBUG_INSTR(IN: 0xA3, OUT: Discard);
630 //! Fetch a byte of data memory.
631 unsigned char cc_peekdatabyte(unsigned int adr){
637 cc_debug(3, 0x90, hb, lb);
639 //Must be 2, perhaps for clocking?
640 return cc_debug(3, 0xE0, 0, 0);
644 //! Fetch a byte of IRAM.
645 u8 cc_peekirambyte(u8 adr){
647 cc_debug(2, 0xE4, 0, 0);
649 return cc_debug(3, 0xE5, adr, 0);
652 //! Write a byte of IRAM.
653 u8 cc_pokeirambyte(u8 adr, u8 val){
655 cc_debug(2, 0xE4, 0, 0);
657 return cc_debug(3, 0x75, adr, val);
658 //return cc_debug(3, 0x75, val, adr);