1 // ARM Debug Interface version 5 (cortex and above)
2 // from the ARM Debug Interface v5 Architecture Specification (IHI 0031A) document:
3 // "Logically, the ARM Debug Interface (ADI) consists of:
4 // * A number of registrs that are private to the ADI. These are referred to as the Debug Access Port (DAP) Registers
5 // * A means to access the DAP registers
6 // * A means to access the debug registers of the debug components to which the ADI is connected
8 // Because the DAP logically consists of two parts, the Debug Port and Access Ports, it must support two types of access:
9 // * Access to the Debug Port (DP) registers. This is provided by Debug Port accesses (DPACC).
10 // * Access to Access Port (AP) registers. This is provided by Access Port accesses (APACC).
11 // An ADI can include multiple Access Ports."
16 //////// lower levels - "Debug Ports"////////
17 //// Serial Wire Debug protocol
18 // the sw-dp is based on the coresight serial wire interface and can be implemented as either a synchronous or async interface (yay! *NOT*)
20 // swd protocol comms consists of a three-phase protocol:
21 // * host-to-target packet req
22 // * target-to-host ack
23 // * data-transfer if necessary, either direction depending on the packet req.
27 //// JTAG debug protocol
28 // as with arm7tdmi will soon be, we're going to live at Select DR state as home state. this allows each transaction to finish to a known state. it's more for mental peace more than anything, since the old way works... but the mental understanding that the tap may either be in exit2 or runtest/idle is a hack at best.
33 //////// mid-levels - resource interface, or "Access Ports" //////// - elected for pythonyness
34 // "An AP is responsible for accessing debug component registers such as processor debug logic, ETM and trace port registers. These accesses are made in response to APACC accesses in a manner defined by the AP."
44 ///////////////////////////////////////////////////////////////////////////////////////////////////
45 //! Handles ARM7TDMI JTAG commands. Forwards others to JTAG.
46 void adiv5handle(unsigned char app, unsigned char verb, unsigned long len){
56 cmddataword[0] = jtagarm_shift_ir(cmddata[0], cmddata[1]);
63 cmddatalong[0] = jtagtransn(cmddatalong[1],cmddata[0]-32,cmddata[1]|NOEND);
64 cmddatalong[1] = jtagtransn(cmddatalong[2],32,cmddata[1]);
67 cmddatalong[0] = jtagtransn(cmddatalong[1],cmddata[0],cmddata[1]);
70 tapstate = (cmddata[1]&NORETIDLE)>0?Update_DR:RunTest_Idle;
72 case JTAGADI_DEBUG_INSTR:
73 cmddatalong[0] = adiv5_instr_primitive(cmddatalong[0],cmddata[4]);
76 case JTAGADI_GET_REGISTER:
78 cmddatalong[0] = adiv5_get_register(val);
81 case JTAGADI_SET_REGISTER:
82 adiv5_set_register(cmddatalong[1], cmddatalong[0]);
85 case JTAG_RESETTARGET:
86 debugstr("RESET TARGET");
88 delay(cmddataword[0]);
94 //case JTAGARM7_STEP_INSTR:
95 /* case JTAGARM7_READ_CODE_MEMORY:
96 case JTAGARM7_WRITE_FLASH_PAGE:
97 case JTAGARM7_READ_FLASH_PAGE:
98 case JTAGARM7_MASS_ERASE_FLASH:
99 case JTAGARM7_PROGRAM_FLASH:
100 case JTAGARM7_LOCKCHIP:
101 case JTAGARM7_CHIP_ERASE:
104 jtaghandle(app,verb,len);