2 \author Travis Goodspeed <travis at radiantmachines.com>
3 \brief MSP430 JTAG (16-bit)
11 unsigned int jtag430mode=MSP430X2MODE;
13 //! Set the program counter.
14 void jtag430_setpc(unsigned int adr){
15 jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
16 jtag_dr_shift16(0x3401);// release low byte
17 jtag_ir_shift8(IR_DATA_16BIT);
18 jtag_dr_shift16(0x4030);//Instruction to load PC
21 jtag_dr_shift16(adr);// Value for PC
23 jtag_ir_shift8(IR_ADDR_CAPTURE);
25 CLRTCLK ;// Now PC is set to "PC_Value"
26 jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
27 jtag_dr_shift16(0x2401);// low byte controlled by JTAG
31 void jtag430_haltcpu(){
32 //jtag430_setinstrfetch();
34 jtag_ir_shift8(IR_DATA_16BIT);
35 jtag_dr_shift16(0x3FFF);//JMP $+0
38 jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
39 jtag_dr_shift16(0x2409);//set JTAG_HALT bit
44 void jtag430_releasecpu(){
46 jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
47 jtag_dr_shift16(0x2401);
48 jtag_ir_shift8(IR_ADDR_CAPTURE);
52 //! Read data from address
53 unsigned int jtag430_readmem(unsigned int adr){
58 jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
61 jtag_dr_shift16(0x2409);//word read
63 jtag_dr_shift16(0x2419);//byte read
64 jtag_ir_shift8(IR_ADDR_16BIT);
65 jtag_dr_shift16(adr);//address
66 jtag_ir_shift8(IR_DATA_TO_ADDR);
70 toret=jtag_dr_shift16(0x0000);//16 bit return
75 //! Write data to address.
76 void jtag430_writemem(unsigned int adr, unsigned int data){
78 jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
80 jtag_dr_shift16(0x2408);//word write
82 jtag_dr_shift16(0x2418);//byte write
83 jtag_ir_shift8(IR_ADDR_16BIT);
85 jtag_ir_shift8(IR_DATA_TO_ADDR);
86 jtag_dr_shift16(data);
90 //! Write data to flash memory. Must be preconfigured.
91 void jtag430_writeflashword(unsigned int adr, unsigned int data){
94 jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
95 jtag_dr_shift16(0x2408);//word write
96 jtag_ir_shift8(IR_ADDR_16BIT);
98 jtag_ir_shift8(IR_DATA_TO_ADDR);
99 jtag_dr_shift16(data);
102 //Return to read mode.
104 jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
105 jtag_dr_shift16(0x2409);
108 jtag430_writemem(adr,data);
110 jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
111 jtag_dr_shift16(0x2409);
115 jtag430_tclk_flashpulses(35); //35 standard
118 //! Configure flash, then write a word.
119 void jtag430_writeflash(unsigned int adr, unsigned int data){
122 //FCTL1=0xA540, enabling flash write
123 jtag430_writemem(0x0128, 0xA540);
124 //FCTL2=0xA540, selecting MCLK as source, DIV=1
125 jtag430_writemem(0x012A, 0xA540);
126 //FCTL3=0xA500, should be 0xA540 for Info Seg A on 2xx chips.
127 jtag430_writemem(0x012C, 0xA500); //all but info flash.
129 //Write the word itself.
130 jtag430_writeflashword(adr,data);
132 //FCTL1=0xA500, disabling flash write
133 jtag430_writemem(0x0128, 0xA500);
135 //jtag430_releasecpu();
145 jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
146 jtag_dr_shift16(0x2C01); // apply
147 jtag_dr_shift16(0x2401); // remove
153 jtagid = jtag_ir_shift8(IR_ADDR_CAPTURE); // get JTAG identifier
156 jtag430_writemem(0x0120, 0x5A80); // Diabled Watchdog
161 #define ERASE_GLOB 0xA50E
162 #define ERASE_ALLMAIN 0xA50C
163 #define ERASE_MASS 0xA506
164 #define ERASE_MAIN 0xA504
165 #define ERASE_SGMT 0xA502
167 //! Configure flash, then write a word.
168 void jtag430_eraseflash(unsigned int mode, unsigned int adr, unsigned int count){
172 jtag430_writemem(0x0128, mode);
173 //FCTL2=0xA540, selecting MCLK as source, DIV=1
174 jtag430_writemem(0x012A, 0xA540);
175 //FCTL3=0xA500, should be 0xA540 for Info Seg A on 2xx chips.
176 jtag430_writemem(0x012C, 0xA500);
178 //Write the erase word.
179 jtag430_writemem(adr, 0x55AA);
180 //Return to read mode.
182 jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
183 jtag_dr_shift16(0x2409);
186 jtag430_tclk_flashpulses(count);
188 //FCTL1=0xA500, disabling flash write
189 jtag430_writemem(0x0128, 0xA500);
191 //jtag430_releasecpu();
195 //! Reset the TAP state machine.
196 void jtag430_resettap(){
204 // Navigate to reset state.
205 // Should be at least six.
220 Sometimes this isn't necessary. */
232 //! Start JTAG, take pins
233 void jtag430_start(){
236 //Known-good starting position.
237 //Might be unnecessary.
242 //Entry sequence from Page 67 of SLAU265A for 4-wire MSP430 JTAG
253 //Perform a reset and disable watchdog.
255 jtag430_writemem(0x120,0x5a80);//disable watchdog
260 //! Set CPU to Instruction Fetch
261 void jtag430_setinstrfetch(){
263 jtag_ir_shift8(IR_CNTRL_SIG_CAPTURE);
265 // Wait until instruction fetch state.
267 if (jtag_dr_shift16(0x0000) & 0x0080)
275 //! Handles classic MSP430 JTAG commands. Forwards others to JTAG.
276 void jtag430handle(unsigned char app,
282 //debugstr("Classic MSP430 handler.");
288 //TAP setup, fuse check
293 case JTAG430_HALTCPU:
297 case JTAG430_RELEASECPU:
298 jtag430_releasecpu();
301 case JTAG430_SETINSTRFETCH:
302 jtag430_setinstrfetch();
306 case JTAG430_READMEM:
310 //Fetch large blocks for bulk fetches,
311 //small blocks for individual peeks.
313 len=(cmddataword[2]);//always even.
318 txhead(app,verb,len);
321 val=jtag430_readmem(at);
325 serial_tx((val&0xFF00)>>8);
328 case JTAG430_WRITEMEM:
331 jtag430_writemem(cmddataword[0],cmddataword[2]);
332 cmddataword[0]=jtag430_readmem(cmddataword[0]);
335 case JTAG430_WRITEFLASH:
336 //debugstr("Poking flash memory.");
337 jtag430_writeflash(cmddataword[0],cmddataword[2]);
339 //Try again if failure.
340 if(cmddataword[0]!=jtag430_readmem(cmddataword[0]))
341 jtag430_writeflash(cmddataword[0],cmddataword[2]);
344 cmddataword[0]=jtag430_readmem(cmddataword[0]);
348 case JTAG430_ERASEFLASH:
349 jtag430_eraseflash(ERASE_MASS,0xFFFE,0x3000);
354 jtag430_setpc(cmddataword[0]);
358 case JTAG430_COREIP_ID:
359 case JTAG430_DEVICE_ID:
366 jtaghandle(app,verb,len);
368 //jtag430_resettap(); //DO NOT UNCOMMENT