2 \author Travis Goodspeed <travis at radiantmachines.com>
3 \brief MSP430 JTAG (16-bit)
10 //! Handles classic MSP430 JTAG commands. Forwards others to JTAG.
11 void jtag430_handle_fn(uint8_t const app,
15 // define the jtag430 app's app_t
16 app_t const jtag430_app = {
27 "\tThe JTAG430 app adds to the basic JTAG app\n"
28 "\tsupport for JTAG'ing MSP430 devices.\n"
31 unsigned int jtag430mode=MSP430X2MODE;
33 unsigned int drwidth=16;
35 //! Shift an address width of data
36 uint32_t jtag430_shift_addr( uint32_t addr )
38 if (!in_run_test_idle())
40 debugstr("Not in run-test-idle state");
44 // get intot the right state
46 jtag_shift_register();
48 // shift DR, then idle
49 return jtag_trans_n(addr, drwidth, MSB);
53 void jtag430_setr(u8 reg, u16 val){
54 jtag_ir_shift_8(IR_CNTRL_SIG_16BIT);
55 jtag_dr_shift_16(0x3401);// release low byte
56 jtag_ir_shift_8(IR_DATA_16BIT);
58 //0x4030 is "MOV #foo, r0"
59 //Right-most field is register, so 0x4035 loads r5
60 jtag_dr_shift_16(0x4030+reg);
63 jtag_dr_shift_16(val);// Value for the register
65 jtag_ir_shift_8(IR_ADDR_CAPTURE);
67 CLRTCLK ;// Now reg is set to new value.
68 jtag_ir_shift_8(IR_CNTRL_SIG_16BIT);
69 jtag_dr_shift_16(0x2401);// low byte controlled by JTAG
72 //! Set the program counter.
73 void jtag430_setpc(unsigned int adr){
78 void jtag430_haltcpu(){
79 //jtag430_setinstrfetch();
81 jtag_ir_shift_8(IR_DATA_16BIT);
82 jtag_dr_shift_16(0x3FFF);//JMP $+0
85 jtag_ir_shift_8(IR_CNTRL_SIG_16BIT);
86 jtag_dr_shift_16(0x2409);//set JTAG_HALT bit
91 void jtag430_releasecpu(){
93 //debugstr("Releasing target MSP430.");
96 jtag_ir_shift_8(IR_CNTRL_SIG_16BIT);
97 jtag_dr_shift_16(0x2C01); //Apply reset.
98 jtag_dr_shift_16(0x2401); //Release reset.
100 jtag_ir_shift_8(IR_CNTRL_SIG_RELEASE);
104 //! Read data from address
105 unsigned int jtag430_readmem(unsigned int adr){
110 jtag_ir_shift_8(IR_CNTRL_SIG_16BIT);
113 jtag_dr_shift_16(0x2409);//word read
115 jtag_dr_shift_16(0x2419);//byte read
116 jtag_ir_shift_8(IR_ADDR_16BIT);
117 jtag430_shift_addr(adr);//address
118 jtag_ir_shift_8(IR_DATA_TO_ADDR);
122 toret=jtag_dr_shift_16(0x0000);//16 bit return
127 //! Write data to address.
128 void jtag430_writemem(unsigned int adr, unsigned int data){
130 jtag_ir_shift_8(IR_CNTRL_SIG_16BIT);
132 jtag_dr_shift_16(0x2408);//word write
134 jtag_dr_shift_16(0x2418);//byte write
135 jtag_ir_shift_8(IR_ADDR_16BIT);
136 jtag430_shift_addr(adr);
137 jtag_ir_shift_8(IR_DATA_TO_ADDR);
138 jtag_dr_shift_16(data);
142 //! Write data to flash memory. Must be preconfigured.
143 void jtag430_writeflashword(unsigned int adr, unsigned int data){
146 jtag_ir_shift_8(IR_CNTRL_SIG_16BIT);
147 jtag_dr_shift_16(0x2408);//word write
148 jtag_ir_shift_8(IR_ADDR_16BIT);
149 jtag430_shift_addr(adr);
150 jtag_ir_shift_8(IR_DATA_TO_ADDR);
151 jtag_dr_shift_16(data);
154 //Return to read mode.
156 jtag_ir_shift_8(IR_CNTRL_SIG_16BIT);
157 jtag_dr_shift_16(0x2409);
160 jtag430_writemem(adr,data);
162 jtag_ir_shift_8(IR_CNTRL_SIG_16BIT);
163 jtag_dr_shift_16(0x2409);
167 jtag430_tclk_flashpulses(35); //35 standard
170 //! Configure flash, then write a word.
171 void jtag430_writeflash(unsigned int adr, unsigned int data){
174 //FCTL1=0xA540, enabling flash write
175 jtag430_writemem(0x0128, 0xA540);
176 //FCTL2=0xA540, selecting MCLK as source, DIV=1
177 jtag430_writemem(0x012A, 0xA540);
178 //FCTL3=0xA500, should be 0xA540 for Info Seg A on 2xx chips.
179 jtag430_writemem(0x012C, 0xA500); //all but info flash.
180 //if(jtag430_readmem(0x012C));
182 //Write the word itself.
183 jtag430_writeflashword(adr,data);
185 //FCTL1=0xA500, disabling flash write
186 jtag430_writemem(0x0128, 0xA500);
188 //jtag430_releasecpu();
196 jtag_ir_shift_8(IR_CNTRL_SIG_16BIT);
197 jtag_dr_shift_16(0x2C01); // apply
198 jtag_dr_shift_16(0x2401); // remove
204 jtagid = jtag_ir_shift_8(IR_ADDR_CAPTURE); // get JTAG identifier
207 jtag430_writemem(0x0120, 0x5A80); // Diabled Watchdog
212 #define ERASE_GLOB 0xA50E
213 #define ERASE_ALLMAIN 0xA50C
214 #define ERASE_MASS 0xA506
215 #define ERASE_MAIN 0xA504
216 #define ERASE_SGMT 0xA502
218 //! Configure flash, then write a word.
219 void jtag430_eraseflash(unsigned int mode, unsigned int adr, unsigned int count,
224 jtag430_writemem(0x0128, mode);
225 //FCTL2=0xA540, selecting MCLK as source, DIV=1
226 jtag430_writemem(0x012A, 0xA540);
227 //FCTL3=0xA500, should be 0xA540 for Info Seg A on 2xx chips.
229 jtag430_writemem(0x012C, 0xA540);
231 jtag430_writemem(0x012C, 0xA500);
233 //Write the erase word.
234 jtag430_writemem(adr, 0x55AA);
235 //Return to read mode.
237 jtag_ir_shift_8(IR_CNTRL_SIG_16BIT);
238 jtag_dr_shift_16(0x2409);
241 jtag430_tclk_flashpulses(count);
243 //FCTL1=0xA500, disabling flash write
244 jtag430_writemem(0x0128, 0xA500);
246 //jtag430_releasecpu();
250 //! Reset the TAP state machine.
251 void jtag430_resettap(){
259 // Navigate to reset state.
260 // Should be at least six.
273 Sometimes this isn't necessary. */
287 unsigned char jtag430x2_jtagid(){
289 jtagid = jtag_ir_shift_8(IR_BYPASS);
290 if(jtagid!=0x89 && jtagid!=0x91){
291 debugstr("Unknown JTAG ID");
296 //! Start JTAG, take pins
297 unsigned char jtag430x2_start(){
300 //Known-good starting position.
301 //Might be unnecessary.
307 //Entry sequence from Page 67 of SLAU265A for 4-wire MSP430 JTAG
320 //Perform a reset and disable watchdog.
321 return jtag430x2_jtagid();
325 //! Start JTAG, take pins
326 void jtag430_start(){
329 //Known-good starting position.
330 //Might be unnecessary.
337 //Entry sequence from Page 67 of SLAU265A for 4-wire MSP430 JTAG
349 //Perform a reset and disable watchdog.
351 jtag430_writemem(0x120,0x5a80);//disable watchdog
358 debugstr("Exiting JTAG.");
361 //Known-good starting position.
362 //Might be unnecessary.
368 //Entry sequence from Page 67 of SLAU265A for 4-wire MSP430 JTAG
377 //! Set CPU to Instruction Fetch
378 void jtag430_setinstrfetch(){
380 jtag_ir_shift_8(IR_CNTRL_SIG_CAPTURE);
382 // Wait until instruction fetch state.
384 if (jtag_dr_shift_16(0x0000) & 0x0080)
395 //! Handles classic MSP430 JTAG commands. Forwards others to JTAG.
396 void jtag430_handle_fn(uint8_t const app,
405 * Sometimes JTAG doesn't init correctly.
406 * This restarts the connection if the masked-rom
407 * chip ID cannot be read. Should print warning
408 * for testing server.
411 while((i=jtag430_readmem(0xff0))==0xFFFF){
412 debugstr("Reconnecting to target MSP430.");
421 debugstr("Using JTAG430 (instead of JTAG430X2)!");
426 jtag430mode=MSP430MODE;
428 /* So the way this works is that a width of 20 does some
429 backward-compatibility finagling, causing the correct value
430 to be exchanged for addresses on 16-bit chips as well as the
431 new MSP430X chips. (This has only been verified on the
432 MSP430F2xx family. TODO verify for others.)
437 //Perform a reset and disable watchdog.
439 jtag430_writemem(0x120,0x5a80);//disable watchdog
452 case JTAG430_HALTCPU:
456 case JTAG430_RELEASECPU:
457 jtag430_releasecpu();
460 case JTAG430_SETINSTRFETCH:
461 jtag430_setinstrfetch();
465 case JTAG430_READMEM:
469 //Fetch large blocks for bulk fetches,
470 //small blocks for individual peeks.
472 l=(cmddataword[2]);//always even.
478 for(i = 0; i < l; i += 2) {
480 val=jtag430_readmem(at);
484 serial_tx((val&0xFF00)>>8);
487 case JTAG430_WRITEMEM:
490 jtag430_writemem(cmddataword[0],cmddataword[2]);
491 cmddataword[0]=jtag430_readmem(cmddataword[0]);
494 case JTAG430_WRITEFLASH:
497 for(i=0;i<(len>>1)-2;i++){
498 //debugstr("Poking flash memory.");
499 jtag430_writeflash(at+(i<<1),cmddataword[i+2]);
500 //Reflash if needed. Try this twice to save grace?
501 if(cmddataword[i]!=jtag430_readmem(at))
502 jtag430_writeflash(at+(i<<1),cmddataword[i+2]);
505 //Return result of first write as a word.
506 cmddataword[0]=jtag430_readmem(cmddataword[0]);
510 case JTAG430_ERASEFLASH:
511 jtag430_eraseflash(ERASE_MASS,0xFFFE,0x3000,0);
514 case JTAG430_ERASEINFO:
515 jtag430_eraseflash(ERASE_SGMT,0x1000,0x3000,1);
520 //debughex("Setting PC.");
521 //debughex(cmddataword[0]);
522 jtag430_setpc(cmddataword[0]);
523 jtag430_releasecpu();
527 jtag430_setr(cmddata[0],cmddataword[1]);
531 //jtag430_getr(cmddata[0]);
532 debugstr("JTAG430_GETREG not yet implemented.");
533 cmddataword[0]=0xDEAD;
536 case JTAG430_COREIP_ID:
537 //cmddataword[0]=jtag430_coreid();
538 cmddataword[0]=0xdead;
541 case JTAG430_DEVICE_ID:
542 //cmddatalong[0]=jtag430_deviceid();
543 cmddataword[0]=0xdead;
544 cmddataword[1]=0xbeef;
548 (*(jtag_app.handle))(app,verb,len);
550 //jtag430_resettap(); //DO NOT UNCOMMENT