git.rot13.org Git - goodfet/blob - firmware/apps/jtag/jtag430.c

   1 /*! \file jtag430.c
   2   \author Travis Goodspeed <travis at radiantmachines.com>
   3   \brief MSP430 JTAG (16-bit)
   4 */
   5
   6 #include "platform.h"
   7 #include "command.h"
   8 #include "jtag430.h"
   9
  10 //! Handles classic MSP430 JTAG commands.  Forwards others to JTAG.
  11 void jtag430_handle_fn(uint8_t const app,
  12                        uint8_t const verb,
  13                        uint32_t const len);
  14
  15 // define the jtag430 app's app_t
  16 app_t const jtag430_app = {
  17
  18         /* app number */
  19         JTAG430,
  20
  21         /* handle fn */
  22         jtag430_handle_fn,
  23
  24         /* name */
  25         "JTAG430",
  26
  27         /* desc */
  28         "\tThe JTAG430 app adds to the basic JTAG app\n"
  29         "\tsupport for JTAG'ing MSP430 devices.\n"
  30 };
  31
  32 unsigned int jtag430mode=MSP430X2MODE;
  33
  34 //! Set a register.
  35 void jtag430_setr(u8 reg, u16 val){
  36   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
  37   jtag_dr_shift16(0x3401);// release low byte
  38   jtag_ir_shift8(IR_DATA_16BIT);
  39
  40   //0x4030 is "MOV #foo, r0"
  41   //Right-most field is register, so 0x4035 loads r5
  42   jtag_dr_shift16(0x4030+reg);
  43   CLRTCLK;
  44   SETTCLK;
  45   jtag_dr_shift16(val);// Value for the register
  46   CLRTCLK;
  47   jtag_ir_shift8(IR_ADDR_CAPTURE);
  48   SETTCLK;
  49   CLRTCLK ;// Now reg is set to new value.
  50   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
  51   jtag_dr_shift16(0x2401);// low byte controlled by JTAG
  52 }
  53
  54 //! Set the program counter.
  55 void jtag430_setpc(unsigned int adr){
  56   jtag430_setr(0,adr);
  57 }
  58
  59 //! Halt the CPU
  60 void jtag430_haltcpu(){
  61   //jtag430_setinstrfetch();
  62
  63   jtag_ir_shift8(IR_DATA_16BIT);
  64   jtag_dr_shift16(0x3FFF);//JMP $+0
  65
  66   CLRTCLK;
  67   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
  68   jtag_dr_shift16(0x2409);//set JTAG_HALT bit
  69   SETTCLK;
  70 }
  71
  72 //! Release the CPU
  73 void jtag430_releasecpu(){
  74   CLRTCLK;
  75   //debugstr("Releasing target MSP430.");
  76
  77   /*
  78   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
  79   jtag_dr_shift16(0x2C01); //Apply reset.
  80   jtag_dr_shift16(0x2401); //Release reset.
  81   */
  82   jtag_ir_shift8(IR_CNTRL_SIG_RELEASE);
  83   SETTCLK;
  84 }
  85
  86 //! Read data from address
  87 unsigned int jtag430_readmem(unsigned int adr){
  88   unsigned int toret;
  89   jtag430_haltcpu();
  90
  91   CLRTCLK;
  92   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
  93
  94   if(adr>0xFF)
  95     jtag_dr_shift16(0x2409);//word read
  96   else
  97     jtag_dr_shift16(0x2419);//byte read
  98   jtag_ir_shift8(IR_ADDR_16BIT);
  99   jtag_dr_shiftadr(adr);//address
 100   jtag_ir_shift8(IR_DATA_TO_ADDR);
 101   SETTCLK;
 102
 103   CLRTCLK;
 104   toret=jtag_dr_shift16(0x0000);//16 bit return
 105
 106   return toret;
 107 }
 108
 109 //! Write data to address.
 110 void jtag430_writemem(unsigned int adr, unsigned int data){
 111   CLRTCLK;
 112   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
 113   if(adr>0xFF)
 114     jtag_dr_shift16(0x2408);//word write
 115   else
 116     jtag_dr_shift16(0x2418);//byte write
 117   jtag_ir_shift8(IR_ADDR_16BIT);
 118   jtag_dr_shiftadr(adr);
 119   jtag_ir_shift8(IR_DATA_TO_ADDR);
 120   jtag_dr_shift16(data);
 121   SETTCLK;
 122 }
 123
 124 //! Write data to flash memory.  Must be preconfigured.
 125 void jtag430_writeflashword(unsigned int adr, unsigned int data){
 126
 127   CLRTCLK;
 128   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
 129   jtag_dr_shift16(0x2408);//word write
 130   jtag_ir_shift8(IR_ADDR_16BIT);
 131   jtag_dr_shiftadr(adr);
 132   jtag_ir_shift8(IR_DATA_TO_ADDR);
 133   jtag_dr_shift16(data);
 134   SETTCLK;
 135
 136   //Return to read mode.
 137   CLRTCLK;
 138   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
 139   jtag_dr_shift16(0x2409);
 140
 141   /*
 142   jtag430_writemem(adr,data);
 143   CLRTCLK;
 144   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
 145   jtag_dr_shift16(0x2409);
 146   */
 147
 148   //Pulse TCLK
 149   jtag430_tclk_flashpulses(35); //35 standard
 150 }
 151
 152 //! Configure flash, then write a word.
 153 void jtag430_writeflash(unsigned int adr, unsigned int data){
 154   jtag430_haltcpu();
 155
 156   //FCTL1=0xA540, enabling flash write
 157   jtag430_writemem(0x0128, 0xA540);
 158   //FCTL2=0xA540, selecting MCLK as source, DIV=1
 159   jtag430_writemem(0x012A, 0xA540);
 160   //FCTL3=0xA500, should be 0xA540 for Info Seg A on 2xx chips.
 161   jtag430_writemem(0x012C, 0xA500); //all but info flash.
 162   //if(jtag430_readmem(0x012C));
 163
 164   //Write the word itself.
 165   jtag430_writeflashword(adr,data);
 166
 167   //FCTL1=0xA500, disabling flash write
 168   jtag430_writemem(0x0128, 0xA500);
 169
 170   //jtag430_releasecpu();
 171 }
 172
 173
 174
 175 //! Power-On Reset
 176 void jtag430_por(){
 177   unsigned int jtagid;
 178
 179   // Perform Reset
 180   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
 181   jtag_dr_shift16(0x2C01); // apply
 182   jtag_dr_shift16(0x2401); // remove
 183   CLRTCLK;
 184   SETTCLK;
 185   CLRTCLK;
 186   SETTCLK;
 187   CLRTCLK;
 188   jtagid = jtag_ir_shift8(IR_ADDR_CAPTURE); // get JTAG identifier
 189   SETTCLK;
 190
 191   jtag430_writemem(0x0120, 0x5A80);   // Diabled Watchdog
 192 }
 193
 194
 195
 196 #define ERASE_GLOB 0xA50E
 197 #define ERASE_ALLMAIN 0xA50C
 198 #define ERASE_MASS 0xA506
 199 #define ERASE_MAIN 0xA504
 200 #define ERASE_SGMT 0xA502
 201
 202 //! Configure flash, then write a word.
 203 void jtag430_eraseflash(unsigned int mode, unsigned int adr, unsigned int count,
 204                         unsigned int info){
 205   jtag430_haltcpu();
 206
 207   //FCTL1= erase mode
 208   jtag430_writemem(0x0128, mode);
 209   //FCTL2=0xA540, selecting MCLK as source, DIV=1
 210   jtag430_writemem(0x012A, 0xA540);
 211   //FCTL3=0xA500, should be 0xA540 for Info Seg A on 2xx chips.
 212   if(info)
 213     jtag430_writemem(0x012C, 0xA540);
 214   else
 215     jtag430_writemem(0x012C, 0xA500);
 216
 217   //Write the erase word.
 218   jtag430_writemem(adr, 0x55AA);
 219   //Return to read mode.
 220   CLRTCLK;
 221   jtag_ir_shift8(IR_CNTRL_SIG_16BIT);
 222   jtag_dr_shift16(0x2409);
 223
 224   //Send the pulses.
 225   jtag430_tclk_flashpulses(count);
 226
 227   //FCTL1=0xA500, disabling flash write
 228   jtag430_writemem(0x0128, 0xA500);
 229
 230   //jtag430_releasecpu();
 231 }
 232
 233
 234 //! Reset the TAP state machine.
 235 void jtag430_resettap(){
 236   int i;
 237   // Settle output
 238   SETTDI; //430X2
 239   SETTMS;
 240   //SETTDI; //classic
 241   TCKTOCK;
 242
 243   // Navigate to reset state.
 244   // Should be at least six.
 245   for(i=0;i<4;i++){
 246     TCKTOCK;
 247   }
 248
 249   // test-logic-reset
 250   CLRTMS;
 251   TCKTOCK;
 252   SETTMS;
 253   // idle
 254
 255
 256   /* sacred, by spec.
 257      Sometimes this isn't necessary.  */
 258   // fuse check
 259   CLRTMS;
 260   delay(50);
 261   SETTMS;
 262   CLRTMS;
 263   delay(50);
 264   SETTMS;
 265   /**/
 266
 267 }
 268
 269 unsigned char jtagid;
 270
 271 //! Get the JTAG ID
 272 unsigned char jtag430x2_jtagid(){
 273   jtag430_resettap();
 274   jtagid=jtag_ir_shift8(IR_BYPASS);
 275   if(jtagid!=0x89 && jtagid!=0x91){
 276     debugstr("Unknown JTAG ID");
 277     debughex(jtagid);
 278   }
 279   return jtagid;
 280 }
 281 //! Start JTAG, take pins
 282 unsigned char jtag430x2_start(){
 283   jtagsetup();
 284
 285   //Known-good starting position.
 286   //Might be unnecessary.
 287   SETTST;
 288   SETRST;
 289
 290   delay(0xFFFF);
 291
 292   //Entry sequence from Page 67 of SLAU265A for 4-wire MSP430 JTAG
 293   CLRRST;
 294   delay(20);//10
 295   CLRTST;
 296
 297   delay(10);//5
 298   SETTST;
 299   msdelay(10);//5
 300   SETRST;
 301   P5DIR&=~RST;
 302
 303   delay(0xFFFF);
 304
 305   //Perform a reset and disable watchdog.
 306   return jtag430x2_jtagid();
 307 }
 308
 309
 310 //! Start JTAG, take pins
 311 void jtag430_start(){
 312   jtagsetup();
 313
 314   //Known-good starting position.
 315   //Might be unnecessary.
 316   SETTST;
 317   SETRST;
 318   delay(0xFFFF);
 319
 320
 321   #ifndef SBWREWRITE
 322   //Entry sequence from Page 67 of SLAU265A for 4-wire MSP430 JTAG
 323   CLRRST;
 324   delay(100); //100
 325   CLRTST;
 326   delay(50);  //50
 327   SETTST;
 328   delay(50);  //50
 329   SETRST;
 330   P5DIR&=~RST;
 331   delay(0xFFFF);
 332   #endif
 333
 334   //Perform a reset and disable watchdog.
 335   jtag430_por();
 336   jtag430_writemem(0x120,0x5a80);//disable watchdog
 337
 338   jtag430_haltcpu();
 339 }
 340
 341 //! Stop JTAG.
 342 void jtag430_stop(){
 343   debugstr("Exiting JTAG.");
 344   jtagsetup();
 345
 346   //Known-good starting position.
 347   //Might be unnecessary.
 348   //SETTST;
 349   CLRTST;
 350   SETRST;
 351   delay(0xFFFF);
 352
 353   //Entry sequence from Page 67 of SLAU265A for 4-wire MSP430 JTAG
 354   CLRRST;
 355   delay(0xFFFF);
 356   SETRST;
 357   //P5DIR&=~RST;
 358   //delay(0xFFFF);
 359
 360 }
 361
 362 //! Set CPU to Instruction Fetch
 363 void jtag430_setinstrfetch(){
 364
 365   jtag_ir_shift8(IR_CNTRL_SIG_CAPTURE);
 366
 367   // Wait until instruction fetch state.
 368   while(1){
 369     if (jtag_dr_shift16(0x0000) & 0x0080)
 370       return;
 371     CLRTCLK;
 372     SETTCLK;
 373   }
 374 }
 375
 376 //! Grab the core ID.
 377 unsigned int jtag430_coreid(){
 378   jtag_ir_shift8(IR_COREIP_ID);
 379   return jtag_dr_shift16(0);
 380 }
 381
 382 //! Grab the device ID.
 383 unsigned long jtag430_deviceid(){
 384   jtag_ir_shift8(IR_DEVICE_ID);
 385   return jtag_dr_shift20(0);
 386 }
 387
 388
 389
 390
 391 //! Handles classic MSP430 JTAG commands.  Forwards others to JTAG.
 392 void jtag430_handle_fn(uint8_t const app,
 393                                            uint8_t const verb,
 394                                            uint32_t const len)
 395 {
 396   unsigned long at, l;
 397   unsigned int i, val;
 398
 399
 400   /* FIXME
 401    * Sometimes JTAG doesn't init correctly.
 402    * This restarts the connection if the masked-rom
 403    * chip ID cannot be read.  Should print warning
 404    * for testing server.
 405    */
 406   if (jtagid!=0)
 407     while((i=jtag430_readmem(0xff0))==0xFFFF){
 408       debugstr("Reconnecting to target MSP430.");
 409       jtag430x2_start();
 410       PLEDOUT^=PLEDPIN;
 411     }
 412   PLEDOUT&=~PLEDPIN;
 413
 414
 415   switch(verb){
 416   case START:
 417     /* old method, classic MSP430.
 418     //Enter JTAG mode.
 419     jtag430x2_start();
 420     //TAP setup, fuse check
 421     jtag430_resettap();
 422
 423     cmddata[0]=jtag_ir_shift8(IR_BYPASS);
 424     txdata(app,verb,1);
 425     */
 426     jtag430x2_start();
 427     cmddata[0]=jtagid;
 428
 429     jtag430mode=MSP430MODE;
 430
 431     /* So the way this works is that a width of 20 does some
 432        backward-compatibility finagling, causing the correct value
 433        to be exchanged for addresses on 16-bit chips as well as the
 434        new MSP430X chips.  (This has only been verified on the
 435        MSP430F2xx family.  TODO verify for others.)
 436     */
 437
 438     drwidth=20;
 439
 440     //Perform a reset and disable watchdog.
 441     jtag430_por();
 442     jtag430_writemem(0x120,0x5a80);//disable watchdog
 443
 444     jtag430_haltcpu();
 445
 446     jtag430_resettap();
 447     txdata(app,verb,1);
 448
 449     break;
 450   case STOP:
 451     jtag430_stop();
 452     txdata(app,verb,0);
 453     break;
 454   case JTAG430_HALTCPU:
 455     jtag430_haltcpu();
 456     txdata(app,verb,0);
 457     break;
 458   case JTAG430_RELEASECPU:
 459     jtag430_releasecpu();
 460     txdata(app,verb,0);
 461     break;
 462   case JTAG430_SETINSTRFETCH:
 463     jtag430_setinstrfetch();
 464     txdata(app,verb,0);
 465     break;
 466
 467   case JTAG430_READMEM:
 468   case PEEK:
 469     at=cmddatalong[0];
 470
 471     //Fetch large blocks for bulk fetches,
 472     //small blocks for individual peeks.
 473     if(len>5)
 474       l=(cmddataword[2]);//always even.
 475     else
 476       l=2;
 477     l&=~1;//clear lsbit
 478
 479     txhead(app,verb,l);
 480     for(i = 0; i < l; i += 2) {
 481       jtag430_resettap();
 482       val=jtag430_readmem(at);
 483
 484       at+=2;
 485       serial_tx(val&0xFF);
 486       serial_tx((val&0xFF00)>>8);
 487     }
 488     break;
 489   case JTAG430_WRITEMEM:
 490   case POKE:
 491     jtag430_haltcpu();
 492     jtag430_writemem(cmddataword[0],cmddataword[2]);
 493     cmddataword[0]=jtag430_readmem(cmddataword[0]);
 494     txdata(app,verb,2);
 495     break;
 496     /*
 497   case JTAG430_WRITEFLASH:
 498
 499     //debugstr("Poking flash memory.");
 500     jtag430_writeflash(cmddataword[0],cmddataword[2]);
 501
 502     //Try again if failure.
 503     //if(cmddataword[2]!=jtag430_readmem(cmddataword[0]))
 504     //  jtag430_writeflash(cmddataword[0],cmddataword[2]);
 505
 506     //Return result.
 507     cmddataword[0]=jtag430_readmem(cmddataword[0]);
 508
 509     txdata(app,verb,2);
 510     break; */
 511   case JTAG430_WRITEFLASH:
 512     at=cmddataword[0];
 513
 514     for(i=0;i<(len>>1)-2;i++){
 515       //debugstr("Poking flash memory.");
 516       jtag430_writeflash(at+(i<<1),cmddataword[i+2]);
 517       //Reflash if needed.  Try this twice to save grace?
 518       if(cmddataword[i]!=jtag430_readmem(at))
 519         jtag430_writeflash(at+(i<<1),cmddataword[i+2]);
 520     }
 521
 522     //Return result of first write as a word.
 523     cmddataword[0]=jtag430_readmem(cmddataword[0]);
 524
 525     txdata(app,verb,2);
 526     break;
 527   case JTAG430_ERASEFLASH:
 528     jtag430_eraseflash(ERASE_MASS,0xFFFE,0x3000,0);
 529     txdata(app,verb,0);
 530     break;
 531   case JTAG430_ERASEINFO:
 532     jtag430_eraseflash(ERASE_SGMT,0x1000,0x3000,1);
 533     txdata(app,verb,0);
 534     break;
 535   case JTAG430_SETPC:
 536     jtag430_haltcpu();
 537     //debughex("Setting PC.");
 538     //debughex(cmddataword[0]);
 539     jtag430_setpc(cmddataword[0]);
 540     jtag430_releasecpu();
 541     txdata(app,verb,0);
 542     break;
 543   case JTAG430_SETREG:
 544     jtag430_setr(cmddata[0],cmddataword[1]);
 545     txdata(app,verb,0);
 546     break;
 547   case JTAG430_GETREG:
 548     //jtag430_getr(cmddata[0]);
 549     debugstr("JTAG430_GETREG not yet implemented.");
 550     cmddataword[0]=0xDEAD;
 551     txdata(app,verb,2);
 552     break;
 553   case JTAG430_COREIP_ID:
 554     cmddataword[0]=jtag430_coreid();
 555     txdata(app,verb,2);
 556     break;
 557   case JTAG430_DEVICE_ID:
 558     cmddatalong[0]=jtag430_deviceid();
 559     txdata(app,verb,4);
 560     break;
 561   default:
 562     (*(jtag_app.handle))(app,verb,len);
 563   }
 564   //jtag430_resettap();  //DO NOT UNCOMMENT
 565 }