1 /*! \file jtagarm7tdmi.h
2 \brief JTAG handler functions for the ARM7TDMI family of processors
8 #define JTAGSTATE_ARM 0 // bit 4 on dbg status reg is low
9 #define JTAGSTATE_THUMB 1
11 #define ARMTCKTOCK CLRTCK; PLEDOUT^=PLEDPIN; SETTCK; PLEDOUT^=PLEDPIN;
12 // ASSUME RUN-TEST/IDLE STATE
13 #define SHIFT_IR SETTMS;TCKTOCK;TCKTOCK;CLRTMS;TCKTOCK;TCKTOCK;
14 #define SHIFT_DR SETTMS;TCKTOCK;CLRTMS;TCKTOCK;TCKTOCK;
18 unsigned long registers[16]; // constant array
19 unsigned char current_chain;
20 unsigned char last_halt_debug_state = -1;
21 unsigned long last_halt_pc = -1;
22 unsigned long count_dbgspd_instr_since_debug = 0;
23 unsigned long count_sysspd_instr_since_debug = 0;
26 void jtag_goto_shift_ir();
27 void jtag_goto_shift_dr();
28 void jtag_reset_to_runtest_idle();
29 void jtag_arm_tcktock();
32 // JTAGARM7TDMI Commands
34 //! Write data to address.
35 unsigned long jtagarm7tdmi_writemem(unsigned long adr, unsigned long data);
36 //! Read data from address
37 unsigned long jtagarm7tdmi_readmem(unsigned long adr);
40 unsigned long jtagarm7tdmi_haltcpu();
42 unsigned long jtagarm7tdmi_releasecpu();
44 //! Set the program counter.
45 unsigned long jtagarm7tdmi_setpc(unsigned long adr);
47 //! Write data to address.
48 unsigned long jtagarm7tdmi_writeflash(unsigned long adr, unsigned long data);
52 unsigned long jtagarm7tdmi_start(void);
53 //! Reset TAP State Machine
54 void jtagarm7tdmi_resettap();
56 //! ARM-specific JTAG bit-transfer
57 unsigned long jtagarmtransn(unsigned long word, unsigned char bitcount, unsigned char lsb, unsigned char end, unsigned char retidle);
59 //! Grab debug register - Expect chain 2 to be selected
60 unsigned long jtagarm7tdmi_get_dbgstate() ;
62 unsigned long jtagarm7tdmi_idcode();
63 //! Connect Bypass Register to TDO/TDI
64 unsigned char jtagarm7tdmi_bypass();
65 //! Connect the appropriate scan chain to TDO/TDI
66 unsigned long jtagarm7tdmi_scan_intest(int n);
68 // ARM7TDMI-specific pins
69 // DBGRQ - GoodFET Pin 8
73 The instruction register is 4 bits in length.
74 There is no parity bit.
75 The fixed value 0001 is loaded into the instruction register during the CAPTURE-IR
77 The least significant bit of the instruction register is scanned in and scanned out first.
80 //4-bit ARM7TDMI JTAG commands, bit-swapped
81 #define ARM7TDMI_IR_EXTEST 0x0
82 #define ARM7TDMI_IR_SCAN_N 0x2
83 #define ARM7TDMI_IR_SAMPLE 0x3
84 #define ARM7TDMI_IR_RESTART 0x4
85 #define ARM7TDMI_IR_CLAMP 0x5
86 #define ARM7TDMI_IR_HIGHZ 0x7
87 #define ARM7TDMI_IR_CLAMPZ 0x9
88 #define ARM7TDMI_IR_INTEST 0xC
89 #define ARM7TDMI_IR_IDCODE 0xE
90 #define ARM7TDMI_IR_BYPASS 0xF
92 // read 3 bit - Debug Control
93 #define EICE_DBGCTRL 0
94 #define EICE_DBGCTRL_BITLEN 3
95 // read 5 bit - Debug Status
96 #define EICE_DBGSTATUS 1
97 #define EICE_DBGSTATUS_BITLEN 5
98 // read 6 bit - Debug Comms Control Register
100 #define EICE_DBGCCR_BITLEN 6
101 // r/w 32 bit - Debug Comms Data Register
102 #define EICE_DBGCDR 5
103 // r/w 32 bit - Watchpoint 0 Address
104 #define EICE_WP0ADDR 8
105 // r/w 32 bit - Watchpoint 0 Addres Mask
106 #define EICE_WP0ADDRMASK 9
107 // r/w 32 bit - Watchpoint 0 Data
108 #define EICE_WP0DATA 10
109 // r/w 32 bit - Watchpoint 0 Data Masl
110 #define EICE_WP0DATAMASK 11
111 // r/w 9 bit - Watchpoint 0 Control Value
112 #define EICE_WP0CTRL 12
113 // r/w 8 bit - Watchpoint 0 Control Mask
114 #define EICE_WP0CTRLMASK 13
115 // r/w 32 bit - Watchpoint 0 Address
116 #define EICE_WP1ADDR 16
117 // r/w 32 bit - Watchpoint 0 Addres Mask
118 #define EICE_WP1ADDRMASK 17
119 // r/w 32 bit - Watchpoint 0 Data
120 #define EICE_WP1DATA 18
121 // r/w 32 bit - Watchpoint 0 Data Masl
122 #define EICE_WP1DATAMASK 19
123 // r/w 9 bit - Watchpoint 0 Control Value
124 #define EICE_WP1CTRL 20
125 // r/w 8 bit - Watchpoint 0 Control Mask
126 #define EICE_WP1CTRLMASK 21
137 //JTAGARM7TDMI commands
138 #define JTAGARM7TDMI_GET_DEBUG_CTRL 0x80
139 #define JTAGARM7TDMI_SET_DEBUG_CTRL 0x81
140 #define JTAGARM7TDMI_GET_PC 0x82
141 #define JTAGARM7TDMI_SET_PC 0x83
142 #define JTAGARM7TDMI_GET_CHIP_ID 0x84
143 #define JTAGARM7TDMI_GET_DEBUG_STATE 0x85
144 #define JTAGARM7TDMI_GET_WATCHPOINT 0x86
145 #define JTAGARM7TDMI_SET_WATCHPOINT 0x87
146 #define JTAGARM7TDMI_GET_REGISTER 0x88
147 #define JTAGARM7TDMI_SET_REGISTER 0x89
148 #define JTAGARM7TDMI_GET_REGISTERS 0x8a
149 #define JTAGARM7TDMI_SET_REGISTERS 0x8b
150 #define JTAGARM7TDMI_HALTCPU 0x8c
151 #define JTAGARM7TDMI_RELEASECPU 0x8d
152 #define JTAGARM7TDMI_DEBUG_INSTR 0x8e
153 #define JTAGARM7TDMI_STEP_INSTR 0x8f
154 #define JTAGARM7TDMI_WRITEMEM 0x90
155 #define JTAGARM7TDMI_READMEM 0x91
156 #define JTAGARM7TDMI_WRITE_FLASH_PAGE 0x92
157 #define JTAGARM7TDMI_READ_FLASH_PAGE 0x93
158 #define JTAGARM7TDMI_MASS_ERASE_FLASH 0x94
159 #define JTAGARM7TDMI_PROGRAM_FLASH 0x95
160 #define JTAGARM7TDMI_LOCKCHIP 0x96
161 #define JTAGARM7TDMI_CHIP_ERASE 0x97
162 // Really ARM specific stuff
163 #define JTAGARM7TDMI_GET_CPSR 0x98
164 #define JTAGARM7TDMI_SET_CPSR 0x99
165 #define JTAGARM7TDMI_GET_SPSR 0x9a
166 #define JTAGARM7TDMI_SET_SPSR 0x9b
167 #define JTAGARM7TDMI_SET_MODE_THUMB 0x9c
168 #define JTAGARM7TDMI_SET_MODE_ARM 0x9d
171 // for deeper understanding, read the instruction cycle timing section of:
172 // http://www.atmel.com/dyn/resources/prod_documents/DDI0029G_7TDMI_R3_trm.pdf
173 #define EXECNOPARM 0xe1a00000
174 #define ARM_INSTR_NOP 0xe1a00000
175 #define ARM_INSTR_STR_Rx_r14 0xe58e0000
176 #define ARM_READ_REG ARM_INSTR_STR_Rx_r14
177 #define ARM_INSTR_LDR_Rx_r14 0xe59e0000
178 #define ARM_WRITE_REG ARM_INSTR_LDR_Rx_r14
179 #define ARM_INSTR_LDR_R1_r0_4 0xe4901004
180 #define ARM_READ_MEM ARM_INSTR_LDR_R1_r0_4
181 #define ARM_INSTR_MRS_R0_CPSR 0xf10f0000
182 #define ARM_INSTR_MSR_cpsr_cxsf_R0 0xe12ff000
183 #define ARM_INSTR_STM_R0_r0_r15 0x
184 #define ARM_INSTR_STMIA_R14_r0_rx 0xE88E0000 // add up to 65k to indicate which registers...
185 #define ARM_STORE_MULTIPLE ARM_INSTR_STMIA_R14_r0-rx
186 #define ARM_INSTR_SKANKREGS 0xE88Effff
187 #define ARM_INSTR_CLOBBEREGS 0xE88Effff
189 #define ARM_INSTR_B_PC 0xea000000
190 #define ARM_INSTR_BX_PC 0xe1200010 // need to set r0 to the desired address
191 #define THUMB_INSTR_STR_R0_r0 0x60006000
192 #define THUMB_INSTR_MOV_R0_PC 0x46b846b8
193 #define THUMB_INSTR_BX_PC 0x47784778
194 #define THUMB_INSTR_NOP 0x1c001c00
195 #define ARM_REG_PC 15
197 #define JTAG_ARM7TDMI_DBG_DBGACK 1
198 #define JTAG_ARM7TDMI_DBG_DBGRQ 2
199 #define JTAG_ARM7TDMI_DBG_IFEN 4
200 #define JTAG_ARM7TDMI_DBG_cgenL 8
201 #define JTAG_ARM7TDMI_DBG_TBIT 16