2 \author Travis Goodspeed
3 \brief MSP430-generic functions.
7 //Silently be empty if not an MSP430.
33 //! Initialize MSP430 registers and all that jazz.
35 WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer
42 /* P5.0 out and low; this is chosen for the PIC app (in which P5.0
43 is !MCLR) to ensure that an attached PIC chip, if present, is
44 immediately driven to reset state. A brief explanation of why this
47 At least dsPIC33F and PIC24H --and very likely other 16-bit PIC
48 families-- draw a large amount of current when running, especially
49 when using a fast clock: from 60 mA up to approx. 90 mA. If the
50 PIC target begins to run before the client can request a new ICSP
51 session, which requires much less current (e.g., less than 2 mA),
52 then the MSP430 chip on the GoodFET will fail to start and the FTDI
53 may have trouble communicating with the client. The latter likely
54 relates to the FTDI on-chip 3V3 regulator being specified up to
58 //P5REN &= ~BIT0; //DO NOT UNCOMMENT. Breaks GF1x support.
60 //This will have to be cut soon. Use pulling resistors instead.
66 //Setup clocks, unique to each '430.
70 //DAC should be at full voltage if it exists.
72 //glitchvoltages(0xfff,0xfff);
73 ADC12CTL0 = REF2_5V + REFON; // Internal 2.5V ref on
74 //for(i=0;i!=0xFFFF;i++) asm("nop"); //DO NOT UNCOMMENT, breaks GCC4
75 DAC12_0CTL = DAC12IR + DAC12AMP_5 + DAC12ENC; // Int ref gain 1
76 DAC12_0DAT = 0xFFF; //Max voltage 0xfff
77 DAC12_1CTL = DAC12IR + DAC12AMP_5 + DAC12ENC; // Int ref gain 1
78 DAC12_1DAT = 0x000; //Min voltage 0x000
83 This part is really ugly. GSEL (P5.7) must be high to select
84 normal voltage, but a lot of applications light to swing it low
85 to be a nuissance. To get around this, we assume that anyone
86 with a glitching FET will also have a DAC, then we set that DAC
89 At some point, each target must be sanitized to show that it
90 doesn't clear P5OUT or P5DIR.
92 P5DIR|=BIT7; P5OUT=BIT7; //Normal Supply
93 //P5DIR&=~BIT7; //Glitch Supply