1 //! MSP430F1612/1611 clock and I/O definitions
11 unsigned char serial_rx(){
14 while(!(IFG1&URXIFG0));//wait for a byte
23 unsigned char serial1_rx(){
26 while(!(IFG2&URXIFG1));//wait for a byte
36 void serial_tx(unsigned char x){
37 while ((IFG1 & UTXIFG0) == 0); //loop until buffer is free
41 //! Transmit a byte on the second UART.
42 void serial1_tx(unsigned char x){
43 while ((IFG2 & UTXIFG1) == 0); //loop until buffer is free
47 //! Set the baud rate.
48 void setbaud(unsigned char rate){
50 //http://mspgcc.sourceforge.net/baudrate.html
53 UBR00=0x7F; UBR10=0x01; UMCTL0=0x5B; /* uart0 3683400Hz 9599bps */
56 UBR00=0xBF; UBR10=0x00; UMCTL0=0xF7; /* uart0 3683400Hz 19194bps */
59 UBR00=0x5F; UBR10=0x00; UMCTL0=0xBF; /* uart0 3683400Hz 38408bps */
62 UBR00=0x40; UBR10=0x00; UMCTL0=0x00; /* uart0 3683400Hz 57553bps */
66 UBR00=0x20; UBR10=0x00; UMCTL0=0x00; /* uart0 3683400Hz 115106bps */
71 //! Set the baud rate of the second uart.
72 void setbaud1(unsigned char rate){
74 //http://mspgcc.sourceforge.net/baudrate.html
77 // UBR01=0x7F; UBR11=0x01; UMCTL1=0x5B; /* uart0 3683400Hz 9599bps */
80 //UBR01=0xBF; UBR11=0x00; UMCTL1=0xF7; /* uart0 3683400Hz 19194bps */
83 //UBR01=0x5F; UBR11=0x00; UMCTL1=0xBF; /* uart0 3683400Hz 38408bps */
86 //UBR01=0x40; UBR11=0x00; UMCTL1=0x00; /* uart0 3683400Hz 57553bps */
90 //UBR01=0x20; UBR11=0x00; UMCTL1=0x00; /* uart0 3683400Hz 115106bps */
96 void msp430_init_uart(){
100 P3SEL |= BIT4|BIT5; // P3.4,5 = USART0 TXD/RXD
103 UCTL0 = SWRST | CHAR; /* 8-bit character, UART mode */
104 UTCTL0 = SSEL1; /* UCLK = MCLK */
108 ME1 &= ~USPIE0; /* USART1 SPI module disable */
109 ME1 |= (UTXE0 | URXE0); /* Enable USART1 TXD/RXD */
113 /* XXX Clear pending interrupts before enable!!! */
117 //IE1 |= URXIE1; /* Enable USART1 RX interrupt */
121 void msp430_init_dco() {
122 /* This code taken from the FU Berlin sources and reformatted. */
126 //#define MSP430_CPU_SPEED 2457600UL
128 //Too fast for internal resistor.
129 //#define MSP430_CPU_SPEED 4915200UL
132 //#deefine MSP430_CPU_SPEED 4500000UL
135 #define MSP430_CPU_SPEED 3683400UL
136 #define DELTA ((MSP430_CPU_SPEED) / (32768 / 8))
137 unsigned int compare, oldcapture = 0;
140 WDTCTL = WDTPW + WDTHOLD; //stop WDT
147 /* ACLK is devided by 4. RSEL=6 no division for MCLK
148 and SSMCLK. XT2 is off. */
151 BCSCTL2 = 0x00; /* Init FLL to desired frequency using the 32762Hz
152 crystal DCO frquenzy = 2,4576 MHz */
156 BCSCTL1 |= DIVA1 + DIVA0; /* ACLK = LFXT1CLK/8 */
157 for(i = 0xffff; i > 0; i--) { /* Delay for XTAL to settle */
161 CCTL2 = CCIS0 + CM0 + CAP; // Define CCR2, CAP, ACLK
162 TACTL = TASSEL1 + TACLR + MC1; // SMCLK, continous mode
167 while((CCTL2 & CCIFG) != CCIFG); /* Wait until capture occured! */
168 CCTL2 &= ~CCIFG; /* Capture occured, clear flag */
169 compare = CCR2; /* Get current captured SMCLK */
170 compare = compare - oldcapture; /* SMCLK difference */
171 oldcapture = CCR2; /* Save current captured SMCLK */
173 if(DELTA == compare) {
174 break; /* if equal, leave "while(1)" */
175 } else if(DELTA < compare) { /* DCO is too fast, slow it down */
177 if(DCOCTL == 0xFF) { /* Did DCO role under? */
180 } else { /* -> Select next lower RSEL */
182 if(DCOCTL == 0x00) { /* Did DCO role over? */
185 /* -> Select next higher RSEL */
189 CCTL2 = 0; /* Stop CCR2 function */
190 TACTL = 0; /* Stop Timer_A */
192 BCSCTL1 &= ~(DIVA1 + DIVA0); /* remove /8 divisor from ACLK again */