include/asm-ia64/pal.h

   1 #ifndef _ASM_IA64_PAL_H
   2 #define _ASM_IA64_PAL_H
   3
   4 /*
   5  * Processor Abstraction Layer definitions.
   6  *
   7  * This is based on Intel IA-64 Architecture Software Developer's Manual rev 1.0
   8  * chapter 11 IA-64 Processor Abstraction Layer
   9  *
  10  * Copyright (C) 1998-2001 Hewlett-Packard Co
  11  *      David Mosberger-Tang <davidm@hpl.hp.com>
  12  *      Stephane Eranian <eranian@hpl.hp.com>
  13  * Copyright (C) 1999 VA Linux Systems
  14  * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
  15  * Copyright (C) 1999 Srinivasa Prasad Thirumalachar <sprasad@sprasad.engr.sgi.com>
  16  *
  17  * 99/10/01     davidm  Make sure we pass zero for reserved parameters.
  18  * 00/03/07     davidm  Updated pal_cache_flush() to be in sync with PAL v2.6.
  19  * 00/03/23     cfleck  Modified processor min-state save area to match updated PAL & SAL info
  20  * 00/05/24     eranian Updated to latest PAL spec, fix structures bugs, added
  21  * 00/05/25     eranian Support for stack calls, and static physical calls
  22  * 00/06/18     eranian Support for stacked physical calls
  23  * 06/10/26     rja     Support for Intel Itanium Architecture Software Developer's
  24  *                      Manual Rev 2.2 (Jan 2006)
  25  */
  26
  27 /*
  28  * Note that some of these calls use a static-register only calling
  29  * convention which has nothing to do with the regular calling
  30  * convention.
  31  */
  32 #define PAL_CACHE_FLUSH         1       /* flush i/d cache */
  33 #define PAL_CACHE_INFO          2       /* get detailed i/d cache info */
  34 #define PAL_CACHE_INIT          3       /* initialize i/d cache */
  35 #define PAL_CACHE_SUMMARY       4       /* get summary of cache heirarchy */
  36 #define PAL_MEM_ATTRIB          5       /* list supported memory attributes */
  37 #define PAL_PTCE_INFO           6       /* purge TLB info */
  38 #define PAL_VM_INFO             7       /* return supported virtual memory features */
  39 #define PAL_VM_SUMMARY          8       /* return summary on supported vm features */
  40 #define PAL_BUS_GET_FEATURES    9       /* return processor bus interface features settings */
  41 #define PAL_BUS_SET_FEATURES    10      /* set processor bus features */
  42 #define PAL_DEBUG_INFO          11      /* get number of debug registers */
  43 #define PAL_FIXED_ADDR          12      /* get fixed component of processors's directed address */
  44 #define PAL_FREQ_BASE           13      /* base frequency of the platform */
  45 #define PAL_FREQ_RATIOS         14      /* ratio of processor, bus and ITC frequency */
  46 #define PAL_PERF_MON_INFO       15      /* return performance monitor info */
  47 #define PAL_PLATFORM_ADDR       16      /* set processor interrupt block and IO port space addr */
  48 #define PAL_PROC_GET_FEATURES   17      /* get configurable processor features & settings */
  49 #define PAL_PROC_SET_FEATURES   18      /* enable/disable configurable processor features */
  50 #define PAL_RSE_INFO            19      /* return rse information */
  51 #define PAL_VERSION             20      /* return version of PAL code */
  52 #define PAL_MC_CLEAR_LOG        21      /* clear all processor log info */
  53 #define PAL_MC_DRAIN            22      /* drain operations which could result in an MCA */
  54 #define PAL_MC_EXPECTED         23      /* set/reset expected MCA indicator */
  55 #define PAL_MC_DYNAMIC_STATE    24      /* get processor dynamic state */
  56 #define PAL_MC_ERROR_INFO       25      /* get processor MCA info and static state */
  57 #define PAL_MC_RESUME           26      /* Return to interrupted process */
  58 #define PAL_MC_REGISTER_MEM     27      /* Register memory for PAL to use during MCAs and inits */
  59 #define PAL_HALT                28      /* enter the low power HALT state */
  60 #define PAL_HALT_LIGHT          29      /* enter the low power light halt state*/
  61 #define PAL_COPY_INFO           30      /* returns info needed to relocate PAL */
  62 #define PAL_CACHE_LINE_INIT     31      /* init tags & data of cache line */
  63 #define PAL_PMI_ENTRYPOINT      32      /* register PMI memory entry points with the processor */
  64 #define PAL_ENTER_IA_32_ENV     33      /* enter IA-32 system environment */
  65 #define PAL_VM_PAGE_SIZE        34      /* return vm TC and page walker page sizes */
  66
  67 #define PAL_MEM_FOR_TEST        37      /* get amount of memory needed for late processor test */
  68 #define PAL_CACHE_PROT_INFO     38      /* get i/d cache protection info */
  69 #define PAL_REGISTER_INFO       39      /* return AR and CR register information*/
  70 #define PAL_SHUTDOWN            40      /* enter processor shutdown state */
  71 #define PAL_PREFETCH_VISIBILITY 41      /* Make Processor Prefetches Visible */
  72 #define PAL_LOGICAL_TO_PHYSICAL 42      /* returns information on logical to physical processor mapping */
  73 #define PAL_CACHE_SHARED_INFO   43      /* returns information on caches shared by logical processor */
  74 #define PAL_GET_HW_POLICY       48      /* Get current hardware resource sharing policy */
  75 #define PAL_SET_HW_POLICY       49      /* Set current hardware resource sharing policy */
  76
  77 #define PAL_COPY_PAL            256     /* relocate PAL procedures and PAL PMI */
  78 #define PAL_HALT_INFO           257     /* return the low power capabilities of processor */
  79 #define PAL_TEST_PROC           258     /* perform late processor self-test */
  80 #define PAL_CACHE_READ          259     /* read tag & data of cacheline for diagnostic testing */
  81 #define PAL_CACHE_WRITE         260     /* write tag & data of cacheline for diagnostic testing */
  82 #define PAL_VM_TR_READ          261     /* read contents of translation register */
  83 #define PAL_GET_PSTATE          262     /* get the current P-state */
  84 #define PAL_SET_PSTATE          263     /* set the P-state */
  85 #define PAL_BRAND_INFO          274     /* Processor branding information */
  86
  87 #ifndef __ASSEMBLY__
  88
  89 #include <linux/types.h>
  90 #include <asm/fpu.h>
  91
  92 /*
  93  * Data types needed to pass information into PAL procedures and
  94  * interpret information returned by them.
  95  */
  96
  97 /* Return status from the PAL procedure */
  98 typedef s64                             pal_status_t;
  99
 100 #define PAL_STATUS_SUCCESS              0       /* No error */
 101 #define PAL_STATUS_UNIMPLEMENTED        (-1)    /* Unimplemented procedure */
 102 #define PAL_STATUS_EINVAL               (-2)    /* Invalid argument */
 103 #define PAL_STATUS_ERROR                (-3)    /* Error */
 104 #define PAL_STATUS_CACHE_INIT_FAIL      (-4)    /* Could not initialize the
 105                                                  * specified level and type of
 106                                                  * cache without sideeffects
 107                                                  * and "restrict" was 1
 108                                                  */
 109 #define PAL_STATUS_REQUIRES_MEMORY      (-9)    /* Call requires PAL memory buffer */
 110
 111 /* Processor cache level in the heirarchy */
 112 typedef u64                             pal_cache_level_t;
 113 #define PAL_CACHE_LEVEL_L0              0       /* L0 */
 114 #define PAL_CACHE_LEVEL_L1              1       /* L1 */
 115 #define PAL_CACHE_LEVEL_L2              2       /* L2 */
 116
 117
 118 /* Processor cache type at a particular level in the heirarchy */
 119
 120 typedef u64                             pal_cache_type_t;
 121 #define PAL_CACHE_TYPE_INSTRUCTION      1       /* Instruction cache */
 122 #define PAL_CACHE_TYPE_DATA             2       /* Data or unified cache */
 123 #define PAL_CACHE_TYPE_INSTRUCTION_DATA 3       /* Both Data & Instruction */
 124
 125
 126 #define PAL_CACHE_FLUSH_INVALIDATE      1       /* Invalidate clean lines */
 127 #define PAL_CACHE_FLUSH_CHK_INTRS       2       /* check for interrupts/mc while flushing */
 128
 129 /* Processor cache line size in bytes  */
 130 typedef int                             pal_cache_line_size_t;
 131
 132 /* Processor cache line state */
 133 typedef u64                             pal_cache_line_state_t;
 134 #define PAL_CACHE_LINE_STATE_INVALID    0       /* Invalid */
 135 #define PAL_CACHE_LINE_STATE_SHARED     1       /* Shared */
 136 #define PAL_CACHE_LINE_STATE_EXCLUSIVE  2       /* Exclusive */
 137 #define PAL_CACHE_LINE_STATE_MODIFIED   3       /* Modified */
 138
 139 typedef struct pal_freq_ratio {
 140         u32 den, num;           /* numerator & denominator */
 141 } itc_ratio, proc_ratio;
 142
 143 typedef union  pal_cache_config_info_1_s {
 144         struct {
 145                 u64             u               : 1,    /* 0 Unified cache ? */
 146                                 at              : 2,    /* 2-1 Cache mem attr*/
 147                                 reserved        : 5,    /* 7-3 Reserved */
 148                                 associativity   : 8,    /* 16-8 Associativity*/
 149                                 line_size       : 8,    /* 23-17 Line size */
 150                                 stride          : 8,    /* 31-24 Stride */
 151                                 store_latency   : 8,    /*39-32 Store latency*/
 152                                 load_latency    : 8,    /* 47-40 Load latency*/
 153                                 store_hints     : 8,    /* 55-48 Store hints*/
 154                                 load_hints      : 8;    /* 63-56 Load hints */
 155         } pcci1_bits;
 156         u64                     pcci1_data;
 157 } pal_cache_config_info_1_t;
 158
 159 typedef union  pal_cache_config_info_2_s {
 160         struct {
 161                 u32             cache_size;             /*cache size in bytes*/
 162
 163
 164                 u32             alias_boundary  : 8,    /* 39-32 aliased addr
 165                                                          * separation for max
 166                                                          * performance.
 167                                                          */
 168                                 tag_ls_bit      : 8,    /* 47-40 LSb of addr*/
 169                                 tag_ms_bit      : 8,    /* 55-48 MSb of addr*/
 170                                 reserved        : 8;    /* 63-56 Reserved */
 171         } pcci2_bits;
 172         u64                     pcci2_data;
 173 } pal_cache_config_info_2_t;
 174
 175
 176 typedef struct pal_cache_config_info_s {
 177         pal_status_t                    pcci_status;
 178         pal_cache_config_info_1_t       pcci_info_1;
 179         pal_cache_config_info_2_t       pcci_info_2;
 180         u64                             pcci_reserved;
 181 } pal_cache_config_info_t;
 182
 183 #define pcci_ld_hints           pcci_info_1.pcci1_bits.load_hints
 184 #define pcci_st_hints           pcci_info_1.pcci1_bits.store_hints
 185 #define pcci_ld_latency         pcci_info_1.pcci1_bits.load_latency
 186 #define pcci_st_latency         pcci_info_1.pcci1_bits.store_latency
 187 #define pcci_stride             pcci_info_1.pcci1_bits.stride
 188 #define pcci_line_size          pcci_info_1.pcci1_bits.line_size
 189 #define pcci_assoc              pcci_info_1.pcci1_bits.associativity
 190 #define pcci_cache_attr         pcci_info_1.pcci1_bits.at
 191 #define pcci_unified            pcci_info_1.pcci1_bits.u
 192 #define pcci_tag_msb            pcci_info_2.pcci2_bits.tag_ms_bit
 193 #define pcci_tag_lsb            pcci_info_2.pcci2_bits.tag_ls_bit
 194 #define pcci_alias_boundary     pcci_info_2.pcci2_bits.alias_boundary
 195 #define pcci_cache_size         pcci_info_2.pcci2_bits.cache_size
 196
 197
 198
 199 /* Possible values for cache attributes */
 200
 201 #define PAL_CACHE_ATTR_WT               0       /* Write through cache */
 202 #define PAL_CACHE_ATTR_WB               1       /* Write back cache */
 203 #define PAL_CACHE_ATTR_WT_OR_WB         2       /* Either write thru or write
 204                                                  * back depending on TLB
 205                                                  * memory attributes
 206                                                  */
 207
 208
 209 /* Possible values for cache hints */
 210
 211 #define PAL_CACHE_HINT_TEMP_1           0       /* Temporal level 1 */
 212 #define PAL_CACHE_HINT_NTEMP_1          1       /* Non-temporal level 1 */
 213 #define PAL_CACHE_HINT_NTEMP_ALL        3       /* Non-temporal all levels */
 214
 215 /* Processor cache protection  information */
 216 typedef union pal_cache_protection_element_u {
 217         u32                     pcpi_data;
 218         struct {
 219                 u32             data_bits       : 8, /* # data bits covered by
 220                                                       * each unit of protection
 221                                                       */
 222
 223                                 tagprot_lsb     : 6, /* Least -do- */
 224                                 tagprot_msb     : 6, /* Most Sig. tag address
 225                                                       * bit that this
 226                                                       * protection covers.
 227                                                       */
 228                                 prot_bits       : 6, /* # of protection bits */
 229                                 method          : 4, /* Protection method */
 230                                 t_d             : 2; /* Indicates which part
 231                                                       * of the cache this
 232                                                       * protection encoding
 233                                                       * applies.
 234                                                       */
 235         } pcp_info;
 236 } pal_cache_protection_element_t;
 237
 238 #define pcpi_cache_prot_part    pcp_info.t_d
 239 #define pcpi_prot_method        pcp_info.method
 240 #define pcpi_prot_bits          pcp_info.prot_bits
 241 #define pcpi_tagprot_msb        pcp_info.tagprot_msb
 242 #define pcpi_tagprot_lsb        pcp_info.tagprot_lsb
 243 #define pcpi_data_bits          pcp_info.data_bits
 244
 245 /* Processor cache part encodings */
 246 #define PAL_CACHE_PROT_PART_DATA        0       /* Data protection  */
 247 #define PAL_CACHE_PROT_PART_TAG         1       /* Tag  protection */
 248 #define PAL_CACHE_PROT_PART_TAG_DATA    2       /* Tag+data protection (tag is
 249                                                  * more significant )
 250                                                  */
 251 #define PAL_CACHE_PROT_PART_DATA_TAG    3       /* Data+tag protection (data is
 252                                                  * more significant )
 253                                                  */
 254 #define PAL_CACHE_PROT_PART_MAX         6
 255
 256
 257 typedef struct pal_cache_protection_info_s {
 258         pal_status_t                    pcpi_status;
 259         pal_cache_protection_element_t  pcp_info[PAL_CACHE_PROT_PART_MAX];
 260 } pal_cache_protection_info_t;
 261
 262
 263 /* Processor cache protection method encodings */
 264 #define PAL_CACHE_PROT_METHOD_NONE              0       /* No protection */
 265 #define PAL_CACHE_PROT_METHOD_ODD_PARITY        1       /* Odd parity */
 266 #define PAL_CACHE_PROT_METHOD_EVEN_PARITY       2       /* Even parity */
 267 #define PAL_CACHE_PROT_METHOD_ECC               3       /* ECC protection */
 268
 269
 270 /* Processor cache line identification in the heirarchy */
 271 typedef union pal_cache_line_id_u {
 272         u64                     pclid_data;
 273         struct {
 274                 u64             cache_type      : 8,    /* 7-0 cache type */
 275                                 level           : 8,    /* 15-8 level of the
 276                                                          * cache in the
 277                                                          * heirarchy.
 278                                                          */
 279                                 way             : 8,    /* 23-16 way in the set
 280                                                          */
 281                                 part            : 8,    /* 31-24 part of the
 282                                                          * cache
 283                                                          */
 284                                 reserved        : 32;   /* 63-32 is reserved*/
 285         } pclid_info_read;
 286         struct {
 287                 u64             cache_type      : 8,    /* 7-0 cache type */
 288                                 level           : 8,    /* 15-8 level of the
 289                                                          * cache in the
 290                                                          * heirarchy.
 291                                                          */
 292                                 way             : 8,    /* 23-16 way in the set
 293                                                          */
 294                                 part            : 8,    /* 31-24 part of the
 295                                                          * cache
 296                                                          */
 297                                 mesi            : 8,    /* 39-32 cache line
 298                                                          * state
 299                                                          */
 300                                 start           : 8,    /* 47-40 lsb of data to
 301                                                          * invert
 302                                                          */
 303                                 length          : 8,    /* 55-48 #bits to
 304                                                          * invert
 305                                                          */
 306                                 trigger         : 8;    /* 63-56 Trigger error
 307                                                          * by doing a load
 308                                                          * after the write
 309                                                          */
 310
 311         } pclid_info_write;
 312 } pal_cache_line_id_u_t;
 313
 314 #define pclid_read_part         pclid_info_read.part
 315 #define pclid_read_way          pclid_info_read.way
 316 #define pclid_read_level        pclid_info_read.level
 317 #define pclid_read_cache_type   pclid_info_read.cache_type
 318
 319 #define pclid_write_trigger     pclid_info_write.trigger
 320 #define pclid_write_length      pclid_info_write.length
 321 #define pclid_write_start       pclid_info_write.start
 322 #define pclid_write_mesi        pclid_info_write.mesi
 323 #define pclid_write_part        pclid_info_write.part
 324 #define pclid_write_way         pclid_info_write.way
 325 #define pclid_write_level       pclid_info_write.level
 326 #define pclid_write_cache_type  pclid_info_write.cache_type
 327
 328 /* Processor cache line part encodings */
 329 #define PAL_CACHE_LINE_ID_PART_DATA             0       /* Data */
 330 #define PAL_CACHE_LINE_ID_PART_TAG              1       /* Tag */
 331 #define PAL_CACHE_LINE_ID_PART_DATA_PROT        2       /* Data protection */
 332 #define PAL_CACHE_LINE_ID_PART_TAG_PROT         3       /* Tag protection */
 333 #define PAL_CACHE_LINE_ID_PART_DATA_TAG_PROT    4       /* Data+tag
 334                                                          * protection
 335                                                          */
 336 typedef struct pal_cache_line_info_s {
 337         pal_status_t            pcli_status;            /* Return status of the read cache line
 338                                                          * info call.
 339                                                          */
 340         u64                     pcli_data;              /* 64-bit data, tag, protection bits .. */
 341         u64                     pcli_data_len;          /* data length in bits */
 342         pal_cache_line_state_t  pcli_cache_line_state;  /* mesi state */
 343
 344 } pal_cache_line_info_t;
 345
 346
 347 /* Machine Check related crap */
 348
 349 /* Pending event status bits  */
 350 typedef u64                                     pal_mc_pending_events_t;
 351
 352 #define PAL_MC_PENDING_MCA                      (1 << 0)
 353 #define PAL_MC_PENDING_INIT                     (1 << 1)
 354
 355 /* Error information type */
 356 typedef u64                                     pal_mc_info_index_t;
 357
 358 #define PAL_MC_INFO_PROCESSOR                   0       /* Processor */
 359 #define PAL_MC_INFO_CACHE_CHECK                 1       /* Cache check */
 360 #define PAL_MC_INFO_TLB_CHECK                   2       /* Tlb check */
 361 #define PAL_MC_INFO_BUS_CHECK                   3       /* Bus check */
 362 #define PAL_MC_INFO_REQ_ADDR                    4       /* Requestor address */
 363 #define PAL_MC_INFO_RESP_ADDR                   5       /* Responder address */
 364 #define PAL_MC_INFO_TARGET_ADDR                 6       /* Target address */
 365 #define PAL_MC_INFO_IMPL_DEP                    7       /* Implementation
 366                                                          * dependent
 367                                                          */
 368
 369
 370 typedef struct pal_process_state_info_s {
 371         u64             reserved1       : 2,
 372                         rz              : 1,    /* PAL_CHECK processor
 373                                                  * rendezvous
 374                                                  * successful.
 375                                                  */
 376
 377                         ra              : 1,    /* PAL_CHECK attempted
 378                                                  * a rendezvous.
 379                                                  */
 380                         me              : 1,    /* Distinct multiple
 381                                                  * errors occurred
 382                                                  */
 383
 384                         mn              : 1,    /* Min. state save
 385                                                  * area has been
 386                                                  * registered with PAL
 387                                                  */
 388
 389                         sy              : 1,    /* Storage integrity
 390                                                  * synched
 391                                                  */
 392
 393
 394                         co              : 1,    /* Continuable */
 395                         ci              : 1,    /* MC isolated */
 396                         us              : 1,    /* Uncontained storage
 397                                                  * damage.
 398                                                  */
 399
 400
 401                         hd              : 1,    /* Non-essential hw
 402                                                  * lost (no loss of
 403                                                  * functionality)
 404                                                  * causing the
 405                                                  * processor to run in
 406                                                  * degraded mode.
 407                                                  */
 408
 409                         tl              : 1,    /* 1 => MC occurred
 410                                                  * after an instr was
 411                                                  * executed but before
 412                                                  * the trap that
 413                                                  * resulted from instr
 414                                                  * execution was
 415                                                  * generated.
 416                                                  * (Trap Lost )
 417                                                  */
 418                         mi              : 1,    /* More information available
 419                                                  * call PAL_MC_ERROR_INFO
 420                                                  */
 421                         pi              : 1,    /* Precise instruction pointer */
 422                         pm              : 1,    /* Precise min-state save area */
 423
 424                         dy              : 1,    /* Processor dynamic
 425                                                  * state valid
 426                                                  */
 427
 428
 429                         in              : 1,    /* 0 = MC, 1 = INIT */
 430                         rs              : 1,    /* RSE valid */
 431                         cm              : 1,    /* MC corrected */
 432                         ex              : 1,    /* MC is expected */
 433                         cr              : 1,    /* Control regs valid*/
 434                         pc              : 1,    /* Perf cntrs valid */
 435                         dr              : 1,    /* Debug regs valid */
 436                         tr              : 1,    /* Translation regs
 437                                                  * valid
 438                                                  */
 439                         rr              : 1,    /* Region regs valid */
 440                         ar              : 1,    /* App regs valid */
 441                         br              : 1,    /* Branch regs valid */
 442                         pr              : 1,    /* Predicate registers
 443                                                  * valid
 444                                                  */
 445
 446                         fp              : 1,    /* fp registers valid*/
 447                         b1              : 1,    /* Preserved bank one
 448                                                  * general registers
 449                                                  * are valid
 450                                                  */
 451                         b0              : 1,    /* Preserved bank zero
 452                                                  * general registers
 453                                                  * are valid
 454                                                  */
 455                         gr              : 1,    /* General registers
 456                                                  * are valid
 457                                                  * (excl. banked regs)
 458                                                  */
 459                         dsize           : 16,   /* size of dynamic
 460                                                  * state returned
 461                                                  * by the processor
 462                                                  */
 463
 464                         se              : 1,    /* Shared error.  MCA in a
 465                                                    shared structure */
 466                         reserved2       : 10,
 467                         cc              : 1,    /* Cache check */
 468                         tc              : 1,    /* TLB check */
 469                         bc              : 1,    /* Bus check */
 470                         rc              : 1,    /* Register file check */
 471                         uc              : 1;    /* Uarch check */
 472
 473 } pal_processor_state_info_t;
 474
 475 typedef struct pal_cache_check_info_s {
 476         u64             op              : 4,    /* Type of cache
 477                                                  * operation that
 478                                                  * caused the machine
 479                                                  * check.
 480                                                  */
 481                         level           : 2,    /* Cache level */
 482                         reserved1       : 2,
 483                         dl              : 1,    /* Failure in data part
 484                                                  * of cache line
 485                                                  */
 486                         tl              : 1,    /* Failure in tag part
 487                                                  * of cache line
 488                                                  */
 489                         dc              : 1,    /* Failure in dcache */
 490                         ic              : 1,    /* Failure in icache */
 491                         mesi            : 3,    /* Cache line state */
 492                         mv              : 1,    /* mesi valid */
 493                         way             : 5,    /* Way in which the
 494                                                  * error occurred
 495                                                  */
 496                         wiv             : 1,    /* Way field valid */
 497                         reserved2       : 1,
 498                         dp              : 1,    /* Data poisoned on MBE */
 499                         reserved3       : 8,
 500
 501                         index           : 20,   /* Cache line index */
 502                         reserved4       : 2,
 503
 504                         is              : 1,    /* instruction set (1 == ia32) */
 505                         iv              : 1,    /* instruction set field valid */
 506                         pl              : 2,    /* privilege level */
 507                         pv              : 1,    /* privilege level field valid */
 508                         mcc             : 1,    /* Machine check corrected */
 509                         tv              : 1,    /* Target address
 510                                                  * structure is valid
 511                                                  */
 512                         rq              : 1,    /* Requester identifier
 513                                                  * structure is valid
 514                                                  */
 515                         rp              : 1,    /* Responder identifier
 516                                                  * structure is valid
 517                                                  */
 518                         pi              : 1;    /* Precise instruction pointer
 519                                                  * structure is valid
 520                                                  */
 521 } pal_cache_check_info_t;
 522
 523 typedef struct pal_tlb_check_info_s {
 524
 525         u64             tr_slot         : 8,    /* Slot# of TR where
 526                                                  * error occurred
 527                                                  */
 528                         trv             : 1,    /* tr_slot field is valid */
 529                         reserved1       : 1,
 530                         level           : 2,    /* TLB level where failure occurred */
 531                         reserved2       : 4,
 532                         dtr             : 1,    /* Fail in data TR */
 533                         itr             : 1,    /* Fail in inst TR */
 534                         dtc             : 1,    /* Fail in data TC */
 535                         itc             : 1,    /* Fail in inst. TC */
 536                         op              : 4,    /* Cache operation */
 537                         reserved3       : 30,
 538
 539                         is              : 1,    /* instruction set (1 == ia32) */
 540                         iv              : 1,    /* instruction set field valid */
 541                         pl              : 2,    /* privilege level */
 542                         pv              : 1,    /* privilege level field valid */
 543                         mcc             : 1,    /* Machine check corrected */
 544                         tv              : 1,    /* Target address
 545                                                  * structure is valid
 546                                                  */
 547                         rq              : 1,    /* Requester identifier
 548                                                  * structure is valid
 549                                                  */
 550                         rp              : 1,    /* Responder identifier
 551                                                  * structure is valid
 552                                                  */
 553                         pi              : 1;    /* Precise instruction pointer
 554                                                  * structure is valid
 555                                                  */
 556 } pal_tlb_check_info_t;
 557
 558 typedef struct pal_bus_check_info_s {
 559         u64             size            : 5,    /* Xaction size */
 560                         ib              : 1,    /* Internal bus error */
 561                         eb              : 1,    /* External bus error */
 562                         cc              : 1,    /* Error occurred
 563                                                  * during cache-cache
 564                                                  * transfer.
 565                                                  */
 566                         type            : 8,    /* Bus xaction type*/
 567                         sev             : 5,    /* Bus error severity*/
 568                         hier            : 2,    /* Bus hierarchy level */
 569                         dp              : 1,    /* Data poisoned on MBE */
 570                         bsi             : 8,    /* Bus error status
 571                                                  * info
 572                                                  */
 573                         reserved2       : 22,
 574
 575                         is              : 1,    /* instruction set (1 == ia32) */
 576                         iv              : 1,    /* instruction set field valid */
 577                         pl              : 2,    /* privilege level */
 578                         pv              : 1,    /* privilege level field valid */
 579                         mcc             : 1,    /* Machine check corrected */
 580                         tv              : 1,    /* Target address
 581                                                  * structure is valid
 582                                                  */
 583                         rq              : 1,    /* Requester identifier
 584                                                  * structure is valid
 585                                                  */
 586                         rp              : 1,    /* Responder identifier
 587                                                  * structure is valid
 588                                                  */
 589                         pi              : 1;    /* Precise instruction pointer
 590                                                  * structure is valid
 591                                                  */
 592 } pal_bus_check_info_t;
 593
 594 typedef struct pal_reg_file_check_info_s {
 595         u64             id              : 4,    /* Register file identifier */
 596                         op              : 4,    /* Type of register
 597                                                  * operation that
 598                                                  * caused the machine
 599                                                  * check.
 600                                                  */
 601                         reg_num         : 7,    /* Register number */
 602                         rnv             : 1,    /* reg_num valid */
 603                         reserved2       : 38,
 604
 605                         is              : 1,    /* instruction set (1 == ia32) */
 606                         iv              : 1,    /* instruction set field valid */
 607                         pl              : 2,    /* privilege level */
 608                         pv              : 1,    /* privilege level field valid */
 609                         mcc             : 1,    /* Machine check corrected */
 610                         reserved3       : 3,
 611                         pi              : 1;    /* Precise instruction pointer
 612                                                  * structure is valid
 613                                                  */
 614 } pal_reg_file_check_info_t;
 615
 616 typedef struct pal_uarch_check_info_s {
 617         u64             sid             : 5,    /* Structure identification */
 618                         level           : 3,    /* Level of failure */
 619                         array_id        : 4,    /* Array identification */
 620                         op              : 4,    /* Type of
 621                                                  * operation that
 622                                                  * caused the machine
 623                                                  * check.
 624                                                  */
 625                         way             : 6,    /* Way of structure */
 626                         wv              : 1,    /* way valid */
 627                         xv              : 1,    /* index valid */
 628                         reserved1       : 8,
 629                         index           : 8,    /* Index or set of the uarch
 630                                                  * structure that failed.
 631                                                  */
 632                         reserved2       : 24,
 633
 634                         is              : 1,    /* instruction set (1 == ia32) */
 635                         iv              : 1,    /* instruction set field valid */
 636                         pl              : 2,    /* privilege level */
 637                         pv              : 1,    /* privilege level field valid */
 638                         mcc             : 1,    /* Machine check corrected */
 639                         tv              : 1,    /* Target address
 640                                                  * structure is valid
 641                                                  */
 642                         rq              : 1,    /* Requester identifier
 643                                                  * structure is valid
 644                                                  */
 645                         rp              : 1,    /* Responder identifier
 646                                                  * structure is valid
 647                                                  */
 648                         pi              : 1;    /* Precise instruction pointer
 649                                                  * structure is valid
 650                                                  */
 651 } pal_uarch_check_info_t;
 652
 653 typedef union pal_mc_error_info_u {
 654         u64                             pmei_data;
 655         pal_processor_state_info_t      pme_processor;
 656         pal_cache_check_info_t          pme_cache;
 657         pal_tlb_check_info_t            pme_tlb;
 658         pal_bus_check_info_t            pme_bus;
 659         pal_reg_file_check_info_t       pme_reg_file;
 660         pal_uarch_check_info_t          pme_uarch;
 661 } pal_mc_error_info_t;
 662
 663 #define pmci_proc_unknown_check                 pme_processor.uc
 664 #define pmci_proc_bus_check                     pme_processor.bc
 665 #define pmci_proc_tlb_check                     pme_processor.tc
 666 #define pmci_proc_cache_check                   pme_processor.cc
 667 #define pmci_proc_dynamic_state_size            pme_processor.dsize
 668 #define pmci_proc_gpr_valid                     pme_processor.gr
 669 #define pmci_proc_preserved_bank0_gpr_valid     pme_processor.b0
 670 #define pmci_proc_preserved_bank1_gpr_valid     pme_processor.b1
 671 #define pmci_proc_fp_valid                      pme_processor.fp
 672 #define pmci_proc_predicate_regs_valid          pme_processor.pr
 673 #define pmci_proc_branch_regs_valid             pme_processor.br
 674 #define pmci_proc_app_regs_valid                pme_processor.ar
 675 #define pmci_proc_region_regs_valid             pme_processor.rr
 676 #define pmci_proc_translation_regs_valid        pme_processor.tr
 677 #define pmci_proc_debug_regs_valid              pme_processor.dr
 678 #define pmci_proc_perf_counters_valid           pme_processor.pc
 679 #define pmci_proc_control_regs_valid            pme_processor.cr
 680 #define pmci_proc_machine_check_expected        pme_processor.ex
 681 #define pmci_proc_machine_check_corrected       pme_processor.cm
 682 #define pmci_proc_rse_valid                     pme_processor.rs
 683 #define pmci_proc_machine_check_or_init         pme_processor.in
 684 #define pmci_proc_dynamic_state_valid           pme_processor.dy
 685 #define pmci_proc_operation                     pme_processor.op
 686 #define pmci_proc_trap_lost                     pme_processor.tl
 687 #define pmci_proc_hardware_damage               pme_processor.hd
 688 #define pmci_proc_uncontained_storage_damage    pme_processor.us
 689 #define pmci_proc_machine_check_isolated        pme_processor.ci
 690 #define pmci_proc_continuable                   pme_processor.co
 691 #define pmci_proc_storage_intergrity_synced     pme_processor.sy
 692 #define pmci_proc_min_state_save_area_regd      pme_processor.mn
 693 #define pmci_proc_distinct_multiple_errors      pme_processor.me
 694 #define pmci_proc_pal_attempted_rendezvous      pme_processor.ra
 695 #define pmci_proc_pal_rendezvous_complete       pme_processor.rz
 696
 697
 698 #define pmci_cache_level                        pme_cache.level
 699 #define pmci_cache_line_state                   pme_cache.mesi
 700 #define pmci_cache_line_state_valid             pme_cache.mv
 701 #define pmci_cache_line_index                   pme_cache.index
 702 #define pmci_cache_instr_cache_fail             pme_cache.ic
 703 #define pmci_cache_data_cache_fail              pme_cache.dc
 704 #define pmci_cache_line_tag_fail                pme_cache.tl
 705 #define pmci_cache_line_data_fail               pme_cache.dl
 706 #define pmci_cache_operation                    pme_cache.op
 707 #define pmci_cache_way_valid                    pme_cache.wv
 708 #define pmci_cache_target_address_valid         pme_cache.tv
 709 #define pmci_cache_way                          pme_cache.way
 710 #define pmci_cache_mc                           pme_cache.mc
 711
 712 #define pmci_tlb_instr_translation_cache_fail   pme_tlb.itc
 713 #define pmci_tlb_data_translation_cache_fail    pme_tlb.dtc
 714 #define pmci_tlb_instr_translation_reg_fail     pme_tlb.itr
 715 #define pmci_tlb_data_translation_reg_fail      pme_tlb.dtr
 716 #define pmci_tlb_translation_reg_slot           pme_tlb.tr_slot
 717 #define pmci_tlb_mc                             pme_tlb.mc
 718
 719 #define pmci_bus_status_info                    pme_bus.bsi
 720 #define pmci_bus_req_address_valid              pme_bus.rq
 721 #define pmci_bus_resp_address_valid             pme_bus.rp
 722 #define pmci_bus_target_address_valid           pme_bus.tv
 723 #define pmci_bus_error_severity                 pme_bus.sev
 724 #define pmci_bus_transaction_type               pme_bus.type
 725 #define pmci_bus_cache_cache_transfer           pme_bus.cc
 726 #define pmci_bus_transaction_size               pme_bus.size
 727 #define pmci_bus_internal_error                 pme_bus.ib
 728 #define pmci_bus_external_error                 pme_bus.eb
 729 #define pmci_bus_mc                             pme_bus.mc
 730
 731 /*
 732  * NOTE: this min_state_save area struct only includes the 1KB
 733  * architectural state save area.  The other 3 KB is scratch space
 734  * for PAL.
 735  */
 736
 737 typedef struct pal_min_state_area_s {
 738         u64     pmsa_nat_bits;          /* nat bits for saved GRs  */
 739         u64     pmsa_gr[15];            /* GR1  - GR15             */
 740         u64     pmsa_bank0_gr[16];      /* GR16 - GR31             */
 741         u64     pmsa_bank1_gr[16];      /* GR16 - GR31             */
 742         u64     pmsa_pr;                /* predicate registers     */
 743         u64     pmsa_br0;               /* branch register 0       */
 744         u64     pmsa_rsc;               /* ar.rsc                  */
 745         u64     pmsa_iip;               /* cr.iip                  */
 746         u64     pmsa_ipsr;              /* cr.ipsr                 */
 747         u64     pmsa_ifs;               /* cr.ifs                  */
 748         u64     pmsa_xip;               /* previous iip            */
 749         u64     pmsa_xpsr;              /* previous psr            */
 750         u64     pmsa_xfs;               /* previous ifs            */
 751         u64     pmsa_br1;               /* branch register 1       */
 752         u64     pmsa_reserved[70];      /* pal_min_state_area should total to 1KB */
 753 } pal_min_state_area_t;
 754
 755
 756 struct ia64_pal_retval {
 757         /*
 758          * A zero status value indicates call completed without error.
 759          * A negative status value indicates reason of call failure.
 760          * A positive status value indicates success but an
 761          * informational value should be printed (e.g., "reboot for
 762          * change to take effect").
 763          */
 764         s64 status;
 765         u64 v0;
 766         u64 v1;
 767         u64 v2;
 768 };
 769
 770 /*
 771  * Note: Currently unused PAL arguments are generally labeled
 772  * "reserved" so the value specified in the PAL documentation
 773  * (generally 0) MUST be passed.  Reserved parameters are not optional
 774  * parameters.
 775  */
 776 extern struct ia64_pal_retval ia64_pal_call_static (u64, u64, u64, u64);
 777 extern struct ia64_pal_retval ia64_pal_call_stacked (u64, u64, u64, u64);
 778 extern struct ia64_pal_retval ia64_pal_call_phys_static (u64, u64, u64, u64);
 779 extern struct ia64_pal_retval ia64_pal_call_phys_stacked (u64, u64, u64, u64);
 780 extern void ia64_save_scratch_fpregs (struct ia64_fpreg *);
 781 extern void ia64_load_scratch_fpregs (struct ia64_fpreg *);
 782
 783 #define PAL_CALL(iprv,a0,a1,a2,a3) do {                 \
 784         struct ia64_fpreg fr[6];                        \
 785         ia64_save_scratch_fpregs(fr);                   \
 786         iprv = ia64_pal_call_static(a0, a1, a2, a3);    \
 787         ia64_load_scratch_fpregs(fr);                   \
 788 } while (0)
 789
 790 #define PAL_CALL_STK(iprv,a0,a1,a2,a3) do {             \
 791         struct ia64_fpreg fr[6];                        \
 792         ia64_save_scratch_fpregs(fr);                   \
 793         iprv = ia64_pal_call_stacked(a0, a1, a2, a3);   \
 794         ia64_load_scratch_fpregs(fr);                   \
 795 } while (0)
 796
 797 #define PAL_CALL_PHYS(iprv,a0,a1,a2,a3) do {                    \
 798         struct ia64_fpreg fr[6];                                \
 799         ia64_save_scratch_fpregs(fr);                           \
 800         iprv = ia64_pal_call_phys_static(a0, a1, a2, a3);       \
 801         ia64_load_scratch_fpregs(fr);                           \
 802 } while (0)
 803
 804 #define PAL_CALL_PHYS_STK(iprv,a0,a1,a2,a3) do {                \
 805         struct ia64_fpreg fr[6];                                \
 806         ia64_save_scratch_fpregs(fr);                           \
 807         iprv = ia64_pal_call_phys_stacked(a0, a1, a2, a3);      \
 808         ia64_load_scratch_fpregs(fr);                           \
 809 } while (0)
 810
 811 typedef int (*ia64_pal_handler) (u64, ...);
 812 extern ia64_pal_handler ia64_pal;
 813 extern void ia64_pal_handler_init (void *);
 814
 815 extern ia64_pal_handler ia64_pal;
 816
 817 extern pal_cache_config_info_t          l0d_cache_config_info;
 818 extern pal_cache_config_info_t          l0i_cache_config_info;
 819 extern pal_cache_config_info_t          l1_cache_config_info;
 820 extern pal_cache_config_info_t          l2_cache_config_info;
 821
 822 extern pal_cache_protection_info_t      l0d_cache_protection_info;
 823 extern pal_cache_protection_info_t      l0i_cache_protection_info;
 824 extern pal_cache_protection_info_t      l1_cache_protection_info;
 825 extern pal_cache_protection_info_t      l2_cache_protection_info;
 826
 827 extern pal_cache_config_info_t          pal_cache_config_info_get(pal_cache_level_t,
 828                                                                   pal_cache_type_t);
 829
 830 extern pal_cache_protection_info_t      pal_cache_protection_info_get(pal_cache_level_t,
 831                                                                       pal_cache_type_t);
 832
 833
 834 extern void                             pal_error(int);
 835
 836
 837 /* Useful wrappers for the current list of pal procedures */
 838
 839 typedef union pal_bus_features_u {
 840         u64     pal_bus_features_val;
 841         struct {
 842                 u64     pbf_reserved1                           :       29;
 843                 u64     pbf_req_bus_parking                     :       1;
 844                 u64     pbf_bus_lock_mask                       :       1;
 845                 u64     pbf_enable_half_xfer_rate               :       1;
 846                 u64     pbf_reserved2                           :       20;
 847                 u64     pbf_enable_shared_line_replace          :       1;
 848                 u64     pbf_enable_exclusive_line_replace       :       1;
 849                 u64     pbf_disable_xaction_queueing            :       1;
 850                 u64     pbf_disable_resp_err_check              :       1;
 851                 u64     pbf_disable_berr_check                  :       1;
 852                 u64     pbf_disable_bus_req_internal_err_signal :       1;
 853                 u64     pbf_disable_bus_req_berr_signal         :       1;
 854                 u64     pbf_disable_bus_init_event_check        :       1;
 855                 u64     pbf_disable_bus_init_event_signal       :       1;
 856                 u64     pbf_disable_bus_addr_err_check          :       1;
 857                 u64     pbf_disable_bus_addr_err_signal         :       1;
 858                 u64     pbf_disable_bus_data_err_check          :       1;
 859         } pal_bus_features_s;
 860 } pal_bus_features_u_t;
 861
 862 extern void pal_bus_features_print (u64);
 863
 864 /* Provide information about configurable processor bus features */
 865 static inline s64
 866 ia64_pal_bus_get_features (pal_bus_features_u_t *features_avail,
 867                            pal_bus_features_u_t *features_status,
 868                            pal_bus_features_u_t *features_control)
 869 {
 870         struct ia64_pal_retval iprv;
 871         PAL_CALL_PHYS(iprv, PAL_BUS_GET_FEATURES, 0, 0, 0);
 872         if (features_avail)
 873                 features_avail->pal_bus_features_val = iprv.v0;
 874         if (features_status)
 875                 features_status->pal_bus_features_val = iprv.v1;
 876         if (features_control)
 877                 features_control->pal_bus_features_val = iprv.v2;
 878         return iprv.status;
 879 }
 880
 881 /* Enables/disables specific processor bus features */
 882 static inline s64
 883 ia64_pal_bus_set_features (pal_bus_features_u_t feature_select)
 884 {
 885         struct ia64_pal_retval iprv;
 886         PAL_CALL_PHYS(iprv, PAL_BUS_SET_FEATURES, feature_select.pal_bus_features_val, 0, 0);
 887         return iprv.status;
 888 }
 889
 890 /* Get detailed cache information */
 891 static inline s64
 892 ia64_pal_cache_config_info (u64 cache_level, u64 cache_type, pal_cache_config_info_t *conf)
 893 {
 894         struct ia64_pal_retval iprv;
 895
 896         PAL_CALL(iprv, PAL_CACHE_INFO, cache_level, cache_type, 0);
 897
 898         if (iprv.status == 0) {
 899                 conf->pcci_status                 = iprv.status;
 900                 conf->pcci_info_1.pcci1_data      = iprv.v0;
 901                 conf->pcci_info_2.pcci2_data      = iprv.v1;
 902                 conf->pcci_reserved               = iprv.v2;
 903         }
 904         return iprv.status;
 905
 906 }
 907
 908 /* Get detailed cche protection information */
 909 static inline s64
 910 ia64_pal_cache_prot_info (u64 cache_level, u64 cache_type, pal_cache_protection_info_t *prot)
 911 {
 912         struct ia64_pal_retval iprv;
 913
 914         PAL_CALL(iprv, PAL_CACHE_PROT_INFO, cache_level, cache_type, 0);
 915
 916         if (iprv.status == 0) {
 917                 prot->pcpi_status           = iprv.status;
 918                 prot->pcp_info[0].pcpi_data = iprv.v0 & 0xffffffff;
 919                 prot->pcp_info[1].pcpi_data = iprv.v0 >> 32;
 920                 prot->pcp_info[2].pcpi_data = iprv.v1 & 0xffffffff;
 921                 prot->pcp_info[3].pcpi_data = iprv.v1 >> 32;
 922                 prot->pcp_info[4].pcpi_data = iprv.v2 & 0xffffffff;
 923                 prot->pcp_info[5].pcpi_data = iprv.v2 >> 32;
 924         }
 925         return iprv.status;
 926 }
 927
 928 /*
 929  * Flush the processor instruction or data caches.  *PROGRESS must be
 930  * initialized to zero before calling this for the first time..
 931  */
 932 static inline s64
 933 ia64_pal_cache_flush (u64 cache_type, u64 invalidate, u64 *progress, u64 *vector)
 934 {
 935         struct ia64_pal_retval iprv;
 936         PAL_CALL(iprv, PAL_CACHE_FLUSH, cache_type, invalidate, *progress);
 937         if (vector)
 938                 *vector = iprv.v0;
 939         *progress = iprv.v1;
 940         return iprv.status;
 941 }
 942
 943
 944 /* Initialize the processor controlled caches */
 945 static inline s64
 946 ia64_pal_cache_init (u64 level, u64 cache_type, u64 rest)
 947 {
 948         struct ia64_pal_retval iprv;
 949         PAL_CALL(iprv, PAL_CACHE_INIT, level, cache_type, rest);
 950         return iprv.status;
 951 }
 952
 953 /* Initialize the tags and data of a data or unified cache line of
 954  * processor controlled cache to known values without the availability
 955  * of backing memory.
 956  */
 957 static inline s64
 958 ia64_pal_cache_line_init (u64 physical_addr, u64 data_value)
 959 {
 960         struct ia64_pal_retval iprv;
 961         PAL_CALL(iprv, PAL_CACHE_LINE_INIT, physical_addr, data_value, 0);
 962         return iprv.status;
 963 }
 964
 965
 966 /* Read the data and tag of a processor controlled cache line for diags */
 967 static inline s64
 968 ia64_pal_cache_read (pal_cache_line_id_u_t line_id, u64 physical_addr)
 969 {
 970         struct ia64_pal_retval iprv;
 971         PAL_CALL_PHYS_STK(iprv, PAL_CACHE_READ, line_id.pclid_data,
 972                                 physical_addr, 0);
 973         return iprv.status;
 974 }
 975
 976 /* Return summary information about the heirarchy of caches controlled by the processor */
 977 static inline s64
 978 ia64_pal_cache_summary (u64 *cache_levels, u64 *unique_caches)
 979 {
 980         struct ia64_pal_retval iprv;
 981         PAL_CALL(iprv, PAL_CACHE_SUMMARY, 0, 0, 0);
 982         if (cache_levels)
 983                 *cache_levels = iprv.v0;
 984         if (unique_caches)
 985                 *unique_caches = iprv.v1;
 986         return iprv.status;
 987 }
 988
 989 /* Write the data and tag of a processor-controlled cache line for diags */
 990 static inline s64
 991 ia64_pal_cache_write (pal_cache_line_id_u_t line_id, u64 physical_addr, u64 data)
 992 {
 993         struct ia64_pal_retval iprv;
 994         PAL_CALL_PHYS_STK(iprv, PAL_CACHE_WRITE, line_id.pclid_data,
 995                                 physical_addr, data);
 996         return iprv.status;
 997 }
 998
 999
1000 /* Return the parameters needed to copy relocatable PAL procedures from ROM to memory */
1001 static inline s64
1002 ia64_pal_copy_info (u64 copy_type, u64 num_procs, u64 num_iopics,
1003                     u64 *buffer_size, u64 *buffer_align)
1004 {
1005         struct ia64_pal_retval iprv;
1006         PAL_CALL(iprv, PAL_COPY_INFO, copy_type, num_procs, num_iopics);
1007         if (buffer_size)
1008                 *buffer_size = iprv.v0;
1009         if (buffer_align)
1010                 *buffer_align = iprv.v1;
1011         return iprv.status;
1012 }
1013
1014 /* Copy relocatable PAL procedures from ROM to memory */
1015 static inline s64
1016 ia64_pal_copy_pal (u64 target_addr, u64 alloc_size, u64 processor, u64 *pal_proc_offset)
1017 {
1018         struct ia64_pal_retval iprv;
1019         PAL_CALL(iprv, PAL_COPY_PAL, target_addr, alloc_size, processor);
1020         if (pal_proc_offset)
1021                 *pal_proc_offset = iprv.v0;
1022         return iprv.status;
1023 }
1024
1025 /* Return the number of instruction and data debug register pairs */
1026 static inline s64
1027 ia64_pal_debug_info (u64 *inst_regs,  u64 *data_regs)
1028 {
1029         struct ia64_pal_retval iprv;
1030         PAL_CALL(iprv, PAL_DEBUG_INFO, 0, 0, 0);
1031         if (inst_regs)
1032                 *inst_regs = iprv.v0;
1033         if (data_regs)
1034                 *data_regs = iprv.v1;
1035
1036         return iprv.status;
1037 }
1038
1039 #ifdef TBD
1040 /* Switch from IA64-system environment to IA-32 system environment */
1041 static inline s64
1042 ia64_pal_enter_ia32_env (ia32_env1, ia32_env2, ia32_env3)
1043 {
1044         struct ia64_pal_retval iprv;
1045         PAL_CALL(iprv, PAL_ENTER_IA_32_ENV, ia32_env1, ia32_env2, ia32_env3);
1046         return iprv.status;
1047 }
1048 #endif
1049
1050 /* Get unique geographical address of this processor on its bus */
1051 static inline s64
1052 ia64_pal_fixed_addr (u64 *global_unique_addr)
1053 {
1054         struct ia64_pal_retval iprv;
1055         PAL_CALL(iprv, PAL_FIXED_ADDR, 0, 0, 0);
1056         if (global_unique_addr)
1057                 *global_unique_addr = iprv.v0;
1058         return iprv.status;
1059 }
1060
1061 /* Get base frequency of the platform if generated by the processor */
1062 static inline s64
1063 ia64_pal_freq_base (u64 *platform_base_freq)
1064 {
1065         struct ia64_pal_retval iprv;
1066         PAL_CALL(iprv, PAL_FREQ_BASE, 0, 0, 0);
1067         if (platform_base_freq)
1068                 *platform_base_freq = iprv.v0;
1069         return iprv.status;
1070 }
1071
1072 /*
1073  * Get the ratios for processor frequency, bus frequency and interval timer to
1074  * to base frequency of the platform
1075  */
1076 static inline s64
1077 ia64_pal_freq_ratios (struct pal_freq_ratio *proc_ratio, struct pal_freq_ratio *bus_ratio,
1078                       struct pal_freq_ratio *itc_ratio)
1079 {
1080         struct ia64_pal_retval iprv;
1081         PAL_CALL(iprv, PAL_FREQ_RATIOS, 0, 0, 0);
1082         if (proc_ratio)
1083                 *(u64 *)proc_ratio = iprv.v0;
1084         if (bus_ratio)
1085                 *(u64 *)bus_ratio = iprv.v1;
1086         if (itc_ratio)
1087                 *(u64 *)itc_ratio = iprv.v2;
1088         return iprv.status;
1089 }
1090
1091 /*
1092  * Get the current hardware resource sharing policy of the processor
1093  */
1094 static inline s64
1095 ia64_pal_get_hw_policy (u64 proc_num, u64 *cur_policy, u64 *num_impacted,
1096                         u64 *la)
1097 {
1098         struct ia64_pal_retval iprv;
1099         PAL_CALL(iprv, PAL_GET_HW_POLICY, proc_num, 0, 0);
1100         if (cur_policy)
1101                 *cur_policy = iprv.v0;
1102         if (num_impacted)
1103                 *num_impacted = iprv.v1;
1104         if (la)
1105                 *la = iprv.v2;
1106         return iprv.status;
1107 }
1108
1109 /* Make the processor enter HALT or one of the implementation dependent low
1110  * power states where prefetching and execution are suspended and cache and
1111  * TLB coherency is not maintained.
1112  */
1113 static inline s64
1114 ia64_pal_halt (u64 halt_state)
1115 {
1116         struct ia64_pal_retval iprv;
1117         PAL_CALL(iprv, PAL_HALT, halt_state, 0, 0);
1118         return iprv.status;
1119 }
1120
1121 typedef union pal_power_mgmt_info_u {
1122         u64                     ppmi_data;
1123         struct {
1124                u64              exit_latency            : 16,
1125                                 entry_latency           : 16,
1126                                 power_consumption       : 28,
1127                                 im                      : 1,
1128                                 co                      : 1,
1129                                 reserved                : 2;
1130         } pal_power_mgmt_info_s;
1131 } pal_power_mgmt_info_u_t;
1132
1133 /* Return information about processor's optional power management capabilities. */
1134 static inline s64
1135 ia64_pal_halt_info (pal_power_mgmt_info_u_t *power_buf)
1136 {
1137         struct ia64_pal_retval iprv;
1138         PAL_CALL_STK(iprv, PAL_HALT_INFO, (unsigned long) power_buf, 0, 0);
1139         return iprv.status;
1140 }
1141
1142 /* Get the current P-state information */
1143 static inline s64
1144 ia64_pal_get_pstate (u64 *pstate_index)
1145 {
1146         struct ia64_pal_retval iprv;
1147         PAL_CALL_STK(iprv, PAL_GET_PSTATE, 0, 0, 0);
1148         *pstate_index = iprv.v0;
1149         return iprv.status;
1150 }
1151
1152 /* Set the P-state */
1153 static inline s64
1154 ia64_pal_set_pstate (u64 pstate_index)
1155 {
1156         struct ia64_pal_retval iprv;
1157         PAL_CALL_STK(iprv, PAL_SET_PSTATE, pstate_index, 0, 0);
1158         return iprv.status;
1159 }
1160
1161 /* Processor branding information*/
1162 static inline s64
1163 ia64_pal_get_brand_info (char *brand_info)
1164 {
1165         struct ia64_pal_retval iprv;
1166         PAL_CALL_STK(iprv, PAL_BRAND_INFO, 0, (u64)brand_info, 0);
1167         return iprv.status;
1168 }
1169
1170 /* Cause the processor to enter LIGHT HALT state, where prefetching and execution are
1171  * suspended, but cache and TLB coherency is maintained.
1172  */
1173 static inline s64
1174 ia64_pal_halt_light (void)
1175 {
1176         struct ia64_pal_retval iprv;
1177         PAL_CALL(iprv, PAL_HALT_LIGHT, 0, 0, 0);
1178         return iprv.status;
1179 }
1180
1181 /* Clear all the processor error logging   registers and reset the indicator that allows
1182  * the error logging registers to be written. This procedure also checks the pending
1183  * machine check bit and pending INIT bit and reports their states.
1184  */
1185 static inline s64
1186 ia64_pal_mc_clear_log (u64 *pending_vector)
1187 {
1188         struct ia64_pal_retval iprv;
1189         PAL_CALL(iprv, PAL_MC_CLEAR_LOG, 0, 0, 0);
1190         if (pending_vector)
1191                 *pending_vector = iprv.v0;
1192         return iprv.status;
1193 }
1194
1195 /* Ensure that all outstanding transactions in a processor are completed or that any
1196  * MCA due to thes outstanding transaction is taken.
1197  */
1198 static inline s64
1199 ia64_pal_mc_drain (void)
1200 {
1201         struct ia64_pal_retval iprv;
1202         PAL_CALL(iprv, PAL_MC_DRAIN, 0, 0, 0);
1203         return iprv.status;
1204 }
1205
1206 /* Return the machine check dynamic processor state */
1207 static inline s64
1208 ia64_pal_mc_dynamic_state (u64 offset, u64 *size, u64 *pds)
1209 {
1210         struct ia64_pal_retval iprv;
1211         PAL_CALL(iprv, PAL_MC_DYNAMIC_STATE, offset, 0, 0);
1212         if (size)
1213                 *size = iprv.v0;
1214         if (pds)
1215                 *pds = iprv.v1;
1216         return iprv.status;
1217 }
1218
1219 /* Return processor machine check information */
1220 static inline s64
1221 ia64_pal_mc_error_info (u64 info_index, u64 type_index, u64 *size, u64 *error_info)
1222 {
1223         struct ia64_pal_retval iprv;
1224         PAL_CALL(iprv, PAL_MC_ERROR_INFO, info_index, type_index, 0);
1225         if (size)
1226                 *size = iprv.v0;
1227         if (error_info)
1228                 *error_info = iprv.v1;
1229         return iprv.status;
1230 }
1231
1232 /* Inform PALE_CHECK whether a machine check is expected so that PALE_CHECK willnot
1233  * attempt to correct any expected machine checks.
1234  */
1235 static inline s64
1236 ia64_pal_mc_expected (u64 expected, u64 *previous)
1237 {
1238         struct ia64_pal_retval iprv;
1239         PAL_CALL(iprv, PAL_MC_EXPECTED, expected, 0, 0);
1240         if (previous)
1241                 *previous = iprv.v0;
1242         return iprv.status;
1243 }
1244
1245 /* Register a platform dependent location with PAL to which it can save
1246  * minimal processor state in the event of a machine check or initialization
1247  * event.
1248  */
1249 static inline s64
1250 ia64_pal_mc_register_mem (u64 physical_addr)
1251 {
1252         struct ia64_pal_retval iprv;
1253         PAL_CALL(iprv, PAL_MC_REGISTER_MEM, physical_addr, 0, 0);
1254         return iprv.status;
1255 }
1256
1257 /* Restore minimal architectural processor state, set CMC interrupt if necessary
1258  * and resume execution
1259  */
1260 static inline s64
1261 ia64_pal_mc_resume (u64 set_cmci, u64 save_ptr)
1262 {
1263         struct ia64_pal_retval iprv;
1264         PAL_CALL(iprv, PAL_MC_RESUME, set_cmci, save_ptr, 0);
1265         return iprv.status;
1266 }
1267
1268 /* Return the memory attributes implemented by the processor */
1269 static inline s64
1270 ia64_pal_mem_attrib (u64 *mem_attrib)
1271 {
1272         struct ia64_pal_retval iprv;
1273         PAL_CALL(iprv, PAL_MEM_ATTRIB, 0, 0, 0);
1274         if (mem_attrib)
1275                 *mem_attrib = iprv.v0 & 0xff;
1276         return iprv.status;
1277 }
1278
1279 /* Return the amount of memory needed for second phase of processor
1280  * self-test and the required alignment of memory.
1281  */
1282 static inline s64
1283 ia64_pal_mem_for_test (u64 *bytes_needed, u64 *alignment)
1284 {
1285         struct ia64_pal_retval iprv;
1286         PAL_CALL(iprv, PAL_MEM_FOR_TEST, 0, 0, 0);
1287         if (bytes_needed)
1288                 *bytes_needed = iprv.v0;
1289         if (alignment)
1290                 *alignment = iprv.v1;
1291         return iprv.status;
1292 }
1293
1294 typedef union pal_perf_mon_info_u {
1295         u64                       ppmi_data;
1296         struct {
1297                u64              generic         : 8,
1298                                 width           : 8,
1299                                 cycles          : 8,
1300                                 retired         : 8,
1301                                 reserved        : 32;
1302         } pal_perf_mon_info_s;
1303 } pal_perf_mon_info_u_t;
1304
1305 /* Return the performance monitor information about what can be counted
1306  * and how to configure the monitors to count the desired events.
1307  */
1308 static inline s64
1309 ia64_pal_perf_mon_info (u64 *pm_buffer, pal_perf_mon_info_u_t *pm_info)
1310 {
1311         struct ia64_pal_retval iprv;
1312         PAL_CALL(iprv, PAL_PERF_MON_INFO, (unsigned long) pm_buffer, 0, 0);
1313         if (pm_info)
1314                 pm_info->ppmi_data = iprv.v0;
1315         return iprv.status;
1316 }
1317
1318 /* Specifies the physical address of the processor interrupt block
1319  * and I/O port space.
1320  */
1321 static inline s64
1322 ia64_pal_platform_addr (u64 type, u64 physical_addr)
1323 {
1324         struct ia64_pal_retval iprv;
1325         PAL_CALL(iprv, PAL_PLATFORM_ADDR, type, physical_addr, 0);
1326         return iprv.status;
1327 }
1328
1329 /* Set the SAL PMI entrypoint in memory */
1330 static inline s64
1331 ia64_pal_pmi_entrypoint (u64 sal_pmi_entry_addr)
1332 {
1333         struct ia64_pal_retval iprv;
1334         PAL_CALL(iprv, PAL_PMI_ENTRYPOINT, sal_pmi_entry_addr, 0, 0);
1335         return iprv.status;
1336 }
1337
1338 struct pal_features_s;
1339 /* Provide information about configurable processor features */
1340 static inline s64
1341 ia64_pal_proc_get_features (u64 *features_avail,
1342                             u64 *features_status,
1343                             u64 *features_control)
1344 {
1345         struct ia64_pal_retval iprv;
1346         PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, 0, 0);
1347         if (iprv.status == 0) {
1348                 *features_avail   = iprv.v0;
1349                 *features_status  = iprv.v1;
1350                 *features_control = iprv.v2;
1351         }
1352         return iprv.status;
1353 }
1354
1355 /* Enable/disable processor dependent features */
1356 static inline s64
1357 ia64_pal_proc_set_features (u64 feature_select)
1358 {
1359         struct ia64_pal_retval iprv;
1360         PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES, feature_select, 0, 0);
1361         return iprv.status;
1362 }
1363
1364 /*
1365  * Put everything in a struct so we avoid the global offset table whenever
1366  * possible.
1367  */
1368 typedef struct ia64_ptce_info_s {
1369         u64             base;
1370         u32             count[2];
1371         u32             stride[2];
1372 } ia64_ptce_info_t;
1373
1374 /* Return the information required for the architected loop used to purge
1375  * (initialize) the entire TC
1376  */
1377 static inline s64
1378 ia64_get_ptce (ia64_ptce_info_t *ptce)
1379 {
1380         struct ia64_pal_retval iprv;
1381
1382         if (!ptce)
1383                 return -1;
1384
1385         PAL_CALL(iprv, PAL_PTCE_INFO, 0, 0, 0);
1386         if (iprv.status == 0) {
1387                 ptce->base = iprv.v0;
1388                 ptce->count[0] = iprv.v1 >> 32;
1389                 ptce->count[1] = iprv.v1 & 0xffffffff;
1390                 ptce->stride[0] = iprv.v2 >> 32;
1391                 ptce->stride[1] = iprv.v2 & 0xffffffff;
1392         }
1393         return iprv.status;
1394 }
1395
1396 /* Return info about implemented application and control registers. */
1397 static inline s64
1398 ia64_pal_register_info (u64 info_request, u64 *reg_info_1, u64 *reg_info_2)
1399 {
1400         struct ia64_pal_retval iprv;
1401         PAL_CALL(iprv, PAL_REGISTER_INFO, info_request, 0, 0);
1402         if (reg_info_1)
1403                 *reg_info_1 = iprv.v0;
1404         if (reg_info_2)
1405                 *reg_info_2 = iprv.v1;
1406         return iprv.status;
1407 }
1408
1409 typedef union pal_hints_u {
1410         u64                     ph_data;
1411         struct {
1412                u64              si              : 1,
1413                                 li              : 1,
1414                                 reserved        : 62;
1415         } pal_hints_s;
1416 } pal_hints_u_t;
1417
1418 /* Return information about the register stack and RSE for this processor
1419  * implementation.
1420  */
1421 static inline s64
1422 ia64_pal_rse_info (u64 *num_phys_stacked, pal_hints_u_t *hints)
1423 {
1424         struct ia64_pal_retval iprv;
1425         PAL_CALL(iprv, PAL_RSE_INFO, 0, 0, 0);
1426         if (num_phys_stacked)
1427                 *num_phys_stacked = iprv.v0;
1428         if (hints)
1429                 hints->ph_data = iprv.v1;
1430         return iprv.status;
1431 }
1432
1433 /*
1434  * Set the current hardware resource sharing policy of the processor
1435  */
1436 static inline s64
1437 ia64_pal_set_hw_policy (u64 policy)
1438 {
1439         struct ia64_pal_retval iprv;
1440         PAL_CALL(iprv, PAL_SET_HW_POLICY, policy, 0, 0);
1441         return iprv.status;
1442 }
1443
1444 /* Cause the processor to enter SHUTDOWN state, where prefetching and execution are
1445  * suspended, but cause cache and TLB coherency to be maintained.
1446  * This is usually called in IA-32 mode.
1447  */
1448 static inline s64
1449 ia64_pal_shutdown (void)
1450 {
1451         struct ia64_pal_retval iprv;
1452         PAL_CALL(iprv, PAL_SHUTDOWN, 0, 0, 0);
1453         return iprv.status;
1454 }
1455
1456 /* Perform the second phase of processor self-test. */
1457 static inline s64
1458 ia64_pal_test_proc (u64 test_addr, u64 test_size, u64 attributes, u64 *self_test_state)
1459 {
1460         struct ia64_pal_retval iprv;
1461         PAL_CALL(iprv, PAL_TEST_PROC, test_addr, test_size, attributes);
1462         if (self_test_state)
1463                 *self_test_state = iprv.v0;
1464         return iprv.status;
1465 }
1466
1467 typedef union  pal_version_u {
1468         u64     pal_version_val;
1469         struct {
1470                 u64     pv_pal_b_rev            :       8;
1471                 u64     pv_pal_b_model          :       8;
1472                 u64     pv_reserved1            :       8;
1473                 u64     pv_pal_vendor           :       8;
1474                 u64     pv_pal_a_rev            :       8;
1475                 u64     pv_pal_a_model          :       8;
1476                 u64     pv_reserved2            :       16;
1477         } pal_version_s;
1478 } pal_version_u_t;
1479
1480
1481 /*
1482  * Return PAL version information.  While the documentation states that
1483  * PAL_VERSION can be called in either physical or virtual mode, some
1484  * implementations only allow physical calls.  We don't call it very often,
1485  * so the overhead isn't worth eliminating.
1486  */
1487 static inline s64
1488 ia64_pal_version (pal_version_u_t *pal_min_version, pal_version_u_t *pal_cur_version)
1489 {
1490         struct ia64_pal_retval iprv;
1491         PAL_CALL_PHYS(iprv, PAL_VERSION, 0, 0, 0);
1492         if (pal_min_version)
1493                 pal_min_version->pal_version_val = iprv.v0;
1494
1495         if (pal_cur_version)
1496                 pal_cur_version->pal_version_val = iprv.v1;
1497
1498         return iprv.status;
1499 }
1500
1501 typedef union pal_tc_info_u {
1502         u64                     pti_val;
1503         struct {
1504                u64              num_sets        :       8,
1505                                 associativity   :       8,
1506                                 num_entries     :       16,
1507                                 pf              :       1,
1508                                 unified         :       1,
1509                                 reduce_tr       :       1,
1510                                 reserved        :       29;
1511         } pal_tc_info_s;
1512 } pal_tc_info_u_t;
1513
1514 #define tc_reduce_tr            pal_tc_info_s.reduce_tr
1515 #define tc_unified              pal_tc_info_s.unified
1516 #define tc_pf                   pal_tc_info_s.pf
1517 #define tc_num_entries          pal_tc_info_s.num_entries
1518 #define tc_associativity        pal_tc_info_s.associativity
1519 #define tc_num_sets             pal_tc_info_s.num_sets
1520
1521
1522 /* Return information about the virtual memory characteristics of the processor
1523  * implementation.
1524  */
1525 static inline s64
1526 ia64_pal_vm_info (u64 tc_level, u64 tc_type,  pal_tc_info_u_t *tc_info, u64 *tc_pages)
1527 {
1528         struct ia64_pal_retval iprv;
1529         PAL_CALL(iprv, PAL_VM_INFO, tc_level, tc_type, 0);
1530         if (tc_info)
1531                 tc_info->pti_val = iprv.v0;
1532         if (tc_pages)
1533                 *tc_pages = iprv.v1;
1534         return iprv.status;
1535 }
1536
1537 /* Get page size information about the virtual memory characteristics of the processor
1538  * implementation.
1539  */
1540 static inline s64
1541 ia64_pal_vm_page_size (u64 *tr_pages, u64 *vw_pages)
1542 {
1543         struct ia64_pal_retval iprv;
1544         PAL_CALL(iprv, PAL_VM_PAGE_SIZE, 0, 0, 0);
1545         if (tr_pages)
1546                 *tr_pages = iprv.v0;
1547         if (vw_pages)
1548                 *vw_pages = iprv.v1;
1549         return iprv.status;
1550 }
1551
1552 typedef union pal_vm_info_1_u {
1553         u64                     pvi1_val;
1554         struct {
1555                 u64             vw              : 1,
1556                                 phys_add_size   : 7,
1557                                 key_size        : 8,
1558                                 max_pkr         : 8,
1559                                 hash_tag_id     : 8,
1560                                 max_dtr_entry   : 8,
1561                                 max_itr_entry   : 8,
1562                                 max_unique_tcs  : 8,
1563                                 num_tc_levels   : 8;
1564         } pal_vm_info_1_s;
1565 } pal_vm_info_1_u_t;
1566
1567 #define PAL_MAX_PURGES          0xFFFF          /* all ones is means unlimited */
1568
1569 typedef union pal_vm_info_2_u {
1570         u64                     pvi2_val;
1571         struct {
1572                 u64             impl_va_msb     : 8,
1573                                 rid_size        : 8,
1574                                 max_purges      : 16,
1575                                 reserved        : 32;
1576         } pal_vm_info_2_s;
1577 } pal_vm_info_2_u_t;
1578
1579 /* Get summary information about the virtual memory characteristics of the processor
1580  * implementation.
1581  */
1582 static inline s64
1583 ia64_pal_vm_summary (pal_vm_info_1_u_t *vm_info_1, pal_vm_info_2_u_t *vm_info_2)
1584 {
1585         struct ia64_pal_retval iprv;
1586         PAL_CALL(iprv, PAL_VM_SUMMARY, 0, 0, 0);
1587         if (vm_info_1)
1588                 vm_info_1->pvi1_val = iprv.v0;
1589         if (vm_info_2)
1590                 vm_info_2->pvi2_val = iprv.v1;
1591         return iprv.status;
1592 }
1593
1594 typedef union pal_itr_valid_u {
1595         u64                     piv_val;
1596         struct {
1597                u64              access_rights_valid     : 1,
1598                                 priv_level_valid        : 1,
1599                                 dirty_bit_valid         : 1,
1600                                 mem_attr_valid          : 1,
1601                                 reserved                : 60;
1602         } pal_tr_valid_s;
1603 } pal_tr_valid_u_t;
1604
1605 /* Read a translation register */
1606 static inline s64
1607 ia64_pal_tr_read (u64 reg_num, u64 tr_type, u64 *tr_buffer, pal_tr_valid_u_t *tr_valid)
1608 {
1609         struct ia64_pal_retval iprv;
1610         PAL_CALL_PHYS_STK(iprv, PAL_VM_TR_READ, reg_num, tr_type,(u64)ia64_tpa(tr_buffer));
1611         if (tr_valid)
1612                 tr_valid->piv_val = iprv.v0;
1613         return iprv.status;
1614 }
1615
1616 /*
1617  * PAL_PREFETCH_VISIBILITY transaction types
1618  */
1619 #define PAL_VISIBILITY_VIRTUAL          0
1620 #define PAL_VISIBILITY_PHYSICAL         1
1621
1622 /*
1623  * PAL_PREFETCH_VISIBILITY return codes
1624  */
1625 #define PAL_VISIBILITY_OK               1
1626 #define PAL_VISIBILITY_OK_REMOTE_NEEDED 0
1627 #define PAL_VISIBILITY_INVAL_ARG        -2
1628 #define PAL_VISIBILITY_ERROR            -3
1629
1630 static inline s64
1631 ia64_pal_prefetch_visibility (s64 trans_type)
1632 {
1633         struct ia64_pal_retval iprv;
1634         PAL_CALL(iprv, PAL_PREFETCH_VISIBILITY, trans_type, 0, 0);
1635         return iprv.status;
1636 }
1637
1638 /* data structure for getting information on logical to physical mappings */
1639 typedef union pal_log_overview_u {
1640         struct {
1641                 u64     num_log         :16,    /* Total number of logical
1642                                                  * processors on this die
1643                                                  */
1644                         tpc             :8,     /* Threads per core */
1645                         reserved3       :8,     /* Reserved */
1646                         cpp             :8,     /* Cores per processor */
1647                         reserved2       :8,     /* Reserved */
1648                         ppid            :8,     /* Physical processor ID */
1649                         reserved1       :8;     /* Reserved */
1650         } overview_bits;
1651         u64 overview_data;
1652 } pal_log_overview_t;
1653
1654 typedef union pal_proc_n_log_info1_u{
1655         struct {
1656                 u64     tid             :16,    /* Thread id */
1657                         reserved2       :16,    /* Reserved */
1658                         cid             :16,    /* Core id */
1659                         reserved1       :16;    /* Reserved */
1660         } ppli1_bits;
1661         u64     ppli1_data;
1662 } pal_proc_n_log_info1_t;
1663
1664 typedef union pal_proc_n_log_info2_u {
1665         struct {
1666                 u64     la              :16,    /* Logical address */
1667                         reserved        :48;    /* Reserved */
1668         } ppli2_bits;
1669         u64     ppli2_data;
1670 } pal_proc_n_log_info2_t;
1671
1672 typedef struct pal_logical_to_physical_s
1673 {
1674         pal_log_overview_t overview;
1675         pal_proc_n_log_info1_t ppli1;
1676         pal_proc_n_log_info2_t ppli2;
1677 } pal_logical_to_physical_t;
1678
1679 #define overview_num_log        overview.overview_bits.num_log
1680 #define overview_tpc            overview.overview_bits.tpc
1681 #define overview_cpp            overview.overview_bits.cpp
1682 #define overview_ppid           overview.overview_bits.ppid
1683 #define log1_tid                ppli1.ppli1_bits.tid
1684 #define log1_cid                ppli1.ppli1_bits.cid
1685 #define log2_la                 ppli2.ppli2_bits.la
1686
1687 /* Get information on logical to physical processor mappings. */
1688 static inline s64
1689 ia64_pal_logical_to_phys(u64 proc_number, pal_logical_to_physical_t *mapping)
1690 {
1691         struct ia64_pal_retval iprv;
1692
1693         PAL_CALL(iprv, PAL_LOGICAL_TO_PHYSICAL, proc_number, 0, 0);
1694
1695         if (iprv.status == PAL_STATUS_SUCCESS)
1696         {
1697                 mapping->overview.overview_data = iprv.v0;
1698                 mapping->ppli1.ppli1_data = iprv.v1;
1699                 mapping->ppli2.ppli2_data = iprv.v2;
1700         }
1701
1702         return iprv.status;
1703 }
1704
1705 typedef struct pal_cache_shared_info_s
1706 {
1707         u64 num_shared;
1708         pal_proc_n_log_info1_t ppli1;
1709         pal_proc_n_log_info2_t ppli2;
1710 } pal_cache_shared_info_t;
1711
1712 /* Get information on logical to physical processor mappings. */
1713 static inline s64
1714 ia64_pal_cache_shared_info(u64 level,
1715                 u64 type,
1716                 u64 proc_number,
1717                 pal_cache_shared_info_t *info)
1718 {
1719         struct ia64_pal_retval iprv;
1720
1721         PAL_CALL(iprv, PAL_CACHE_SHARED_INFO, level, type, proc_number);
1722
1723         if (iprv.status == PAL_STATUS_SUCCESS) {
1724                 info->num_shared = iprv.v0;
1725                 info->ppli1.ppli1_data = iprv.v1;
1726                 info->ppli2.ppli2_data = iprv.v2;
1727         }
1728
1729         return iprv.status;
1730 }
1731 #endif /* __ASSEMBLY__ */
1732
1733 #endif /* _ASM_IA64_PAL_H */