include/asm-ia64/pal.h

   1 #ifndef _ASM_IA64_PAL_H
   2 #define _ASM_IA64_PAL_H
   3
   4 /*
   5  * Processor Abstraction Layer definitions.
   6  *
   7  * This is based on Intel IA-64 Architecture Software Developer's Manual rev 1.0
   8  * chapter 11 IA-64 Processor Abstraction Layer
   9  *
  10  * Copyright (C) 1998-2001 Hewlett-Packard Co
  11  *      David Mosberger-Tang <davidm@hpl.hp.com>
  12  *      Stephane Eranian <eranian@hpl.hp.com>
  13  * Copyright (C) 1999 VA Linux Systems
  14  * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
  15  * Copyright (C) 1999 Srinivasa Prasad Thirumalachar <sprasad@sprasad.engr.sgi.com>
  16  *
  17  * 99/10/01     davidm  Make sure we pass zero for reserved parameters.
  18  * 00/03/07     davidm  Updated pal_cache_flush() to be in sync with PAL v2.6.
  19  * 00/03/23     cfleck  Modified processor min-state save area to match updated PAL & SAL info
  20  * 00/05/24     eranian Updated to latest PAL spec, fix structures bugs, added
  21  * 00/05/25     eranian Support for stack calls, and static physical calls
  22  * 00/06/18     eranian Support for stacked physical calls
  23  */
  24
  25 /*
  26  * Note that some of these calls use a static-register only calling
  27  * convention which has nothing to do with the regular calling
  28  * convention.
  29  */
  30 #define PAL_CACHE_FLUSH         1       /* flush i/d cache */
  31 #define PAL_CACHE_INFO          2       /* get detailed i/d cache info */
  32 #define PAL_CACHE_INIT          3       /* initialize i/d cache */
  33 #define PAL_CACHE_SUMMARY       4       /* get summary of cache heirarchy */
  34 #define PAL_MEM_ATTRIB          5       /* list supported memory attributes */
  35 #define PAL_PTCE_INFO           6       /* purge TLB info */
  36 #define PAL_VM_INFO             7       /* return supported virtual memory features */
  37 #define PAL_VM_SUMMARY          8       /* return summary on supported vm features */
  38 #define PAL_BUS_GET_FEATURES    9       /* return processor bus interface features settings */
  39 #define PAL_BUS_SET_FEATURES    10      /* set processor bus features */
  40 #define PAL_DEBUG_INFO          11      /* get number of debug registers */
  41 #define PAL_FIXED_ADDR          12      /* get fixed component of processors's directed address */
  42 #define PAL_FREQ_BASE           13      /* base frequency of the platform */
  43 #define PAL_FREQ_RATIOS         14      /* ratio of processor, bus and ITC frequency */
  44 #define PAL_PERF_MON_INFO       15      /* return performance monitor info */
  45 #define PAL_PLATFORM_ADDR       16      /* set processor interrupt block and IO port space addr */
  46 #define PAL_PROC_GET_FEATURES   17      /* get configurable processor features & settings */
  47 #define PAL_PROC_SET_FEATURES   18      /* enable/disable configurable processor features */
  48 #define PAL_RSE_INFO            19      /* return rse information */
  49 #define PAL_VERSION             20      /* return version of PAL code */
  50 #define PAL_MC_CLEAR_LOG        21      /* clear all processor log info */
  51 #define PAL_MC_DRAIN            22      /* drain operations which could result in an MCA */
  52 #define PAL_MC_EXPECTED         23      /* set/reset expected MCA indicator */
  53 #define PAL_MC_DYNAMIC_STATE    24      /* get processor dynamic state */
  54 #define PAL_MC_ERROR_INFO       25      /* get processor MCA info and static state */
  55 #define PAL_MC_RESUME           26      /* Return to interrupted process */
  56 #define PAL_MC_REGISTER_MEM     27      /* Register memory for PAL to use during MCAs and inits */
  57 #define PAL_HALT                28      /* enter the low power HALT state */
  58 #define PAL_HALT_LIGHT          29      /* enter the low power light halt state*/
  59 #define PAL_COPY_INFO           30      /* returns info needed to relocate PAL */
  60 #define PAL_CACHE_LINE_INIT     31      /* init tags & data of cache line */
  61 #define PAL_PMI_ENTRYPOINT      32      /* register PMI memory entry points with the processor */
  62 #define PAL_ENTER_IA_32_ENV     33      /* enter IA-32 system environment */
  63 #define PAL_VM_PAGE_SIZE        34      /* return vm TC and page walker page sizes */
  64
  65 #define PAL_MEM_FOR_TEST        37      /* get amount of memory needed for late processor test */
  66 #define PAL_CACHE_PROT_INFO     38      /* get i/d cache protection info */
  67 #define PAL_REGISTER_INFO       39      /* return AR and CR register information*/
  68 #define PAL_SHUTDOWN            40      /* enter processor shutdown state */
  69 #define PAL_PREFETCH_VISIBILITY 41      /* Make Processor Prefetches Visible */
  70 #define PAL_LOGICAL_TO_PHYSICAL 42      /* returns information on logical to physical processor mapping */
  71 #define PAL_CACHE_SHARED_INFO   43      /* returns information on caches shared by logical processor */
  72
  73 #define PAL_COPY_PAL            256     /* relocate PAL procedures and PAL PMI */
  74 #define PAL_HALT_INFO           257     /* return the low power capabilities of processor */
  75 #define PAL_TEST_PROC           258     /* perform late processor self-test */
  76 #define PAL_CACHE_READ          259     /* read tag & data of cacheline for diagnostic testing */
  77 #define PAL_CACHE_WRITE         260     /* write tag & data of cacheline for diagnostic testing */
  78 #define PAL_VM_TR_READ          261     /* read contents of translation register */
  79 #define PAL_GET_PSTATE          262     /* get the current P-state */
  80 #define PAL_SET_PSTATE          263     /* set the P-state */
  81 #define PAL_BRAND_INFO          274     /* Processor branding information */
  82
  83 #ifndef __ASSEMBLY__
  84
  85 #include <linux/types.h>
  86 #include <asm/fpu.h>
  87
  88 /*
  89  * Data types needed to pass information into PAL procedures and
  90  * interpret information returned by them.
  91  */
  92
  93 /* Return status from the PAL procedure */
  94 typedef s64                             pal_status_t;
  95
  96 #define PAL_STATUS_SUCCESS              0       /* No error */
  97 #define PAL_STATUS_UNIMPLEMENTED        (-1)    /* Unimplemented procedure */
  98 #define PAL_STATUS_EINVAL               (-2)    /* Invalid argument */
  99 #define PAL_STATUS_ERROR                (-3)    /* Error */
 100 #define PAL_STATUS_CACHE_INIT_FAIL      (-4)    /* Could not initialize the
 101                                                  * specified level and type of
 102                                                  * cache without sideeffects
 103                                                  * and "restrict" was 1
 104                                                  */
 105
 106 /* Processor cache level in the heirarchy */
 107 typedef u64                             pal_cache_level_t;
 108 #define PAL_CACHE_LEVEL_L0              0       /* L0 */
 109 #define PAL_CACHE_LEVEL_L1              1       /* L1 */
 110 #define PAL_CACHE_LEVEL_L2              2       /* L2 */
 111
 112
 113 /* Processor cache type at a particular level in the heirarchy */
 114
 115 typedef u64                             pal_cache_type_t;
 116 #define PAL_CACHE_TYPE_INSTRUCTION      1       /* Instruction cache */
 117 #define PAL_CACHE_TYPE_DATA             2       /* Data or unified cache */
 118 #define PAL_CACHE_TYPE_INSTRUCTION_DATA 3       /* Both Data & Instruction */
 119
 120
 121 #define PAL_CACHE_FLUSH_INVALIDATE      1       /* Invalidate clean lines */
 122 #define PAL_CACHE_FLUSH_CHK_INTRS       2       /* check for interrupts/mc while flushing */
 123
 124 /* Processor cache line size in bytes  */
 125 typedef int                             pal_cache_line_size_t;
 126
 127 /* Processor cache line state */
 128 typedef u64                             pal_cache_line_state_t;
 129 #define PAL_CACHE_LINE_STATE_INVALID    0       /* Invalid */
 130 #define PAL_CACHE_LINE_STATE_SHARED     1       /* Shared */
 131 #define PAL_CACHE_LINE_STATE_EXCLUSIVE  2       /* Exclusive */
 132 #define PAL_CACHE_LINE_STATE_MODIFIED   3       /* Modified */
 133
 134 typedef struct pal_freq_ratio {
 135         u32 den, num;           /* numerator & denominator */
 136 } itc_ratio, proc_ratio;
 137
 138 typedef union  pal_cache_config_info_1_s {
 139         struct {
 140                 u64             u               : 1,    /* 0 Unified cache ? */
 141                                 at              : 2,    /* 2-1 Cache mem attr*/
 142                                 reserved        : 5,    /* 7-3 Reserved */
 143                                 associativity   : 8,    /* 16-8 Associativity*/
 144                                 line_size       : 8,    /* 23-17 Line size */
 145                                 stride          : 8,    /* 31-24 Stride */
 146                                 store_latency   : 8,    /*39-32 Store latency*/
 147                                 load_latency    : 8,    /* 47-40 Load latency*/
 148                                 store_hints     : 8,    /* 55-48 Store hints*/
 149                                 load_hints      : 8;    /* 63-56 Load hints */
 150         } pcci1_bits;
 151         u64                     pcci1_data;
 152 } pal_cache_config_info_1_t;
 153
 154 typedef union  pal_cache_config_info_2_s {
 155         struct {
 156                 u32             cache_size;             /*cache size in bytes*/
 157
 158
 159                 u32             alias_boundary  : 8,    /* 39-32 aliased addr
 160                                                          * separation for max
 161                                                          * performance.
 162                                                          */
 163                                 tag_ls_bit      : 8,    /* 47-40 LSb of addr*/
 164                                 tag_ms_bit      : 8,    /* 55-48 MSb of addr*/
 165                                 reserved        : 8;    /* 63-56 Reserved */
 166         } pcci2_bits;
 167         u64                     pcci2_data;
 168 } pal_cache_config_info_2_t;
 169
 170
 171 typedef struct pal_cache_config_info_s {
 172         pal_status_t                    pcci_status;
 173         pal_cache_config_info_1_t       pcci_info_1;
 174         pal_cache_config_info_2_t       pcci_info_2;
 175         u64                             pcci_reserved;
 176 } pal_cache_config_info_t;
 177
 178 #define pcci_ld_hints           pcci_info_1.pcci1_bits.load_hints
 179 #define pcci_st_hints           pcci_info_1.pcci1_bits.store_hints
 180 #define pcci_ld_latency         pcci_info_1.pcci1_bits.load_latency
 181 #define pcci_st_latency         pcci_info_1.pcci1_bits.store_latency
 182 #define pcci_stride             pcci_info_1.pcci1_bits.stride
 183 #define pcci_line_size          pcci_info_1.pcci1_bits.line_size
 184 #define pcci_assoc              pcci_info_1.pcci1_bits.associativity
 185 #define pcci_cache_attr         pcci_info_1.pcci1_bits.at
 186 #define pcci_unified            pcci_info_1.pcci1_bits.u
 187 #define pcci_tag_msb            pcci_info_2.pcci2_bits.tag_ms_bit
 188 #define pcci_tag_lsb            pcci_info_2.pcci2_bits.tag_ls_bit
 189 #define pcci_alias_boundary     pcci_info_2.pcci2_bits.alias_boundary
 190 #define pcci_cache_size         pcci_info_2.pcci2_bits.cache_size
 191
 192
 193
 194 /* Possible values for cache attributes */
 195
 196 #define PAL_CACHE_ATTR_WT               0       /* Write through cache */
 197 #define PAL_CACHE_ATTR_WB               1       /* Write back cache */
 198 #define PAL_CACHE_ATTR_WT_OR_WB         2       /* Either write thru or write
 199                                                  * back depending on TLB
 200                                                  * memory attributes
 201                                                  */
 202
 203
 204 /* Possible values for cache hints */
 205
 206 #define PAL_CACHE_HINT_TEMP_1           0       /* Temporal level 1 */
 207 #define PAL_CACHE_HINT_NTEMP_1          1       /* Non-temporal level 1 */
 208 #define PAL_CACHE_HINT_NTEMP_ALL        3       /* Non-temporal all levels */
 209
 210 /* Processor cache protection  information */
 211 typedef union pal_cache_protection_element_u {
 212         u32                     pcpi_data;
 213         struct {
 214                 u32             data_bits       : 8, /* # data bits covered by
 215                                                       * each unit of protection
 216                                                       */
 217
 218                                 tagprot_lsb     : 6, /* Least -do- */
 219                                 tagprot_msb     : 6, /* Most Sig. tag address
 220                                                       * bit that this
 221                                                       * protection covers.
 222                                                       */
 223                                 prot_bits       : 6, /* # of protection bits */
 224                                 method          : 4, /* Protection method */
 225                                 t_d             : 2; /* Indicates which part
 226                                                       * of the cache this
 227                                                       * protection encoding
 228                                                       * applies.
 229                                                       */
 230         } pcp_info;
 231 } pal_cache_protection_element_t;
 232
 233 #define pcpi_cache_prot_part    pcp_info.t_d
 234 #define pcpi_prot_method        pcp_info.method
 235 #define pcpi_prot_bits          pcp_info.prot_bits
 236 #define pcpi_tagprot_msb        pcp_info.tagprot_msb
 237 #define pcpi_tagprot_lsb        pcp_info.tagprot_lsb
 238 #define pcpi_data_bits          pcp_info.data_bits
 239
 240 /* Processor cache part encodings */
 241 #define PAL_CACHE_PROT_PART_DATA        0       /* Data protection  */
 242 #define PAL_CACHE_PROT_PART_TAG         1       /* Tag  protection */
 243 #define PAL_CACHE_PROT_PART_TAG_DATA    2       /* Tag+data protection (tag is
 244                                                  * more significant )
 245                                                  */
 246 #define PAL_CACHE_PROT_PART_DATA_TAG    3       /* Data+tag protection (data is
 247                                                  * more significant )
 248                                                  */
 249 #define PAL_CACHE_PROT_PART_MAX         6
 250
 251
 252 typedef struct pal_cache_protection_info_s {
 253         pal_status_t                    pcpi_status;
 254         pal_cache_protection_element_t  pcp_info[PAL_CACHE_PROT_PART_MAX];
 255 } pal_cache_protection_info_t;
 256
 257
 258 /* Processor cache protection method encodings */
 259 #define PAL_CACHE_PROT_METHOD_NONE              0       /* No protection */
 260 #define PAL_CACHE_PROT_METHOD_ODD_PARITY        1       /* Odd parity */
 261 #define PAL_CACHE_PROT_METHOD_EVEN_PARITY       2       /* Even parity */
 262 #define PAL_CACHE_PROT_METHOD_ECC               3       /* ECC protection */
 263
 264
 265 /* Processor cache line identification in the heirarchy */
 266 typedef union pal_cache_line_id_u {
 267         u64                     pclid_data;
 268         struct {
 269                 u64             cache_type      : 8,    /* 7-0 cache type */
 270                                 level           : 8,    /* 15-8 level of the
 271                                                          * cache in the
 272                                                          * heirarchy.
 273                                                          */
 274                                 way             : 8,    /* 23-16 way in the set
 275                                                          */
 276                                 part            : 8,    /* 31-24 part of the
 277                                                          * cache
 278                                                          */
 279                                 reserved        : 32;   /* 63-32 is reserved*/
 280         } pclid_info_read;
 281         struct {
 282                 u64             cache_type      : 8,    /* 7-0 cache type */
 283                                 level           : 8,    /* 15-8 level of the
 284                                                          * cache in the
 285                                                          * heirarchy.
 286                                                          */
 287                                 way             : 8,    /* 23-16 way in the set
 288                                                          */
 289                                 part            : 8,    /* 31-24 part of the
 290                                                          * cache
 291                                                          */
 292                                 mesi            : 8,    /* 39-32 cache line
 293                                                          * state
 294                                                          */
 295                                 start           : 8,    /* 47-40 lsb of data to
 296                                                          * invert
 297                                                          */
 298                                 length          : 8,    /* 55-48 #bits to
 299                                                          * invert
 300                                                          */
 301                                 trigger         : 8;    /* 63-56 Trigger error
 302                                                          * by doing a load
 303                                                          * after the write
 304                                                          */
 305
 306         } pclid_info_write;
 307 } pal_cache_line_id_u_t;
 308
 309 #define pclid_read_part         pclid_info_read.part
 310 #define pclid_read_way          pclid_info_read.way
 311 #define pclid_read_level        pclid_info_read.level
 312 #define pclid_read_cache_type   pclid_info_read.cache_type
 313
 314 #define pclid_write_trigger     pclid_info_write.trigger
 315 #define pclid_write_length      pclid_info_write.length
 316 #define pclid_write_start       pclid_info_write.start
 317 #define pclid_write_mesi        pclid_info_write.mesi
 318 #define pclid_write_part        pclid_info_write.part
 319 #define pclid_write_way         pclid_info_write.way
 320 #define pclid_write_level       pclid_info_write.level
 321 #define pclid_write_cache_type  pclid_info_write.cache_type
 322
 323 /* Processor cache line part encodings */
 324 #define PAL_CACHE_LINE_ID_PART_DATA             0       /* Data */
 325 #define PAL_CACHE_LINE_ID_PART_TAG              1       /* Tag */
 326 #define PAL_CACHE_LINE_ID_PART_DATA_PROT        2       /* Data protection */
 327 #define PAL_CACHE_LINE_ID_PART_TAG_PROT         3       /* Tag protection */
 328 #define PAL_CACHE_LINE_ID_PART_DATA_TAG_PROT    4       /* Data+tag
 329                                                          * protection
 330                                                          */
 331 typedef struct pal_cache_line_info_s {
 332         pal_status_t            pcli_status;            /* Return status of the read cache line
 333                                                          * info call.
 334                                                          */
 335         u64                     pcli_data;              /* 64-bit data, tag, protection bits .. */
 336         u64                     pcli_data_len;          /* data length in bits */
 337         pal_cache_line_state_t  pcli_cache_line_state;  /* mesi state */
 338
 339 } pal_cache_line_info_t;
 340
 341
 342 /* Machine Check related crap */
 343
 344 /* Pending event status bits  */
 345 typedef u64                                     pal_mc_pending_events_t;
 346
 347 #define PAL_MC_PENDING_MCA                      (1 << 0)
 348 #define PAL_MC_PENDING_INIT                     (1 << 1)
 349
 350 /* Error information type */
 351 typedef u64                                     pal_mc_info_index_t;
 352
 353 #define PAL_MC_INFO_PROCESSOR                   0       /* Processor */
 354 #define PAL_MC_INFO_CACHE_CHECK                 1       /* Cache check */
 355 #define PAL_MC_INFO_TLB_CHECK                   2       /* Tlb check */
 356 #define PAL_MC_INFO_BUS_CHECK                   3       /* Bus check */
 357 #define PAL_MC_INFO_REQ_ADDR                    4       /* Requestor address */
 358 #define PAL_MC_INFO_RESP_ADDR                   5       /* Responder address */
 359 #define PAL_MC_INFO_TARGET_ADDR                 6       /* Target address */
 360 #define PAL_MC_INFO_IMPL_DEP                    7       /* Implementation
 361                                                          * dependent
 362                                                          */
 363
 364
 365 typedef struct pal_process_state_info_s {
 366         u64             reserved1       : 2,
 367                         rz              : 1,    /* PAL_CHECK processor
 368                                                  * rendezvous
 369                                                  * successful.
 370                                                  */
 371
 372                         ra              : 1,    /* PAL_CHECK attempted
 373                                                  * a rendezvous.
 374                                                  */
 375                         me              : 1,    /* Distinct multiple
 376                                                  * errors occurred
 377                                                  */
 378
 379                         mn              : 1,    /* Min. state save
 380                                                  * area has been
 381                                                  * registered with PAL
 382                                                  */
 383
 384                         sy              : 1,    /* Storage integrity
 385                                                  * synched
 386                                                  */
 387
 388
 389                         co              : 1,    /* Continuable */
 390                         ci              : 1,    /* MC isolated */
 391                         us              : 1,    /* Uncontained storage
 392                                                  * damage.
 393                                                  */
 394
 395
 396                         hd              : 1,    /* Non-essential hw
 397                                                  * lost (no loss of
 398                                                  * functionality)
 399                                                  * causing the
 400                                                  * processor to run in
 401                                                  * degraded mode.
 402                                                  */
 403
 404                         tl              : 1,    /* 1 => MC occurred
 405                                                  * after an instr was
 406                                                  * executed but before
 407                                                  * the trap that
 408                                                  * resulted from instr
 409                                                  * execution was
 410                                                  * generated.
 411                                                  * (Trap Lost )
 412                                                  */
 413                         mi              : 1,    /* More information available
 414                                                  * call PAL_MC_ERROR_INFO
 415                                                  */
 416                         pi              : 1,    /* Precise instruction pointer */
 417                         pm              : 1,    /* Precise min-state save area */
 418
 419                         dy              : 1,    /* Processor dynamic
 420                                                  * state valid
 421                                                  */
 422
 423
 424                         in              : 1,    /* 0 = MC, 1 = INIT */
 425                         rs              : 1,    /* RSE valid */
 426                         cm              : 1,    /* MC corrected */
 427                         ex              : 1,    /* MC is expected */
 428                         cr              : 1,    /* Control regs valid*/
 429                         pc              : 1,    /* Perf cntrs valid */
 430                         dr              : 1,    /* Debug regs valid */
 431                         tr              : 1,    /* Translation regs
 432                                                  * valid
 433                                                  */
 434                         rr              : 1,    /* Region regs valid */
 435                         ar              : 1,    /* App regs valid */
 436                         br              : 1,    /* Branch regs valid */
 437                         pr              : 1,    /* Predicate registers
 438                                                  * valid
 439                                                  */
 440
 441                         fp              : 1,    /* fp registers valid*/
 442                         b1              : 1,    /* Preserved bank one
 443                                                  * general registers
 444                                                  * are valid
 445                                                  */
 446                         b0              : 1,    /* Preserved bank zero
 447                                                  * general registers
 448                                                  * are valid
 449                                                  */
 450                         gr              : 1,    /* General registers
 451                                                  * are valid
 452                                                  * (excl. banked regs)
 453                                                  */
 454                         dsize           : 16,   /* size of dynamic
 455                                                  * state returned
 456                                                  * by the processor
 457                                                  */
 458
 459                         se              : 1,    /* Shared error.  MCA in a
 460                                                    shared structure */
 461                         reserved2       : 10,
 462                         cc              : 1,    /* Cache check */
 463                         tc              : 1,    /* TLB check */
 464                         bc              : 1,    /* Bus check */
 465                         rc              : 1,    /* Register file check */
 466                         uc              : 1;    /* Uarch check */
 467
 468 } pal_processor_state_info_t;
 469
 470 typedef struct pal_cache_check_info_s {
 471         u64             op              : 4,    /* Type of cache
 472                                                  * operation that
 473                                                  * caused the machine
 474                                                  * check.
 475                                                  */
 476                         level           : 2,    /* Cache level */
 477                         reserved1       : 2,
 478                         dl              : 1,    /* Failure in data part
 479                                                  * of cache line
 480                                                  */
 481                         tl              : 1,    /* Failure in tag part
 482                                                  * of cache line
 483                                                  */
 484                         dc              : 1,    /* Failure in dcache */
 485                         ic              : 1,    /* Failure in icache */
 486                         mesi            : 3,    /* Cache line state */
 487                         mv              : 1,    /* mesi valid */
 488                         way             : 5,    /* Way in which the
 489                                                  * error occurred
 490                                                  */
 491                         wiv             : 1,    /* Way field valid */
 492                         reserved2       : 1,
 493                         dp              : 1,    /* Data poisoned on MBE */
 494                         reserved3       : 8,
 495
 496                         index           : 20,   /* Cache line index */
 497                         reserved4       : 2,
 498
 499                         is              : 1,    /* instruction set (1 == ia32) */
 500                         iv              : 1,    /* instruction set field valid */
 501                         pl              : 2,    /* privilege level */
 502                         pv              : 1,    /* privilege level field valid */
 503                         mcc             : 1,    /* Machine check corrected */
 504                         tv              : 1,    /* Target address
 505                                                  * structure is valid
 506                                                  */
 507                         rq              : 1,    /* Requester identifier
 508                                                  * structure is valid
 509                                                  */
 510                         rp              : 1,    /* Responder identifier
 511                                                  * structure is valid
 512                                                  */
 513                         pi              : 1;    /* Precise instruction pointer
 514                                                  * structure is valid
 515                                                  */
 516 } pal_cache_check_info_t;
 517
 518 typedef struct pal_tlb_check_info_s {
 519
 520         u64             tr_slot         : 8,    /* Slot# of TR where
 521                                                  * error occurred
 522                                                  */
 523                         trv             : 1,    /* tr_slot field is valid */
 524                         reserved1       : 1,
 525                         level           : 2,    /* TLB level where failure occurred */
 526                         reserved2       : 4,
 527                         dtr             : 1,    /* Fail in data TR */
 528                         itr             : 1,    /* Fail in inst TR */
 529                         dtc             : 1,    /* Fail in data TC */
 530                         itc             : 1,    /* Fail in inst. TC */
 531                         op              : 4,    /* Cache operation */
 532                         reserved3       : 30,
 533
 534                         is              : 1,    /* instruction set (1 == ia32) */
 535                         iv              : 1,    /* instruction set field valid */
 536                         pl              : 2,    /* privilege level */
 537                         pv              : 1,    /* privilege level field valid */
 538                         mcc             : 1,    /* Machine check corrected */
 539                         tv              : 1,    /* Target address
 540                                                  * structure is valid
 541                                                  */
 542                         rq              : 1,    /* Requester identifier
 543                                                  * structure is valid
 544                                                  */
 545                         rp              : 1,    /* Responder identifier
 546                                                  * structure is valid
 547                                                  */
 548                         pi              : 1;    /* Precise instruction pointer
 549                                                  * structure is valid
 550                                                  */
 551 } pal_tlb_check_info_t;
 552
 553 typedef struct pal_bus_check_info_s {
 554         u64             size            : 5,    /* Xaction size */
 555                         ib              : 1,    /* Internal bus error */
 556                         eb              : 1,    /* External bus error */
 557                         cc              : 1,    /* Error occurred
 558                                                  * during cache-cache
 559                                                  * transfer.
 560                                                  */
 561                         type            : 8,    /* Bus xaction type*/
 562                         sev             : 5,    /* Bus error severity*/
 563                         hier            : 2,    /* Bus hierarchy level */
 564                         dp              : 1,    /* Data poisoned on MBE */
 565                         bsi             : 8,    /* Bus error status
 566                                                  * info
 567                                                  */
 568                         reserved2       : 22,
 569
 570                         is              : 1,    /* instruction set (1 == ia32) */
 571                         iv              : 1,    /* instruction set field valid */
 572                         pl              : 2,    /* privilege level */
 573                         pv              : 1,    /* privilege level field valid */
 574                         mcc             : 1,    /* Machine check corrected */
 575                         tv              : 1,    /* Target address
 576                                                  * structure is valid
 577                                                  */
 578                         rq              : 1,    /* Requester identifier
 579                                                  * structure is valid
 580                                                  */
 581                         rp              : 1,    /* Responder identifier
 582                                                  * structure is valid
 583                                                  */
 584                         pi              : 1;    /* Precise instruction pointer
 585                                                  * structure is valid
 586                                                  */
 587 } pal_bus_check_info_t;
 588
 589 typedef struct pal_reg_file_check_info_s {
 590         u64             id              : 4,    /* Register file identifier */
 591                         op              : 4,    /* Type of register
 592                                                  * operation that
 593                                                  * caused the machine
 594                                                  * check.
 595                                                  */
 596                         reg_num         : 7,    /* Register number */
 597                         rnv             : 1,    /* reg_num valid */
 598                         reserved2       : 38,
 599
 600                         is              : 1,    /* instruction set (1 == ia32) */
 601                         iv              : 1,    /* instruction set field valid */
 602                         pl              : 2,    /* privilege level */
 603                         pv              : 1,    /* privilege level field valid */
 604                         mcc             : 1,    /* Machine check corrected */
 605                         reserved3       : 3,
 606                         pi              : 1;    /* Precise instruction pointer
 607                                                  * structure is valid
 608                                                  */
 609 } pal_reg_file_check_info_t;
 610
 611 typedef struct pal_uarch_check_info_s {
 612         u64             sid             : 5,    /* Structure identification */
 613                         level           : 3,    /* Level of failure */
 614                         array_id        : 4,    /* Array identification */
 615                         op              : 4,    /* Type of
 616                                                  * operation that
 617                                                  * caused the machine
 618                                                  * check.
 619                                                  */
 620                         way             : 6,    /* Way of structure */
 621                         wv              : 1,    /* way valid */
 622                         xv              : 1,    /* index valid */
 623                         reserved1       : 8,
 624                         index           : 8,    /* Index or set of the uarch
 625                                                  * structure that failed.
 626                                                  */
 627                         reserved2       : 24,
 628
 629                         is              : 1,    /* instruction set (1 == ia32) */
 630                         iv              : 1,    /* instruction set field valid */
 631                         pl              : 2,    /* privilege level */
 632                         pv              : 1,    /* privilege level field valid */
 633                         mcc             : 1,    /* Machine check corrected */
 634                         tv              : 1,    /* Target address
 635                                                  * structure is valid
 636                                                  */
 637                         rq              : 1,    /* Requester identifier
 638                                                  * structure is valid
 639                                                  */
 640                         rp              : 1,    /* Responder identifier
 641                                                  * structure is valid
 642                                                  */
 643                         pi              : 1;    /* Precise instruction pointer
 644                                                  * structure is valid
 645                                                  */
 646 } pal_uarch_check_info_t;
 647
 648 typedef union pal_mc_error_info_u {
 649         u64                             pmei_data;
 650         pal_processor_state_info_t      pme_processor;
 651         pal_cache_check_info_t          pme_cache;
 652         pal_tlb_check_info_t            pme_tlb;
 653         pal_bus_check_info_t            pme_bus;
 654         pal_reg_file_check_info_t       pme_reg_file;
 655         pal_uarch_check_info_t          pme_uarch;
 656 } pal_mc_error_info_t;
 657
 658 #define pmci_proc_unknown_check                 pme_processor.uc
 659 #define pmci_proc_bus_check                     pme_processor.bc
 660 #define pmci_proc_tlb_check                     pme_processor.tc
 661 #define pmci_proc_cache_check                   pme_processor.cc
 662 #define pmci_proc_dynamic_state_size            pme_processor.dsize
 663 #define pmci_proc_gpr_valid                     pme_processor.gr
 664 #define pmci_proc_preserved_bank0_gpr_valid     pme_processor.b0
 665 #define pmci_proc_preserved_bank1_gpr_valid     pme_processor.b1
 666 #define pmci_proc_fp_valid                      pme_processor.fp
 667 #define pmci_proc_predicate_regs_valid          pme_processor.pr
 668 #define pmci_proc_branch_regs_valid             pme_processor.br
 669 #define pmci_proc_app_regs_valid                pme_processor.ar
 670 #define pmci_proc_region_regs_valid             pme_processor.rr
 671 #define pmci_proc_translation_regs_valid        pme_processor.tr
 672 #define pmci_proc_debug_regs_valid              pme_processor.dr
 673 #define pmci_proc_perf_counters_valid           pme_processor.pc
 674 #define pmci_proc_control_regs_valid            pme_processor.cr
 675 #define pmci_proc_machine_check_expected        pme_processor.ex
 676 #define pmci_proc_machine_check_corrected       pme_processor.cm
 677 #define pmci_proc_rse_valid                     pme_processor.rs
 678 #define pmci_proc_machine_check_or_init         pme_processor.in
 679 #define pmci_proc_dynamic_state_valid           pme_processor.dy
 680 #define pmci_proc_operation                     pme_processor.op
 681 #define pmci_proc_trap_lost                     pme_processor.tl
 682 #define pmci_proc_hardware_damage               pme_processor.hd
 683 #define pmci_proc_uncontained_storage_damage    pme_processor.us
 684 #define pmci_proc_machine_check_isolated        pme_processor.ci
 685 #define pmci_proc_continuable                   pme_processor.co
 686 #define pmci_proc_storage_intergrity_synced     pme_processor.sy
 687 #define pmci_proc_min_state_save_area_regd      pme_processor.mn
 688 #define pmci_proc_distinct_multiple_errors      pme_processor.me
 689 #define pmci_proc_pal_attempted_rendezvous      pme_processor.ra
 690 #define pmci_proc_pal_rendezvous_complete       pme_processor.rz
 691
 692
 693 #define pmci_cache_level                        pme_cache.level
 694 #define pmci_cache_line_state                   pme_cache.mesi
 695 #define pmci_cache_line_state_valid             pme_cache.mv
 696 #define pmci_cache_line_index                   pme_cache.index
 697 #define pmci_cache_instr_cache_fail             pme_cache.ic
 698 #define pmci_cache_data_cache_fail              pme_cache.dc
 699 #define pmci_cache_line_tag_fail                pme_cache.tl
 700 #define pmci_cache_line_data_fail               pme_cache.dl
 701 #define pmci_cache_operation                    pme_cache.op
 702 #define pmci_cache_way_valid                    pme_cache.wv
 703 #define pmci_cache_target_address_valid         pme_cache.tv
 704 #define pmci_cache_way                          pme_cache.way
 705 #define pmci_cache_mc                           pme_cache.mc
 706
 707 #define pmci_tlb_instr_translation_cache_fail   pme_tlb.itc
 708 #define pmci_tlb_data_translation_cache_fail    pme_tlb.dtc
 709 #define pmci_tlb_instr_translation_reg_fail     pme_tlb.itr
 710 #define pmci_tlb_data_translation_reg_fail      pme_tlb.dtr
 711 #define pmci_tlb_translation_reg_slot           pme_tlb.tr_slot
 712 #define pmci_tlb_mc                             pme_tlb.mc
 713
 714 #define pmci_bus_status_info                    pme_bus.bsi
 715 #define pmci_bus_req_address_valid              pme_bus.rq
 716 #define pmci_bus_resp_address_valid             pme_bus.rp
 717 #define pmci_bus_target_address_valid           pme_bus.tv
 718 #define pmci_bus_error_severity                 pme_bus.sev
 719 #define pmci_bus_transaction_type               pme_bus.type
 720 #define pmci_bus_cache_cache_transfer           pme_bus.cc
 721 #define pmci_bus_transaction_size               pme_bus.size
 722 #define pmci_bus_internal_error                 pme_bus.ib
 723 #define pmci_bus_external_error                 pme_bus.eb
 724 #define pmci_bus_mc                             pme_bus.mc
 725
 726 /*
 727  * NOTE: this min_state_save area struct only includes the 1KB
 728  * architectural state save area.  The other 3 KB is scratch space
 729  * for PAL.
 730  */
 731
 732 typedef struct pal_min_state_area_s {
 733         u64     pmsa_nat_bits;          /* nat bits for saved GRs  */
 734         u64     pmsa_gr[15];            /* GR1  - GR15             */
 735         u64     pmsa_bank0_gr[16];      /* GR16 - GR31             */
 736         u64     pmsa_bank1_gr[16];      /* GR16 - GR31             */
 737         u64     pmsa_pr;                /* predicate registers     */
 738         u64     pmsa_br0;               /* branch register 0       */
 739         u64     pmsa_rsc;               /* ar.rsc                  */
 740         u64     pmsa_iip;               /* cr.iip                  */
 741         u64     pmsa_ipsr;              /* cr.ipsr                 */
 742         u64     pmsa_ifs;               /* cr.ifs                  */
 743         u64     pmsa_xip;               /* previous iip            */
 744         u64     pmsa_xpsr;              /* previous psr            */
 745         u64     pmsa_xfs;               /* previous ifs            */
 746         u64     pmsa_br1;               /* branch register 1       */
 747         u64     pmsa_reserved[70];      /* pal_min_state_area should total to 1KB */
 748 } pal_min_state_area_t;
 749
 750
 751 struct ia64_pal_retval {
 752         /*
 753          * A zero status value indicates call completed without error.
 754          * A negative status value indicates reason of call failure.
 755          * A positive status value indicates success but an
 756          * informational value should be printed (e.g., "reboot for
 757          * change to take effect").
 758          */
 759         s64 status;
 760         u64 v0;
 761         u64 v1;
 762         u64 v2;
 763 };
 764
 765 /*
 766  * Note: Currently unused PAL arguments are generally labeled
 767  * "reserved" so the value specified in the PAL documentation
 768  * (generally 0) MUST be passed.  Reserved parameters are not optional
 769  * parameters.
 770  */
 771 extern struct ia64_pal_retval ia64_pal_call_static (u64, u64, u64, u64);
 772 extern struct ia64_pal_retval ia64_pal_call_stacked (u64, u64, u64, u64);
 773 extern struct ia64_pal_retval ia64_pal_call_phys_static (u64, u64, u64, u64);
 774 extern struct ia64_pal_retval ia64_pal_call_phys_stacked (u64, u64, u64, u64);
 775 extern void ia64_save_scratch_fpregs (struct ia64_fpreg *);
 776 extern void ia64_load_scratch_fpregs (struct ia64_fpreg *);
 777
 778 #define PAL_CALL(iprv,a0,a1,a2,a3) do {                 \
 779         struct ia64_fpreg fr[6];                        \
 780         ia64_save_scratch_fpregs(fr);                   \
 781         iprv = ia64_pal_call_static(a0, a1, a2, a3);    \
 782         ia64_load_scratch_fpregs(fr);                   \
 783 } while (0)
 784
 785 #define PAL_CALL_STK(iprv,a0,a1,a2,a3) do {             \
 786         struct ia64_fpreg fr[6];                        \
 787         ia64_save_scratch_fpregs(fr);                   \
 788         iprv = ia64_pal_call_stacked(a0, a1, a2, a3);   \
 789         ia64_load_scratch_fpregs(fr);                   \
 790 } while (0)
 791
 792 #define PAL_CALL_PHYS(iprv,a0,a1,a2,a3) do {                    \
 793         struct ia64_fpreg fr[6];                                \
 794         ia64_save_scratch_fpregs(fr);                           \
 795         iprv = ia64_pal_call_phys_static(a0, a1, a2, a3);       \
 796         ia64_load_scratch_fpregs(fr);                           \
 797 } while (0)
 798
 799 #define PAL_CALL_PHYS_STK(iprv,a0,a1,a2,a3) do {                \
 800         struct ia64_fpreg fr[6];                                \
 801         ia64_save_scratch_fpregs(fr);                           \
 802         iprv = ia64_pal_call_phys_stacked(a0, a1, a2, a3);      \
 803         ia64_load_scratch_fpregs(fr);                           \
 804 } while (0)
 805
 806 typedef int (*ia64_pal_handler) (u64, ...);
 807 extern ia64_pal_handler ia64_pal;
 808 extern void ia64_pal_handler_init (void *);
 809
 810 extern ia64_pal_handler ia64_pal;
 811
 812 extern pal_cache_config_info_t          l0d_cache_config_info;
 813 extern pal_cache_config_info_t          l0i_cache_config_info;
 814 extern pal_cache_config_info_t          l1_cache_config_info;
 815 extern pal_cache_config_info_t          l2_cache_config_info;
 816
 817 extern pal_cache_protection_info_t      l0d_cache_protection_info;
 818 extern pal_cache_protection_info_t      l0i_cache_protection_info;
 819 extern pal_cache_protection_info_t      l1_cache_protection_info;
 820 extern pal_cache_protection_info_t      l2_cache_protection_info;
 821
 822 extern pal_cache_config_info_t          pal_cache_config_info_get(pal_cache_level_t,
 823                                                                   pal_cache_type_t);
 824
 825 extern pal_cache_protection_info_t      pal_cache_protection_info_get(pal_cache_level_t,
 826                                                                       pal_cache_type_t);
 827
 828
 829 extern void                             pal_error(int);
 830
 831
 832 /* Useful wrappers for the current list of pal procedures */
 833
 834 typedef union pal_bus_features_u {
 835         u64     pal_bus_features_val;
 836         struct {
 837                 u64     pbf_reserved1                           :       29;
 838                 u64     pbf_req_bus_parking                     :       1;
 839                 u64     pbf_bus_lock_mask                       :       1;
 840                 u64     pbf_enable_half_xfer_rate               :       1;
 841                 u64     pbf_reserved2                           :       22;
 842                 u64     pbf_disable_xaction_queueing            :       1;
 843                 u64     pbf_disable_resp_err_check              :       1;
 844                 u64     pbf_disable_berr_check                  :       1;
 845                 u64     pbf_disable_bus_req_internal_err_signal :       1;
 846                 u64     pbf_disable_bus_req_berr_signal         :       1;
 847                 u64     pbf_disable_bus_init_event_check        :       1;
 848                 u64     pbf_disable_bus_init_event_signal       :       1;
 849                 u64     pbf_disable_bus_addr_err_check          :       1;
 850                 u64     pbf_disable_bus_addr_err_signal         :       1;
 851                 u64     pbf_disable_bus_data_err_check          :       1;
 852         } pal_bus_features_s;
 853 } pal_bus_features_u_t;
 854
 855 extern void pal_bus_features_print (u64);
 856
 857 /* Provide information about configurable processor bus features */
 858 static inline s64
 859 ia64_pal_bus_get_features (pal_bus_features_u_t *features_avail,
 860                            pal_bus_features_u_t *features_status,
 861                            pal_bus_features_u_t *features_control)
 862 {
 863         struct ia64_pal_retval iprv;
 864         PAL_CALL_PHYS(iprv, PAL_BUS_GET_FEATURES, 0, 0, 0);
 865         if (features_avail)
 866                 features_avail->pal_bus_features_val = iprv.v0;
 867         if (features_status)
 868                 features_status->pal_bus_features_val = iprv.v1;
 869         if (features_control)
 870                 features_control->pal_bus_features_val = iprv.v2;
 871         return iprv.status;
 872 }
 873
 874 /* Enables/disables specific processor bus features */
 875 static inline s64
 876 ia64_pal_bus_set_features (pal_bus_features_u_t feature_select)
 877 {
 878         struct ia64_pal_retval iprv;
 879         PAL_CALL_PHYS(iprv, PAL_BUS_SET_FEATURES, feature_select.pal_bus_features_val, 0, 0);
 880         return iprv.status;
 881 }
 882
 883 /* Get detailed cache information */
 884 static inline s64
 885 ia64_pal_cache_config_info (u64 cache_level, u64 cache_type, pal_cache_config_info_t *conf)
 886 {
 887         struct ia64_pal_retval iprv;
 888
 889         PAL_CALL(iprv, PAL_CACHE_INFO, cache_level, cache_type, 0);
 890
 891         if (iprv.status == 0) {
 892                 conf->pcci_status                 = iprv.status;
 893                 conf->pcci_info_1.pcci1_data      = iprv.v0;
 894                 conf->pcci_info_2.pcci2_data      = iprv.v1;
 895                 conf->pcci_reserved               = iprv.v2;
 896         }
 897         return iprv.status;
 898
 899 }
 900
 901 /* Get detailed cche protection information */
 902 static inline s64
 903 ia64_pal_cache_prot_info (u64 cache_level, u64 cache_type, pal_cache_protection_info_t *prot)
 904 {
 905         struct ia64_pal_retval iprv;
 906
 907         PAL_CALL(iprv, PAL_CACHE_PROT_INFO, cache_level, cache_type, 0);
 908
 909         if (iprv.status == 0) {
 910                 prot->pcpi_status           = iprv.status;
 911                 prot->pcp_info[0].pcpi_data = iprv.v0 & 0xffffffff;
 912                 prot->pcp_info[1].pcpi_data = iprv.v0 >> 32;
 913                 prot->pcp_info[2].pcpi_data = iprv.v1 & 0xffffffff;
 914                 prot->pcp_info[3].pcpi_data = iprv.v1 >> 32;
 915                 prot->pcp_info[4].pcpi_data = iprv.v2 & 0xffffffff;
 916                 prot->pcp_info[5].pcpi_data = iprv.v2 >> 32;
 917         }
 918         return iprv.status;
 919 }
 920
 921 /*
 922  * Flush the processor instruction or data caches.  *PROGRESS must be
 923  * initialized to zero before calling this for the first time..
 924  */
 925 static inline s64
 926 ia64_pal_cache_flush (u64 cache_type, u64 invalidate, u64 *progress, u64 *vector)
 927 {
 928         struct ia64_pal_retval iprv;
 929         PAL_CALL(iprv, PAL_CACHE_FLUSH, cache_type, invalidate, *progress);
 930         if (vector)
 931                 *vector = iprv.v0;
 932         *progress = iprv.v1;
 933         return iprv.status;
 934 }
 935
 936
 937 /* Initialize the processor controlled caches */
 938 static inline s64
 939 ia64_pal_cache_init (u64 level, u64 cache_type, u64 rest)
 940 {
 941         struct ia64_pal_retval iprv;
 942         PAL_CALL(iprv, PAL_CACHE_INIT, level, cache_type, rest);
 943         return iprv.status;
 944 }
 945
 946 /* Initialize the tags and data of a data or unified cache line of
 947  * processor controlled cache to known values without the availability
 948  * of backing memory.
 949  */
 950 static inline s64
 951 ia64_pal_cache_line_init (u64 physical_addr, u64 data_value)
 952 {
 953         struct ia64_pal_retval iprv;
 954         PAL_CALL(iprv, PAL_CACHE_LINE_INIT, physical_addr, data_value, 0);
 955         return iprv.status;
 956 }
 957
 958
 959 /* Read the data and tag of a processor controlled cache line for diags */
 960 static inline s64
 961 ia64_pal_cache_read (pal_cache_line_id_u_t line_id, u64 physical_addr)
 962 {
 963         struct ia64_pal_retval iprv;
 964         PAL_CALL_PHYS_STK(iprv, PAL_CACHE_READ, line_id.pclid_data,
 965                                 physical_addr, 0);
 966         return iprv.status;
 967 }
 968
 969 /* Return summary information about the heirarchy of caches controlled by the processor */
 970 static inline s64
 971 ia64_pal_cache_summary (u64 *cache_levels, u64 *unique_caches)
 972 {
 973         struct ia64_pal_retval iprv;
 974         PAL_CALL(iprv, PAL_CACHE_SUMMARY, 0, 0, 0);
 975         if (cache_levels)
 976                 *cache_levels = iprv.v0;
 977         if (unique_caches)
 978                 *unique_caches = iprv.v1;
 979         return iprv.status;
 980 }
 981
 982 /* Write the data and tag of a processor-controlled cache line for diags */
 983 static inline s64
 984 ia64_pal_cache_write (pal_cache_line_id_u_t line_id, u64 physical_addr, u64 data)
 985 {
 986         struct ia64_pal_retval iprv;
 987         PAL_CALL_PHYS_STK(iprv, PAL_CACHE_WRITE, line_id.pclid_data,
 988                                 physical_addr, data);
 989         return iprv.status;
 990 }
 991
 992
 993 /* Return the parameters needed to copy relocatable PAL procedures from ROM to memory */
 994 static inline s64
 995 ia64_pal_copy_info (u64 copy_type, u64 num_procs, u64 num_iopics,
 996                     u64 *buffer_size, u64 *buffer_align)
 997 {
 998         struct ia64_pal_retval iprv;
 999         PAL_CALL(iprv, PAL_COPY_INFO, copy_type, num_procs, num_iopics);
1000         if (buffer_size)
1001                 *buffer_size = iprv.v0;
1002         if (buffer_align)
1003                 *buffer_align = iprv.v1;
1004         return iprv.status;
1005 }
1006
1007 /* Copy relocatable PAL procedures from ROM to memory */
1008 static inline s64
1009 ia64_pal_copy_pal (u64 target_addr, u64 alloc_size, u64 processor, u64 *pal_proc_offset)
1010 {
1011         struct ia64_pal_retval iprv;
1012         PAL_CALL(iprv, PAL_COPY_PAL, target_addr, alloc_size, processor);
1013         if (pal_proc_offset)
1014                 *pal_proc_offset = iprv.v0;
1015         return iprv.status;
1016 }
1017
1018 /* Return the number of instruction and data debug register pairs */
1019 static inline s64
1020 ia64_pal_debug_info (u64 *inst_regs,  u64 *data_regs)
1021 {
1022         struct ia64_pal_retval iprv;
1023         PAL_CALL(iprv, PAL_DEBUG_INFO, 0, 0, 0);
1024         if (inst_regs)
1025                 *inst_regs = iprv.v0;
1026         if (data_regs)
1027                 *data_regs = iprv.v1;
1028
1029         return iprv.status;
1030 }
1031
1032 #ifdef TBD
1033 /* Switch from IA64-system environment to IA-32 system environment */
1034 static inline s64
1035 ia64_pal_enter_ia32_env (ia32_env1, ia32_env2, ia32_env3)
1036 {
1037         struct ia64_pal_retval iprv;
1038         PAL_CALL(iprv, PAL_ENTER_IA_32_ENV, ia32_env1, ia32_env2, ia32_env3);
1039         return iprv.status;
1040 }
1041 #endif
1042
1043 /* Get unique geographical address of this processor on its bus */
1044 static inline s64
1045 ia64_pal_fixed_addr (u64 *global_unique_addr)
1046 {
1047         struct ia64_pal_retval iprv;
1048         PAL_CALL(iprv, PAL_FIXED_ADDR, 0, 0, 0);
1049         if (global_unique_addr)
1050                 *global_unique_addr = iprv.v0;
1051         return iprv.status;
1052 }
1053
1054 /* Get base frequency of the platform if generated by the processor */
1055 static inline s64
1056 ia64_pal_freq_base (u64 *platform_base_freq)
1057 {
1058         struct ia64_pal_retval iprv;
1059         PAL_CALL(iprv, PAL_FREQ_BASE, 0, 0, 0);
1060         if (platform_base_freq)
1061                 *platform_base_freq = iprv.v0;
1062         return iprv.status;
1063 }
1064
1065 /*
1066  * Get the ratios for processor frequency, bus frequency and interval timer to
1067  * to base frequency of the platform
1068  */
1069 static inline s64
1070 ia64_pal_freq_ratios (struct pal_freq_ratio *proc_ratio, struct pal_freq_ratio *bus_ratio,
1071                       struct pal_freq_ratio *itc_ratio)
1072 {
1073         struct ia64_pal_retval iprv;
1074         PAL_CALL(iprv, PAL_FREQ_RATIOS, 0, 0, 0);
1075         if (proc_ratio)
1076                 *(u64 *)proc_ratio = iprv.v0;
1077         if (bus_ratio)
1078                 *(u64 *)bus_ratio = iprv.v1;
1079         if (itc_ratio)
1080                 *(u64 *)itc_ratio = iprv.v2;
1081         return iprv.status;
1082 }
1083
1084 /* Make the processor enter HALT or one of the implementation dependent low
1085  * power states where prefetching and execution are suspended and cache and
1086  * TLB coherency is not maintained.
1087  */
1088 static inline s64
1089 ia64_pal_halt (u64 halt_state)
1090 {
1091         struct ia64_pal_retval iprv;
1092         PAL_CALL(iprv, PAL_HALT, halt_state, 0, 0);
1093         return iprv.status;
1094 }
1095
1096 typedef union pal_power_mgmt_info_u {
1097         u64                     ppmi_data;
1098         struct {
1099                u64              exit_latency            : 16,
1100                                 entry_latency           : 16,
1101                                 power_consumption       : 28,
1102                                 im                      : 1,
1103                                 co                      : 1,
1104                                 reserved                : 2;
1105         } pal_power_mgmt_info_s;
1106 } pal_power_mgmt_info_u_t;
1107
1108 /* Return information about processor's optional power management capabilities. */
1109 static inline s64
1110 ia64_pal_halt_info (pal_power_mgmt_info_u_t *power_buf)
1111 {
1112         struct ia64_pal_retval iprv;
1113         PAL_CALL_STK(iprv, PAL_HALT_INFO, (unsigned long) power_buf, 0, 0);
1114         return iprv.status;
1115 }
1116
1117 /* Get the current P-state information */
1118 static inline s64
1119 ia64_pal_get_pstate (u64 *pstate_index)
1120 {
1121         struct ia64_pal_retval iprv;
1122         PAL_CALL_STK(iprv, PAL_GET_PSTATE, 0, 0, 0);
1123         *pstate_index = iprv.v0;
1124         return iprv.status;
1125 }
1126
1127 /* Set the P-state */
1128 static inline s64
1129 ia64_pal_set_pstate (u64 pstate_index)
1130 {
1131         struct ia64_pal_retval iprv;
1132         PAL_CALL_STK(iprv, PAL_SET_PSTATE, pstate_index, 0, 0);
1133         return iprv.status;
1134 }
1135
1136 /* Processor branding information*/
1137 static inline s64
1138 ia64_pal_get_brand_info (char *brand_info)
1139 {
1140         struct ia64_pal_retval iprv;
1141         PAL_CALL_STK(iprv, PAL_BRAND_INFO, 0, (u64)brand_info, 0);
1142         return iprv.status;
1143 }
1144
1145 /* Cause the processor to enter LIGHT HALT state, where prefetching and execution are
1146  * suspended, but cache and TLB coherency is maintained.
1147  */
1148 static inline s64
1149 ia64_pal_halt_light (void)
1150 {
1151         struct ia64_pal_retval iprv;
1152         PAL_CALL(iprv, PAL_HALT_LIGHT, 0, 0, 0);
1153         return iprv.status;
1154 }
1155
1156 /* Clear all the processor error logging   registers and reset the indicator that allows
1157  * the error logging registers to be written. This procedure also checks the pending
1158  * machine check bit and pending INIT bit and reports their states.
1159  */
1160 static inline s64
1161 ia64_pal_mc_clear_log (u64 *pending_vector)
1162 {
1163         struct ia64_pal_retval iprv;
1164         PAL_CALL(iprv, PAL_MC_CLEAR_LOG, 0, 0, 0);
1165         if (pending_vector)
1166                 *pending_vector = iprv.v0;
1167         return iprv.status;
1168 }
1169
1170 /* Ensure that all outstanding transactions in a processor are completed or that any
1171  * MCA due to thes outstanding transaction is taken.
1172  */
1173 static inline s64
1174 ia64_pal_mc_drain (void)
1175 {
1176         struct ia64_pal_retval iprv;
1177         PAL_CALL(iprv, PAL_MC_DRAIN, 0, 0, 0);
1178         return iprv.status;
1179 }
1180
1181 /* Return the machine check dynamic processor state */
1182 static inline s64
1183 ia64_pal_mc_dynamic_state (u64 offset, u64 *size, u64 *pds)
1184 {
1185         struct ia64_pal_retval iprv;
1186         PAL_CALL(iprv, PAL_MC_DYNAMIC_STATE, offset, 0, 0);
1187         if (size)
1188                 *size = iprv.v0;
1189         if (pds)
1190                 *pds = iprv.v1;
1191         return iprv.status;
1192 }
1193
1194 /* Return processor machine check information */
1195 static inline s64
1196 ia64_pal_mc_error_info (u64 info_index, u64 type_index, u64 *size, u64 *error_info)
1197 {
1198         struct ia64_pal_retval iprv;
1199         PAL_CALL(iprv, PAL_MC_ERROR_INFO, info_index, type_index, 0);
1200         if (size)
1201                 *size = iprv.v0;
1202         if (error_info)
1203                 *error_info = iprv.v1;
1204         return iprv.status;
1205 }
1206
1207 /* Inform PALE_CHECK whether a machine check is expected so that PALE_CHECK willnot
1208  * attempt to correct any expected machine checks.
1209  */
1210 static inline s64
1211 ia64_pal_mc_expected (u64 expected, u64 *previous)
1212 {
1213         struct ia64_pal_retval iprv;
1214         PAL_CALL(iprv, PAL_MC_EXPECTED, expected, 0, 0);
1215         if (previous)
1216                 *previous = iprv.v0;
1217         return iprv.status;
1218 }
1219
1220 /* Register a platform dependent location with PAL to which it can save
1221  * minimal processor state in the event of a machine check or initialization
1222  * event.
1223  */
1224 static inline s64
1225 ia64_pal_mc_register_mem (u64 physical_addr)
1226 {
1227         struct ia64_pal_retval iprv;
1228         PAL_CALL(iprv, PAL_MC_REGISTER_MEM, physical_addr, 0, 0);
1229         return iprv.status;
1230 }
1231
1232 /* Restore minimal architectural processor state, set CMC interrupt if necessary
1233  * and resume execution
1234  */
1235 static inline s64
1236 ia64_pal_mc_resume (u64 set_cmci, u64 save_ptr)
1237 {
1238         struct ia64_pal_retval iprv;
1239         PAL_CALL(iprv, PAL_MC_RESUME, set_cmci, save_ptr, 0);
1240         return iprv.status;
1241 }
1242
1243 /* Return the memory attributes implemented by the processor */
1244 static inline s64
1245 ia64_pal_mem_attrib (u64 *mem_attrib)
1246 {
1247         struct ia64_pal_retval iprv;
1248         PAL_CALL(iprv, PAL_MEM_ATTRIB, 0, 0, 0);
1249         if (mem_attrib)
1250                 *mem_attrib = iprv.v0 & 0xff;
1251         return iprv.status;
1252 }
1253
1254 /* Return the amount of memory needed for second phase of processor
1255  * self-test and the required alignment of memory.
1256  */
1257 static inline s64
1258 ia64_pal_mem_for_test (u64 *bytes_needed, u64 *alignment)
1259 {
1260         struct ia64_pal_retval iprv;
1261         PAL_CALL(iprv, PAL_MEM_FOR_TEST, 0, 0, 0);
1262         if (bytes_needed)
1263                 *bytes_needed = iprv.v0;
1264         if (alignment)
1265                 *alignment = iprv.v1;
1266         return iprv.status;
1267 }
1268
1269 typedef union pal_perf_mon_info_u {
1270         u64                       ppmi_data;
1271         struct {
1272                u64              generic         : 8,
1273                                 width           : 8,
1274                                 cycles          : 8,
1275                                 retired         : 8,
1276                                 reserved        : 32;
1277         } pal_perf_mon_info_s;
1278 } pal_perf_mon_info_u_t;
1279
1280 /* Return the performance monitor information about what can be counted
1281  * and how to configure the monitors to count the desired events.
1282  */
1283 static inline s64
1284 ia64_pal_perf_mon_info (u64 *pm_buffer, pal_perf_mon_info_u_t *pm_info)
1285 {
1286         struct ia64_pal_retval iprv;
1287         PAL_CALL(iprv, PAL_PERF_MON_INFO, (unsigned long) pm_buffer, 0, 0);
1288         if (pm_info)
1289                 pm_info->ppmi_data = iprv.v0;
1290         return iprv.status;
1291 }
1292
1293 /* Specifies the physical address of the processor interrupt block
1294  * and I/O port space.
1295  */
1296 static inline s64
1297 ia64_pal_platform_addr (u64 type, u64 physical_addr)
1298 {
1299         struct ia64_pal_retval iprv;
1300         PAL_CALL(iprv, PAL_PLATFORM_ADDR, type, physical_addr, 0);
1301         return iprv.status;
1302 }
1303
1304 /* Set the SAL PMI entrypoint in memory */
1305 static inline s64
1306 ia64_pal_pmi_entrypoint (u64 sal_pmi_entry_addr)
1307 {
1308         struct ia64_pal_retval iprv;
1309         PAL_CALL(iprv, PAL_PMI_ENTRYPOINT, sal_pmi_entry_addr, 0, 0);
1310         return iprv.status;
1311 }
1312
1313 struct pal_features_s;
1314 /* Provide information about configurable processor features */
1315 static inline s64
1316 ia64_pal_proc_get_features (u64 *features_avail,
1317                             u64 *features_status,
1318                             u64 *features_control)
1319 {
1320         struct ia64_pal_retval iprv;
1321         PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, 0, 0);
1322         if (iprv.status == 0) {
1323                 *features_avail   = iprv.v0;
1324                 *features_status  = iprv.v1;
1325                 *features_control = iprv.v2;
1326         }
1327         return iprv.status;
1328 }
1329
1330 /* Enable/disable processor dependent features */
1331 static inline s64
1332 ia64_pal_proc_set_features (u64 feature_select)
1333 {
1334         struct ia64_pal_retval iprv;
1335         PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES, feature_select, 0, 0);
1336         return iprv.status;
1337 }
1338
1339 /*
1340  * Put everything in a struct so we avoid the global offset table whenever
1341  * possible.
1342  */
1343 typedef struct ia64_ptce_info_s {
1344         u64             base;
1345         u32             count[2];
1346         u32             stride[2];
1347 } ia64_ptce_info_t;
1348
1349 /* Return the information required for the architected loop used to purge
1350  * (initialize) the entire TC
1351  */
1352 static inline s64
1353 ia64_get_ptce (ia64_ptce_info_t *ptce)
1354 {
1355         struct ia64_pal_retval iprv;
1356
1357         if (!ptce)
1358                 return -1;
1359
1360         PAL_CALL(iprv, PAL_PTCE_INFO, 0, 0, 0);
1361         if (iprv.status == 0) {
1362                 ptce->base = iprv.v0;
1363                 ptce->count[0] = iprv.v1 >> 32;
1364                 ptce->count[1] = iprv.v1 & 0xffffffff;
1365                 ptce->stride[0] = iprv.v2 >> 32;
1366                 ptce->stride[1] = iprv.v2 & 0xffffffff;
1367         }
1368         return iprv.status;
1369 }
1370
1371 /* Return info about implemented application and control registers. */
1372 static inline s64
1373 ia64_pal_register_info (u64 info_request, u64 *reg_info_1, u64 *reg_info_2)
1374 {
1375         struct ia64_pal_retval iprv;
1376         PAL_CALL(iprv, PAL_REGISTER_INFO, info_request, 0, 0);
1377         if (reg_info_1)
1378                 *reg_info_1 = iprv.v0;
1379         if (reg_info_2)
1380                 *reg_info_2 = iprv.v1;
1381         return iprv.status;
1382 }
1383
1384 typedef union pal_hints_u {
1385         u64                     ph_data;
1386         struct {
1387                u64              si              : 1,
1388                                 li              : 1,
1389                                 reserved        : 62;
1390         } pal_hints_s;
1391 } pal_hints_u_t;
1392
1393 /* Return information about the register stack and RSE for this processor
1394  * implementation.
1395  */
1396 static inline s64
1397 ia64_pal_rse_info (u64 *num_phys_stacked, pal_hints_u_t *hints)
1398 {
1399         struct ia64_pal_retval iprv;
1400         PAL_CALL(iprv, PAL_RSE_INFO, 0, 0, 0);
1401         if (num_phys_stacked)
1402                 *num_phys_stacked = iprv.v0;
1403         if (hints)
1404                 hints->ph_data = iprv.v1;
1405         return iprv.status;
1406 }
1407
1408 /* Cause the processor to enter SHUTDOWN state, where prefetching and execution are
1409  * suspended, but cause cache and TLB coherency to be maintained.
1410  * This is usually called in IA-32 mode.
1411  */
1412 static inline s64
1413 ia64_pal_shutdown (void)
1414 {
1415         struct ia64_pal_retval iprv;
1416         PAL_CALL(iprv, PAL_SHUTDOWN, 0, 0, 0);
1417         return iprv.status;
1418 }
1419
1420 /* Perform the second phase of processor self-test. */
1421 static inline s64
1422 ia64_pal_test_proc (u64 test_addr, u64 test_size, u64 attributes, u64 *self_test_state)
1423 {
1424         struct ia64_pal_retval iprv;
1425         PAL_CALL(iprv, PAL_TEST_PROC, test_addr, test_size, attributes);
1426         if (self_test_state)
1427                 *self_test_state = iprv.v0;
1428         return iprv.status;
1429 }
1430
1431 typedef union  pal_version_u {
1432         u64     pal_version_val;
1433         struct {
1434                 u64     pv_pal_b_rev            :       8;
1435                 u64     pv_pal_b_model          :       8;
1436                 u64     pv_reserved1            :       8;
1437                 u64     pv_pal_vendor           :       8;
1438                 u64     pv_pal_a_rev            :       8;
1439                 u64     pv_pal_a_model          :       8;
1440                 u64     pv_reserved2            :       16;
1441         } pal_version_s;
1442 } pal_version_u_t;
1443
1444
1445 /*
1446  * Return PAL version information.  While the documentation states that
1447  * PAL_VERSION can be called in either physical or virtual mode, some
1448  * implementations only allow physical calls.  We don't call it very often,
1449  * so the overhead isn't worth eliminating.
1450  */
1451 static inline s64
1452 ia64_pal_version (pal_version_u_t *pal_min_version, pal_version_u_t *pal_cur_version)
1453 {
1454         struct ia64_pal_retval iprv;
1455         PAL_CALL_PHYS(iprv, PAL_VERSION, 0, 0, 0);
1456         if (pal_min_version)
1457                 pal_min_version->pal_version_val = iprv.v0;
1458
1459         if (pal_cur_version)
1460                 pal_cur_version->pal_version_val = iprv.v1;
1461
1462         return iprv.status;
1463 }
1464
1465 typedef union pal_tc_info_u {
1466         u64                     pti_val;
1467         struct {
1468                u64              num_sets        :       8,
1469                                 associativity   :       8,
1470                                 num_entries     :       16,
1471                                 pf              :       1,
1472                                 unified         :       1,
1473                                 reduce_tr       :       1,
1474                                 reserved        :       29;
1475         } pal_tc_info_s;
1476 } pal_tc_info_u_t;
1477
1478 #define tc_reduce_tr            pal_tc_info_s.reduce_tr
1479 #define tc_unified              pal_tc_info_s.unified
1480 #define tc_pf                   pal_tc_info_s.pf
1481 #define tc_num_entries          pal_tc_info_s.num_entries
1482 #define tc_associativity        pal_tc_info_s.associativity
1483 #define tc_num_sets             pal_tc_info_s.num_sets
1484
1485
1486 /* Return information about the virtual memory characteristics of the processor
1487  * implementation.
1488  */
1489 static inline s64
1490 ia64_pal_vm_info (u64 tc_level, u64 tc_type,  pal_tc_info_u_t *tc_info, u64 *tc_pages)
1491 {
1492         struct ia64_pal_retval iprv;
1493         PAL_CALL(iprv, PAL_VM_INFO, tc_level, tc_type, 0);
1494         if (tc_info)
1495                 tc_info->pti_val = iprv.v0;
1496         if (tc_pages)
1497                 *tc_pages = iprv.v1;
1498         return iprv.status;
1499 }
1500
1501 /* Get page size information about the virtual memory characteristics of the processor
1502  * implementation.
1503  */
1504 static inline s64
1505 ia64_pal_vm_page_size (u64 *tr_pages, u64 *vw_pages)
1506 {
1507         struct ia64_pal_retval iprv;
1508         PAL_CALL(iprv, PAL_VM_PAGE_SIZE, 0, 0, 0);
1509         if (tr_pages)
1510                 *tr_pages = iprv.v0;
1511         if (vw_pages)
1512                 *vw_pages = iprv.v1;
1513         return iprv.status;
1514 }
1515
1516 typedef union pal_vm_info_1_u {
1517         u64                     pvi1_val;
1518         struct {
1519                 u64             vw              : 1,
1520                                 phys_add_size   : 7,
1521                                 key_size        : 8,
1522                                 max_pkr         : 8,
1523                                 hash_tag_id     : 8,
1524                                 max_dtr_entry   : 8,
1525                                 max_itr_entry   : 8,
1526                                 max_unique_tcs  : 8,
1527                                 num_tc_levels   : 8;
1528         } pal_vm_info_1_s;
1529 } pal_vm_info_1_u_t;
1530
1531 typedef union pal_vm_info_2_u {
1532         u64                     pvi2_val;
1533         struct {
1534                 u64             impl_va_msb     : 8,
1535                                 rid_size        : 8,
1536                                 reserved        : 48;
1537         } pal_vm_info_2_s;
1538 } pal_vm_info_2_u_t;
1539
1540 /* Get summary information about the virtual memory characteristics of the processor
1541  * implementation.
1542  */
1543 static inline s64
1544 ia64_pal_vm_summary (pal_vm_info_1_u_t *vm_info_1, pal_vm_info_2_u_t *vm_info_2)
1545 {
1546         struct ia64_pal_retval iprv;
1547         PAL_CALL(iprv, PAL_VM_SUMMARY, 0, 0, 0);
1548         if (vm_info_1)
1549                 vm_info_1->pvi1_val = iprv.v0;
1550         if (vm_info_2)
1551                 vm_info_2->pvi2_val = iprv.v1;
1552         return iprv.status;
1553 }
1554
1555 typedef union pal_itr_valid_u {
1556         u64                     piv_val;
1557         struct {
1558                u64              access_rights_valid     : 1,
1559                                 priv_level_valid        : 1,
1560                                 dirty_bit_valid         : 1,
1561                                 mem_attr_valid          : 1,
1562                                 reserved                : 60;
1563         } pal_tr_valid_s;
1564 } pal_tr_valid_u_t;
1565
1566 /* Read a translation register */
1567 static inline s64
1568 ia64_pal_tr_read (u64 reg_num, u64 tr_type, u64 *tr_buffer, pal_tr_valid_u_t *tr_valid)
1569 {
1570         struct ia64_pal_retval iprv;
1571         PAL_CALL_PHYS_STK(iprv, PAL_VM_TR_READ, reg_num, tr_type,(u64)ia64_tpa(tr_buffer));
1572         if (tr_valid)
1573                 tr_valid->piv_val = iprv.v0;
1574         return iprv.status;
1575 }
1576
1577 /*
1578  * PAL_PREFETCH_VISIBILITY transaction types
1579  */
1580 #define PAL_VISIBILITY_VIRTUAL          0
1581 #define PAL_VISIBILITY_PHYSICAL         1
1582
1583 /*
1584  * PAL_PREFETCH_VISIBILITY return codes
1585  */
1586 #define PAL_VISIBILITY_OK               1
1587 #define PAL_VISIBILITY_OK_REMOTE_NEEDED 0
1588 #define PAL_VISIBILITY_INVAL_ARG        -2
1589 #define PAL_VISIBILITY_ERROR            -3
1590
1591 static inline s64
1592 ia64_pal_prefetch_visibility (s64 trans_type)
1593 {
1594         struct ia64_pal_retval iprv;
1595         PAL_CALL(iprv, PAL_PREFETCH_VISIBILITY, trans_type, 0, 0);
1596         return iprv.status;
1597 }
1598
1599 /* data structure for getting information on logical to physical mappings */
1600 typedef union pal_log_overview_u {
1601         struct {
1602                 u64     num_log         :16,    /* Total number of logical
1603                                                  * processors on this die
1604                                                  */
1605                         tpc             :8,     /* Threads per core */
1606                         reserved3       :8,     /* Reserved */
1607                         cpp             :8,     /* Cores per processor */
1608                         reserved2       :8,     /* Reserved */
1609                         ppid            :8,     /* Physical processor ID */
1610                         reserved1       :8;     /* Reserved */
1611         } overview_bits;
1612         u64 overview_data;
1613 } pal_log_overview_t;
1614
1615 typedef union pal_proc_n_log_info1_u{
1616         struct {
1617                 u64     tid             :16,    /* Thread id */
1618                         reserved2       :16,    /* Reserved */
1619                         cid             :16,    /* Core id */
1620                         reserved1       :16;    /* Reserved */
1621         } ppli1_bits;
1622         u64     ppli1_data;
1623 } pal_proc_n_log_info1_t;
1624
1625 typedef union pal_proc_n_log_info2_u {
1626         struct {
1627                 u64     la              :16,    /* Logical address */
1628                         reserved        :48;    /* Reserved */
1629         } ppli2_bits;
1630         u64     ppli2_data;
1631 } pal_proc_n_log_info2_t;
1632
1633 typedef struct pal_logical_to_physical_s
1634 {
1635         pal_log_overview_t overview;
1636         pal_proc_n_log_info1_t ppli1;
1637         pal_proc_n_log_info2_t ppli2;
1638 } pal_logical_to_physical_t;
1639
1640 #define overview_num_log        overview.overview_bits.num_log
1641 #define overview_tpc            overview.overview_bits.tpc
1642 #define overview_cpp            overview.overview_bits.cpp
1643 #define overview_ppid           overview.overview_bits.ppid
1644 #define log1_tid                ppli1.ppli1_bits.tid
1645 #define log1_cid                ppli1.ppli1_bits.cid
1646 #define log2_la                 ppli2.ppli2_bits.la
1647
1648 /* Get information on logical to physical processor mappings. */
1649 static inline s64
1650 ia64_pal_logical_to_phys(u64 proc_number, pal_logical_to_physical_t *mapping)
1651 {
1652         struct ia64_pal_retval iprv;
1653
1654         PAL_CALL(iprv, PAL_LOGICAL_TO_PHYSICAL, proc_number, 0, 0);
1655
1656         if (iprv.status == PAL_STATUS_SUCCESS)
1657         {
1658                 mapping->overview.overview_data = iprv.v0;
1659                 mapping->ppli1.ppli1_data = iprv.v1;
1660                 mapping->ppli2.ppli2_data = iprv.v2;
1661         }
1662
1663         return iprv.status;
1664 }
1665
1666 typedef struct pal_cache_shared_info_s
1667 {
1668         u64 num_shared;
1669         pal_proc_n_log_info1_t ppli1;
1670         pal_proc_n_log_info2_t ppli2;
1671 } pal_cache_shared_info_t;
1672
1673 /* Get information on logical to physical processor mappings. */
1674 static inline s64
1675 ia64_pal_cache_shared_info(u64 level,
1676                 u64 type,
1677                 u64 proc_number,
1678                 pal_cache_shared_info_t *info)
1679 {
1680         struct ia64_pal_retval iprv;
1681
1682         PAL_CALL(iprv, PAL_CACHE_SHARED_INFO, level, type, proc_number);
1683
1684         if (iprv.status == PAL_STATUS_SUCCESS) {
1685                 info->num_shared = iprv.v0;
1686                 info->ppli1.ppli1_data = iprv.v1;
1687                 info->ppli2.ppli2_data = iprv.v2;
1688         }
1689
1690         return iprv.status;
1691 }
1692 #endif /* __ASSEMBLY__ */
1693
1694 #endif /* _ASM_IA64_PAL_H */