1 /* *********************************************************************
2 * SB1250 Board Support Package
4 * Interrupt Mapper definitions File: sb1250_int.h
6 * This module contains constants for manipulating the SB1250's
7 * interrupt mapper and definitions for the interrupt sources.
9 * SB1250 specification level: User's manual 1/02/02
11 * Author: Mitch Lichtenberg
13 *********************************************************************
15 * Copyright 2000,2001,2002,2003
16 * Broadcom Corporation. All rights reserved.
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version.
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 ********************************************************************* */
38 #include "sb1250_defs.h"
40 /* *********************************************************************
41 * Interrupt Mapper Constants
42 ********************************************************************* */
45 * Interrupt sources (Table 4-8, UM 0.2)
47 * First, the interrupt numbers.
50 #if SIBYTE_HDR_FEATURE_1250_112x
52 #define K_INT_SOURCES 64
54 #define K_INT_WATCHDOG_TIMER_0 0
55 #define K_INT_WATCHDOG_TIMER_1 1
56 #define K_INT_TIMER_0 2
57 #define K_INT_TIMER_1 3
58 #define K_INT_TIMER_2 4
59 #define K_INT_TIMER_3 5
62 #define K_INT_UART_0 8
63 #define K_INT_UART_1 9
64 #define K_INT_SER_0 10
65 #define K_INT_SER_1 11
66 #define K_INT_PCMCIA 12
67 #define K_INT_ADDR_TRAP 13
68 #define K_INT_PERF_CNT 14
69 #define K_INT_TRACE_FREEZE 15
70 #define K_INT_BAD_ECC 16
71 #define K_INT_COR_ECC 17
72 #define K_INT_IO_BUS 18
73 #define K_INT_MAC_0 19
74 #define K_INT_MAC_1 20
75 #define K_INT_MAC_2 21
76 #define K_INT_DM_CH_0 22
77 #define K_INT_DM_CH_1 23
78 #define K_INT_DM_CH_2 24
79 #define K_INT_DM_CH_3 25
80 #define K_INT_MBOX_0 26
81 #define K_INT_MBOX_1 27
82 #define K_INT_MBOX_2 28
83 #define K_INT_MBOX_3 29
84 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
85 #define K_INT_CYCLE_CP0_INT 30
86 #define K_INT_CYCLE_CP1_INT 31
87 #endif /* 1250 PASS2 || 112x PASS1 */
88 #define K_INT_GPIO_0 32
89 #define K_INT_GPIO_1 33
90 #define K_INT_GPIO_2 34
91 #define K_INT_GPIO_3 35
92 #define K_INT_GPIO_4 36
93 #define K_INT_GPIO_5 37
94 #define K_INT_GPIO_6 38
95 #define K_INT_GPIO_7 39
96 #define K_INT_GPIO_8 40
97 #define K_INT_GPIO_9 41
98 #define K_INT_GPIO_10 42
99 #define K_INT_GPIO_11 43
100 #define K_INT_GPIO_12 44
101 #define K_INT_GPIO_13 45
102 #define K_INT_GPIO_14 46
103 #define K_INT_GPIO_15 47
104 #define K_INT_LDT_FATAL 48
105 #define K_INT_LDT_NONFATAL 49
106 #define K_INT_LDT_SMI 50
107 #define K_INT_LDT_NMI 51
108 #define K_INT_LDT_INIT 52
109 #define K_INT_LDT_STARTUP 53
110 #define K_INT_LDT_EXT 54
111 #define K_INT_PCI_ERROR 55
112 #define K_INT_PCI_INTA 56
113 #define K_INT_PCI_INTB 57
114 #define K_INT_PCI_INTC 58
115 #define K_INT_PCI_INTD 59
116 #define K_INT_SPARE_2 60
117 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
118 #define K_INT_MAC_0_CH1 61
119 #define K_INT_MAC_1_CH1 62
120 #define K_INT_MAC_2_CH1 63
121 #endif /* 1250 PASS2 || 112x PASS1 */
124 * Mask values for each interrupt
127 #define M_INT_WATCHDOG_TIMER_0 _SB_MAKEMASK1(K_INT_WATCHDOG_TIMER_0)
128 #define M_INT_WATCHDOG_TIMER_1 _SB_MAKEMASK1(K_INT_WATCHDOG_TIMER_1)
129 #define M_INT_TIMER_0 _SB_MAKEMASK1(K_INT_TIMER_0)
130 #define M_INT_TIMER_1 _SB_MAKEMASK1(K_INT_TIMER_1)
131 #define M_INT_TIMER_2 _SB_MAKEMASK1(K_INT_TIMER_2)
132 #define M_INT_TIMER_3 _SB_MAKEMASK1(K_INT_TIMER_3)
133 #define M_INT_SMB_0 _SB_MAKEMASK1(K_INT_SMB_0)
134 #define M_INT_SMB_1 _SB_MAKEMASK1(K_INT_SMB_1)
135 #define M_INT_UART_0 _SB_MAKEMASK1(K_INT_UART_0)
136 #define M_INT_UART_1 _SB_MAKEMASK1(K_INT_UART_1)
137 #define M_INT_SER_0 _SB_MAKEMASK1(K_INT_SER_0)
138 #define M_INT_SER_1 _SB_MAKEMASK1(K_INT_SER_1)
139 #define M_INT_PCMCIA _SB_MAKEMASK1(K_INT_PCMCIA)
140 #define M_INT_ADDR_TRAP _SB_MAKEMASK1(K_INT_ADDR_TRAP)
141 #define M_INT_PERF_CNT _SB_MAKEMASK1(K_INT_PERF_CNT)
142 #define M_INT_TRACE_FREEZE _SB_MAKEMASK1(K_INT_TRACE_FREEZE)
143 #define M_INT_BAD_ECC _SB_MAKEMASK1(K_INT_BAD_ECC)
144 #define M_INT_COR_ECC _SB_MAKEMASK1(K_INT_COR_ECC)
145 #define M_INT_IO_BUS _SB_MAKEMASK1(K_INT_IO_BUS)
146 #define M_INT_MAC_0 _SB_MAKEMASK1(K_INT_MAC_0)
147 #define M_INT_MAC_1 _SB_MAKEMASK1(K_INT_MAC_1)
148 #define M_INT_MAC_2 _SB_MAKEMASK1(K_INT_MAC_2)
149 #define M_INT_DM_CH_0 _SB_MAKEMASK1(K_INT_DM_CH_0)
150 #define M_INT_DM_CH_1 _SB_MAKEMASK1(K_INT_DM_CH_1)
151 #define M_INT_DM_CH_2 _SB_MAKEMASK1(K_INT_DM_CH_2)
152 #define M_INT_DM_CH_3 _SB_MAKEMASK1(K_INT_DM_CH_3)
153 #define M_INT_MBOX_0 _SB_MAKEMASK1(K_INT_MBOX_0)
154 #define M_INT_MBOX_1 _SB_MAKEMASK1(K_INT_MBOX_1)
155 #define M_INT_MBOX_2 _SB_MAKEMASK1(K_INT_MBOX_2)
156 #define M_INT_MBOX_3 _SB_MAKEMASK1(K_INT_MBOX_3)
157 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
158 #define M_INT_CYCLE_CP0_INT _SB_MAKEMASK1(K_INT_CYCLE_CP0_INT)
159 #define M_INT_CYCLE_CP1_INT _SB_MAKEMASK1(K_INT_CYCLE_CP1_INT)
160 #endif /* 1250 PASS2 || 112x PASS1 */
161 #define M_INT_GPIO_0 _SB_MAKEMASK1(K_INT_GPIO_0)
162 #define M_INT_GPIO_1 _SB_MAKEMASK1(K_INT_GPIO_1)
163 #define M_INT_GPIO_2 _SB_MAKEMASK1(K_INT_GPIO_2)
164 #define M_INT_GPIO_3 _SB_MAKEMASK1(K_INT_GPIO_3)
165 #define M_INT_GPIO_4 _SB_MAKEMASK1(K_INT_GPIO_4)
166 #define M_INT_GPIO_5 _SB_MAKEMASK1(K_INT_GPIO_5)
167 #define M_INT_GPIO_6 _SB_MAKEMASK1(K_INT_GPIO_6)
168 #define M_INT_GPIO_7 _SB_MAKEMASK1(K_INT_GPIO_7)
169 #define M_INT_GPIO_8 _SB_MAKEMASK1(K_INT_GPIO_8)
170 #define M_INT_GPIO_9 _SB_MAKEMASK1(K_INT_GPIO_9)
171 #define M_INT_GPIO_10 _SB_MAKEMASK1(K_INT_GPIO_10)
172 #define M_INT_GPIO_11 _SB_MAKEMASK1(K_INT_GPIO_11)
173 #define M_INT_GPIO_12 _SB_MAKEMASK1(K_INT_GPIO_12)
174 #define M_INT_GPIO_13 _SB_MAKEMASK1(K_INT_GPIO_13)
175 #define M_INT_GPIO_14 _SB_MAKEMASK1(K_INT_GPIO_14)
176 #define M_INT_GPIO_15 _SB_MAKEMASK1(K_INT_GPIO_15)
177 #define M_INT_LDT_FATAL _SB_MAKEMASK1(K_INT_LDT_FATAL)
178 #define M_INT_LDT_NONFATAL _SB_MAKEMASK1(K_INT_LDT_NONFATAL)
179 #define M_INT_LDT_SMI _SB_MAKEMASK1(K_INT_LDT_SMI)
180 #define M_INT_LDT_NMI _SB_MAKEMASK1(K_INT_LDT_NMI)
181 #define M_INT_LDT_INIT _SB_MAKEMASK1(K_INT_LDT_INIT)
182 #define M_INT_LDT_STARTUP _SB_MAKEMASK1(K_INT_LDT_STARTUP)
183 #define M_INT_LDT_EXT _SB_MAKEMASK1(K_INT_LDT_EXT)
184 #define M_INT_PCI_ERROR _SB_MAKEMASK1(K_INT_PCI_ERROR)
185 #define M_INT_PCI_INTA _SB_MAKEMASK1(K_INT_PCI_INTA)
186 #define M_INT_PCI_INTB _SB_MAKEMASK1(K_INT_PCI_INTB)
187 #define M_INT_PCI_INTC _SB_MAKEMASK1(K_INT_PCI_INTC)
188 #define M_INT_PCI_INTD _SB_MAKEMASK1(K_INT_PCI_INTD)
189 #define M_INT_SPARE_2 _SB_MAKEMASK1(K_INT_SPARE_2)
190 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
191 #define M_INT_MAC_0_CH1 _SB_MAKEMASK1(K_INT_MAC_0_CH1)
192 #define M_INT_MAC_1_CH1 _SB_MAKEMASK1(K_INT_MAC_1_CH1)
193 #define M_INT_MAC_2_CH1 _SB_MAKEMASK1(K_INT_MAC_2_CH1)
194 #endif /* 1250 PASS2 || 112x PASS1 */
200 #define K_INT_MAP_I0 0 /* interrupt pins on processor */
201 #define K_INT_MAP_I1 1
202 #define K_INT_MAP_I2 2
203 #define K_INT_MAP_I3 3
204 #define K_INT_MAP_I4 4
205 #define K_INT_MAP_I5 5
206 #define K_INT_MAP_NMI 6 /* nonmaskable */
207 #define K_INT_MAP_DINT 7 /* debug interrupt */
210 * LDT Interrupt Set Register (table 4-5)
213 #define S_INT_LDT_INTMSG 0
214 #define M_INT_LDT_INTMSG _SB_MAKEMASK(3,S_INT_LDT_INTMSG)
215 #define V_INT_LDT_INTMSG(x) _SB_MAKEVALUE(x,S_INT_LDT_INTMSG)
216 #define G_INT_LDT_INTMSG(x) _SB_GETVALUE(x,S_INT_LDT_INTMSG,M_INT_LDT_INTMSG)
218 #define K_INT_LDT_INTMSG_FIXED 0
219 #define K_INT_LDT_INTMSG_ARBITRATED 1
220 #define K_INT_LDT_INTMSG_SMI 2
221 #define K_INT_LDT_INTMSG_NMI 3
222 #define K_INT_LDT_INTMSG_INIT 4
223 #define K_INT_LDT_INTMSG_STARTUP 5
224 #define K_INT_LDT_INTMSG_EXTINT 6
225 #define K_INT_LDT_INTMSG_RESERVED 7
227 #define M_INT_LDT_EDGETRIGGER 0
228 #define M_INT_LDT_LEVELTRIGGER _SB_MAKEMASK1(3)
230 #define M_INT_LDT_PHYSICALDEST 0
231 #define M_INT_LDT_LOGICALDEST _SB_MAKEMASK1(4)
233 #define S_INT_LDT_INTDEST 5
234 #define M_INT_LDT_INTDEST _SB_MAKEMASK(10,S_INT_LDT_INTDEST)
235 #define V_INT_LDT_INTDEST(x) _SB_MAKEVALUE(x,S_INT_LDT_INTDEST)
236 #define G_INT_LDT_INTDEST(x) _SB_GETVALUE(x,S_INT_LDT_INTDEST,M_INT_LDT_INTDEST)
238 #define S_INT_LDT_VECTOR 13
239 #define M_INT_LDT_VECTOR _SB_MAKEMASK(8,S_INT_LDT_VECTOR)
240 #define V_INT_LDT_VECTOR(x) _SB_MAKEVALUE(x,S_INT_LDT_VECTOR)
241 #define G_INT_LDT_VECTOR(x) _SB_GETVALUE(x,S_INT_LDT_VECTOR,M_INT_LDT_VECTOR)
244 * Vector format (Table 4-6)
247 #define M_LDTVECT_RAISEINT 0x00
248 #define M_LDTVECT_RAISEMBOX 0x40
251 #endif /* 1250/112x */