include/asm-mips/system.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003 by Ralf Baechle
   7  * Copyright (C) 1996 by Paul M. Antoine
   8  * Copyright (C) 1999 Silicon Graphics
   9  * Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com
  10  * Copyright (C) 2000 MIPS Technologies, Inc.
  11  */
  12 #ifndef _ASM_SYSTEM_H
  13 #define _ASM_SYSTEM_H
  14
  15 #include <linux/config.h>
  16 #include <linux/types.h>
  17
  18 #include <asm/addrspace.h>
  19 #include <asm/cpu-features.h>
  20 #include <asm/dsp.h>
  21 #include <asm/ptrace.h>
  22 #include <asm/war.h>
  23 #include <asm/interrupt.h>
  24
  25 /*
  26  * read_barrier_depends - Flush all pending reads that subsequents reads
  27  * depend on.
  28  *
  29  * No data-dependent reads from memory-like regions are ever reordered
  30  * over this barrier.  All reads preceding this primitive are guaranteed
  31  * to access memory (but not necessarily other CPUs' caches) before any
  32  * reads following this primitive that depend on the data return by
  33  * any of the preceding reads.  This primitive is much lighter weight than
  34  * rmb() on most CPUs, and is never heavier weight than is
  35  * rmb().
  36  *
  37  * These ordering constraints are respected by both the local CPU
  38  * and the compiler.
  39  *
  40  * Ordering is not guaranteed by anything other than these primitives,
  41  * not even by data dependencies.  See the documentation for
  42  * memory_barrier() for examples and URLs to more information.
  43  *
  44  * For example, the following code would force ordering (the initial
  45  * value of "a" is zero, "b" is one, and "p" is "&a"):
  46  *
  47  * <programlisting>
  48  *      CPU 0                           CPU 1
  49  *
  50  *      b = 2;
  51  *      memory_barrier();
  52  *      p = &b;                         q = p;
  53  *                                      read_barrier_depends();
  54  *                                      d = *q;
  55  * </programlisting>
  56  *
  57  * because the read of "*q" depends on the read of "p" and these
  58  * two reads are separated by a read_barrier_depends().  However,
  59  * the following code, with the same initial values for "a" and "b":
  60  *
  61  * <programlisting>
  62  *      CPU 0                           CPU 1
  63  *
  64  *      a = 2;
  65  *      memory_barrier();
  66  *      b = 3;                          y = b;
  67  *                                      read_barrier_depends();
  68  *                                      x = a;
  69  * </programlisting>
  70  *
  71  * does not enforce ordering, since there is no data dependency between
  72  * the read of "a" and the read of "b".  Therefore, on some CPUs, such
  73  * as Alpha, "y" could be set to 3 and "x" to 0.  Use rmb()
  74  * in cases like thiswhere there are no data dependencies.
  75  */
  76
  77 #define read_barrier_depends()  do { } while(0)
  78
  79 #ifdef CONFIG_CPU_HAS_SYNC
  80 #define __sync()                                \
  81         __asm__ __volatile__(                   \
  82                 ".set   push\n\t"               \
  83                 ".set   noreorder\n\t"          \
  84                 ".set   mips2\n\t"              \
  85                 "sync\n\t"                      \
  86                 ".set   pop"                    \
  87                 : /* no output */               \
  88                 : /* no input */                \
  89                 : "memory")
  90 #else
  91 #define __sync()        do { } while(0)
  92 #endif
  93
  94 #define __fast_iob()                            \
  95         __asm__ __volatile__(                   \
  96                 ".set   push\n\t"               \
  97                 ".set   noreorder\n\t"          \
  98                 "lw     $0,%0\n\t"              \
  99                 "nop\n\t"                       \
 100                 ".set   pop"                    \
 101                 : /* no output */               \
 102                 : "m" (*(int *)CKSEG1)          \
 103                 : "memory")
 104
 105 #define fast_wmb()      __sync()
 106 #define fast_rmb()      __sync()
 107 #define fast_mb()       __sync()
 108 #define fast_iob()                              \
 109         do {                                    \
 110                 __sync();                       \
 111                 __fast_iob();                   \
 112         } while (0)
 113
 114 #ifdef CONFIG_CPU_HAS_WB
 115
 116 #include <asm/wbflush.h>
 117
 118 #define wmb()           fast_wmb()
 119 #define rmb()           fast_rmb()
 120 #define mb()            wbflush()
 121 #define iob()           wbflush()
 122
 123 #else /* !CONFIG_CPU_HAS_WB */
 124
 125 #define wmb()           fast_wmb()
 126 #define rmb()           fast_rmb()
 127 #define mb()            fast_mb()
 128 #define iob()           fast_iob()
 129
 130 #endif /* !CONFIG_CPU_HAS_WB */
 131
 132 #ifdef CONFIG_SMP
 133 #define smp_mb()        mb()
 134 #define smp_rmb()       rmb()
 135 #define smp_wmb()       wmb()
 136 #define smp_read_barrier_depends()      read_barrier_depends()
 137 #else
 138 #define smp_mb()        barrier()
 139 #define smp_rmb()       barrier()
 140 #define smp_wmb()       barrier()
 141 #define smp_read_barrier_depends()      do { } while(0)
 142 #endif
 143
 144 #define set_mb(var, value) \
 145 do { var = value; mb(); } while (0)
 146
 147 #define set_wmb(var, value) \
 148 do { var = value; wmb(); } while (0)
 149
 150 /*
 151  * switch_to(n) should switch tasks to task nr n, first
 152  * checking that n isn't the current task, in which case it does nothing.
 153  */
 154 extern asmlinkage void *resume(void *last, void *next, void *next_ti);
 155
 156 struct task_struct;
 157
 158 #define switch_to(prev,next,last)                                       \
 159 do {                                                                    \
 160         if (cpu_has_dsp)                                                \
 161                 __save_dsp(prev);                                       \
 162         (last) = resume(prev, next, next->thread_info);                 \
 163         if (cpu_has_dsp)                                                \
 164                 __restore_dsp(current);                                 \
 165 } while(0)
 166
 167 #define ROT_IN_PIECES                                                   \
 168         "       .set    noreorder       \n"                             \
 169         "       .set    reorder         \n"
 170
 171 static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
 172 {
 173         __u32 retval;
 174
 175         if (cpu_has_llsc && R10000_LLSC_WAR) {
 176                 unsigned long dummy;
 177
 178                 __asm__ __volatile__(
 179                 "1:     ll      %0, %3                  # xchg_u32      \n"
 180                 "       move    %2, %z4                                 \n"
 181                 "       sc      %2, %1                                  \n"
 182                 "       beqzl   %2, 1b                                  \n"
 183                 ROT_IN_PIECES
 184 #ifdef CONFIG_SMP
 185                 "       sync                                            \n"
 186 #endif
 187                 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
 188                 : "R" (*m), "Jr" (val)
 189                 : "memory");
 190         } else if (cpu_has_llsc) {
 191                 unsigned long dummy;
 192
 193                 __asm__ __volatile__(
 194                 "1:     ll      %0, %3                  # xchg_u32      \n"
 195                 "       move    %2, %z4                                 \n"
 196                 "       sc      %2, %1                                  \n"
 197                 "       beqz    %2, 1b                                  \n"
 198 #ifdef CONFIG_SMP
 199                 "       sync                                            \n"
 200 #endif
 201                 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
 202                 : "R" (*m), "Jr" (val)
 203                 : "memory");
 204         } else {
 205                 unsigned long flags;
 206
 207                 local_irq_save(flags);
 208                 retval = *m;
 209                 *m = val;
 210                 local_irq_restore(flags);       /* implies memory barrier  */
 211         }
 212
 213         return retval;
 214 }
 215
 216 #ifdef CONFIG_64BIT
 217 static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
 218 {
 219         __u64 retval;
 220
 221         if (cpu_has_llsc && R10000_LLSC_WAR) {
 222                 unsigned long dummy;
 223
 224                 __asm__ __volatile__(
 225                 "1:     lld     %0, %3                  # xchg_u64      \n"
 226                 "       move    %2, %z4                                 \n"
 227                 "       scd     %2, %1                                  \n"
 228                 "       beqzl   %2, 1b                                  \n"
 229                 ROT_IN_PIECES
 230 #ifdef CONFIG_SMP
 231                 "       sync                                            \n"
 232 #endif
 233                 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
 234                 : "R" (*m), "Jr" (val)
 235                 : "memory");
 236         } else if (cpu_has_llsc) {
 237                 unsigned long dummy;
 238
 239                 __asm__ __volatile__(
 240                 "1:     lld     %0, %3                  # xchg_u64      \n"
 241                 "       move    %2, %z4                                 \n"
 242                 "       scd     %2, %1                                  \n"
 243                 "       beqz    %2, 1b                                  \n"
 244 #ifdef CONFIG_SMP
 245                 "       sync                                            \n"
 246 #endif
 247                 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
 248                 : "R" (*m), "Jr" (val)
 249                 : "memory");
 250         } else {
 251                 unsigned long flags;
 252
 253                 local_irq_save(flags);
 254                 retval = *m;
 255                 *m = val;
 256                 local_irq_restore(flags);       /* implies memory barrier  */
 257         }
 258
 259         return retval;
 260 }
 261 #else
 262 extern __u64 __xchg_u64_unsupported_on_32bit_kernels(volatile __u64 * m, __u64 val);
 263 #define __xchg_u64 __xchg_u64_unsupported_on_32bit_kernels
 264 #endif
 265
 266 /* This function doesn't exist, so you'll get a linker error
 267    if something tries to do an invalid xchg().  */
 268 extern void __xchg_called_with_bad_pointer(void);
 269
 270 static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
 271 {
 272         switch (size) {
 273                 case 4:
 274                         return __xchg_u32(ptr, x);
 275                 case 8:
 276                         return __xchg_u64(ptr, x);
 277         }
 278         __xchg_called_with_bad_pointer();
 279         return x;
 280 }
 281
 282 #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
 283 #define tas(ptr) (xchg((ptr),1))
 284
 285 #define __HAVE_ARCH_CMPXCHG 1
 286
 287 static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old,
 288         unsigned long new)
 289 {
 290         __u32 retval;
 291
 292         if (cpu_has_llsc && R10000_LLSC_WAR) {
 293                 __asm__ __volatile__(
 294                 "       .set    noat                                    \n"
 295                 "1:     ll      %0, %2                  # __cmpxchg_u32 \n"
 296                 "       bne     %0, %z3, 2f                             \n"
 297                 "       move    $1, %z4                                 \n"
 298                 "       sc      $1, %1                                  \n"
 299                 "       beqzl   $1, 1b                                  \n"
 300                 ROT_IN_PIECES
 301 #ifdef CONFIG_SMP
 302                 "       sync                                            \n"
 303 #endif
 304                 "2:                                                     \n"
 305                 "       .set    at                                      \n"
 306                 : "=&r" (retval), "=m" (*m)
 307                 : "R" (*m), "Jr" (old), "Jr" (new)
 308                 : "memory");
 309         } else if (cpu_has_llsc) {
 310                 __asm__ __volatile__(
 311                 "       .set    noat                                    \n"
 312                 "1:     ll      %0, %2                  # __cmpxchg_u32 \n"
 313                 "       bne     %0, %z3, 2f                             \n"
 314                 "       move    $1, %z4                                 \n"
 315                 "       sc      $1, %1                                  \n"
 316                 "       beqz    $1, 1b                                  \n"
 317 #ifdef CONFIG_SMP
 318                 "       sync                                            \n"
 319 #endif
 320                 "2:                                                     \n"
 321                 "       .set    at                                      \n"
 322                 : "=&r" (retval), "=m" (*m)
 323                 : "R" (*m), "Jr" (old), "Jr" (new)
 324                 : "memory");
 325         } else {
 326                 unsigned long flags;
 327
 328                 local_irq_save(flags);
 329                 retval = *m;
 330                 if (retval == old)
 331                         *m = new;
 332                 local_irq_restore(flags);       /* implies memory barrier  */
 333         }
 334
 335         return retval;
 336 }
 337
 338 #ifdef CONFIG_64BIT
 339 static inline unsigned long __cmpxchg_u64(volatile int * m, unsigned long old,
 340         unsigned long new)
 341 {
 342         __u64 retval;
 343
 344         if (cpu_has_llsc) {
 345                 __asm__ __volatile__(
 346                 "       .set    noat                                    \n"
 347                 "1:     lld     %0, %2                  # __cmpxchg_u64 \n"
 348                 "       bne     %0, %z3, 2f                             \n"
 349                 "       move    $1, %z4                                 \n"
 350                 "       scd     $1, %1                                  \n"
 351                 "       beqzl   $1, 1b                                  \n"
 352                 ROT_IN_PIECES
 353 #ifdef CONFIG_SMP
 354                 "       sync                                            \n"
 355 #endif
 356                 "2:                                                     \n"
 357                 "       .set    at                                      \n"
 358                 : "=&r" (retval), "=m" (*m)
 359                 : "R" (*m), "Jr" (old), "Jr" (new)
 360                 : "memory");
 361         } else if (cpu_has_llsc) {
 362                 __asm__ __volatile__(
 363                 "       .set    noat                                    \n"
 364                 "1:     lld     %0, %2                  # __cmpxchg_u64 \n"
 365                 "       bne     %0, %z3, 2f                             \n"
 366                 "       move    $1, %z4                                 \n"
 367                 "       scd     $1, %1                                  \n"
 368                 "       beqz    $1, 1b                                  \n"
 369 #ifdef CONFIG_SMP
 370                 "       sync                                            \n"
 371 #endif
 372                 "2:                                                     \n"
 373                 "       .set    at                                      \n"
 374                 : "=&r" (retval), "=m" (*m)
 375                 : "R" (*m), "Jr" (old), "Jr" (new)
 376                 : "memory");
 377         } else {
 378                 unsigned long flags;
 379
 380                 local_irq_save(flags);
 381                 retval = *m;
 382                 if (retval == old)
 383                         *m = new;
 384                 local_irq_restore(flags);       /* implies memory barrier  */
 385         }
 386
 387         return retval;
 388 }
 389 #else
 390 extern unsigned long __cmpxchg_u64_unsupported_on_32bit_kernels(
 391         volatile int * m, unsigned long old, unsigned long new);
 392 #define __cmpxchg_u64 __cmpxchg_u64_unsupported_on_32bit_kernels
 393 #endif
 394
 395 /* This function doesn't exist, so you'll get a linker error
 396    if something tries to do an invalid cmpxchg().  */
 397 extern void __cmpxchg_called_with_bad_pointer(void);
 398
 399 static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old,
 400         unsigned long new, int size)
 401 {
 402         switch (size) {
 403         case 4:
 404                 return __cmpxchg_u32(ptr, old, new);
 405         case 8:
 406                 return __cmpxchg_u64(ptr, old, new);
 407         }
 408         __cmpxchg_called_with_bad_pointer();
 409         return old;
 410 }
 411
 412 #define cmpxchg(ptr,old,new) ((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(old), (unsigned long)(new),sizeof(*(ptr))))
 413
 414 extern void *set_except_vector(int n, void *addr);
 415 extern void per_cpu_trap_init(void);
 416
 417 extern NORET_TYPE void __die(const char *, struct pt_regs *, const char *file,
 418         const char *func, unsigned long line);
 419 extern void __die_if_kernel(const char *, struct pt_regs *, const char *file,
 420         const char *func, unsigned long line);
 421
 422 #define die(msg, regs)                                                  \
 423         __die(msg, regs, __FILE__ ":", __FUNCTION__, __LINE__)
 424 #define die_if_kernel(msg, regs)                                        \
 425         __die_if_kernel(msg, regs, __FILE__ ":", __FUNCTION__, __LINE__)
 426
 427 extern int stop_a_enabled;
 428
 429 /*
 430  * See include/asm-ia64/system.h; prevents deadlock on SMP
 431  * systems.
 432  */
 433 #define __ARCH_WANT_UNLOCKED_CTXSW
 434
 435 #define arch_align_stack(x) (x)
 436
 437 #endif /* _ASM_SYSTEM_H */