include/asm-powerpc/cputable.h

   1 #ifndef __ASM_POWERPC_CPUTABLE_H
   2 #define __ASM_POWERPC_CPUTABLE_H
   3
   4 #include <asm/asm-compat.h>
   5
   6 #define PPC_FEATURE_32                  0x80000000
   7 #define PPC_FEATURE_64                  0x40000000
   8 #define PPC_FEATURE_601_INSTR           0x20000000
   9 #define PPC_FEATURE_HAS_ALTIVEC         0x10000000
  10 #define PPC_FEATURE_HAS_FPU             0x08000000
  11 #define PPC_FEATURE_HAS_MMU             0x04000000
  12 #define PPC_FEATURE_HAS_4xxMAC          0x02000000
  13 #define PPC_FEATURE_UNIFIED_CACHE       0x01000000
  14 #define PPC_FEATURE_HAS_SPE             0x00800000
  15 #define PPC_FEATURE_HAS_EFP_SINGLE      0x00400000
  16 #define PPC_FEATURE_HAS_EFP_DOUBLE      0x00200000
  17 #define PPC_FEATURE_NO_TB               0x00100000
  18 #define PPC_FEATURE_POWER4              0x00080000
  19 #define PPC_FEATURE_POWER5              0x00040000
  20 #define PPC_FEATURE_POWER5_PLUS         0x00020000
  21 #define PPC_FEATURE_CELL                0x00010000
  22
  23 #ifdef __KERNEL__
  24 #ifndef __ASSEMBLY__
  25
  26 /* This structure can grow, it's real size is used by head.S code
  27  * via the mkdefs mechanism.
  28  */
  29 struct cpu_spec;
  30 struct op_powerpc_model;
  31
  32 typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
  33
  34 struct cpu_spec {
  35         /* CPU is matched via (PVR & pvr_mask) == pvr_value */
  36         unsigned int    pvr_mask;
  37         unsigned int    pvr_value;
  38
  39         char            *cpu_name;
  40         unsigned long   cpu_features;           /* Kernel features */
  41         unsigned int    cpu_user_features;      /* Userland features */
  42
  43         /* cache line sizes */
  44         unsigned int    icache_bsize;
  45         unsigned int    dcache_bsize;
  46
  47         /* number of performance monitor counters */
  48         unsigned int    num_pmcs;
  49
  50         /* this is called to initialize various CPU bits like L1 cache,
  51          * BHT, SPD, etc... from head.S before branching to identify_machine
  52          */
  53         cpu_setup_t     cpu_setup;
  54
  55         /* Used by oprofile userspace to select the right counters */
  56         char            *oprofile_cpu_type;
  57
  58         /* Processor specific oprofile operations */
  59         struct op_powerpc_model *oprofile_model;
  60 };
  61
  62 extern struct cpu_spec          *cur_cpu_spec;
  63
  64 extern void identify_cpu(unsigned long offset, unsigned long cpu);
  65 extern void do_cpu_ftr_fixups(unsigned long offset);
  66
  67 #endif /* __ASSEMBLY__ */
  68
  69 /* CPU kernel features */
  70
  71 /* Retain the 32b definitions all use bottom half of word */
  72 #define CPU_FTR_SPLIT_ID_CACHE          ASM_CONST(0x0000000000000001)
  73 #define CPU_FTR_L2CR                    ASM_CONST(0x0000000000000002)
  74 #define CPU_FTR_SPEC7450                ASM_CONST(0x0000000000000004)
  75 #define CPU_FTR_ALTIVEC                 ASM_CONST(0x0000000000000008)
  76 #define CPU_FTR_TAU                     ASM_CONST(0x0000000000000010)
  77 #define CPU_FTR_CAN_DOZE                ASM_CONST(0x0000000000000020)
  78 #define CPU_FTR_USE_TB                  ASM_CONST(0x0000000000000040)
  79 #define CPU_FTR_604_PERF_MON            ASM_CONST(0x0000000000000080)
  80 #define CPU_FTR_601                     ASM_CONST(0x0000000000000100)
  81 #define CPU_FTR_HPTE_TABLE              ASM_CONST(0x0000000000000200)
  82 #define CPU_FTR_CAN_NAP                 ASM_CONST(0x0000000000000400)
  83 #define CPU_FTR_L3CR                    ASM_CONST(0x0000000000000800)
  84 #define CPU_FTR_L3_DISABLE_NAP          ASM_CONST(0x0000000000001000)
  85 #define CPU_FTR_NAP_DISABLE_L2_PR       ASM_CONST(0x0000000000002000)
  86 #define CPU_FTR_DUAL_PLL_750FX          ASM_CONST(0x0000000000004000)
  87 #define CPU_FTR_NO_DPM                  ASM_CONST(0x0000000000008000)
  88 #define CPU_FTR_HAS_HIGH_BATS           ASM_CONST(0x0000000000010000)
  89 #define CPU_FTR_NEED_COHERENT           ASM_CONST(0x0000000000020000)
  90 #define CPU_FTR_NO_BTIC                 ASM_CONST(0x0000000000040000)
  91 #define CPU_FTR_BIG_PHYS                ASM_CONST(0x0000000000080000)
  92 #define CPU_FTR_NODSISRALIGN            ASM_CONST(0x0000000000100000)
  93
  94 #ifdef __powerpc64__
  95 /* Add the 64b processor unique features in the top half of the word */
  96 #define CPU_FTR_SLB                     ASM_CONST(0x0000000100000000)
  97 #define CPU_FTR_16M_PAGE                ASM_CONST(0x0000000200000000)
  98 #define CPU_FTR_TLBIEL                  ASM_CONST(0x0000000400000000)
  99 #define CPU_FTR_NOEXECUTE               ASM_CONST(0x0000000800000000)
 100 #define CPU_FTR_IABR                    ASM_CONST(0x0000002000000000)
 101 #define CPU_FTR_MMCRA                   ASM_CONST(0x0000004000000000)
 102 #define CPU_FTR_CTRL                    ASM_CONST(0x0000008000000000)
 103 #define CPU_FTR_SMT                     ASM_CONST(0x0000010000000000)
 104 #define CPU_FTR_COHERENT_ICACHE         ASM_CONST(0x0000020000000000)
 105 #define CPU_FTR_LOCKLESS_TLBIE          ASM_CONST(0x0000040000000000)
 106 #define CPU_FTR_MMCRA_SIHV              ASM_CONST(0x0000080000000000)
 107 #define CPU_FTR_CI_LARGE_PAGE           ASM_CONST(0x0000100000000000)
 108 #else
 109 /* ensure on 32b processors the flags are available for compiling but
 110  * don't do anything */
 111 #define CPU_FTR_SLB                     ASM_CONST(0x0)
 112 #define CPU_FTR_16M_PAGE                ASM_CONST(0x0)
 113 #define CPU_FTR_TLBIEL                  ASM_CONST(0x0)
 114 #define CPU_FTR_NOEXECUTE               ASM_CONST(0x0)
 115 #define CPU_FTR_IABR                    ASM_CONST(0x0)
 116 #define CPU_FTR_MMCRA                   ASM_CONST(0x0)
 117 #define CPU_FTR_CTRL                    ASM_CONST(0x0)
 118 #define CPU_FTR_SMT                     ASM_CONST(0x0)
 119 #define CPU_FTR_COHERENT_ICACHE         ASM_CONST(0x0)
 120 #define CPU_FTR_LOCKLESS_TLBIE          ASM_CONST(0x0)
 121 #define CPU_FTR_MMCRA_SIHV              ASM_CONST(0x0)
 122 #define CPU_FTR_CI_LARGE_PAGE           ASM_CONST(0x0)
 123 #endif
 124
 125 #ifndef __ASSEMBLY__
 126
 127 #define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \
 128                                         CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
 129                                         CPU_FTR_NODSISRALIGN | CPU_FTR_CTRL)
 130
 131 /* iSeries doesn't support large pages */
 132 #ifdef CONFIG_PPC_ISERIES
 133 #define CPU_FTR_PPCAS_ARCH_V2   (CPU_FTR_PPCAS_ARCH_V2_BASE)
 134 #else
 135 #define CPU_FTR_PPCAS_ARCH_V2   (CPU_FTR_PPCAS_ARCH_V2_BASE | CPU_FTR_16M_PAGE)
 136 #endif /* CONFIG_PPC_ISERIES */
 137
 138 /* We only set the altivec features if the kernel was compiled with altivec
 139  * support
 140  */
 141 #ifdef CONFIG_ALTIVEC
 142 #define CPU_FTR_ALTIVEC_COMP    CPU_FTR_ALTIVEC
 143 #define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
 144 #else
 145 #define CPU_FTR_ALTIVEC_COMP    0
 146 #define PPC_FEATURE_HAS_ALTIVEC_COMP    0
 147 #endif
 148
 149 /* We need to mark all pages as being coherent if we're SMP or we
 150  * have a 74[45]x and an MPC107 host bridge.
 151  */
 152 #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE)
 153 #define CPU_FTR_COMMON                  CPU_FTR_NEED_COHERENT
 154 #else
 155 #define CPU_FTR_COMMON                  0
 156 #endif
 157
 158 /* The powersave features NAP & DOZE seems to confuse BDI when
 159    debugging. So if a BDI is used, disable theses
 160  */
 161 #ifndef CONFIG_BDI_SWITCH
 162 #define CPU_FTR_MAYBE_CAN_DOZE  CPU_FTR_CAN_DOZE
 163 #define CPU_FTR_MAYBE_CAN_NAP   CPU_FTR_CAN_NAP
 164 #else
 165 #define CPU_FTR_MAYBE_CAN_DOZE  0
 166 #define CPU_FTR_MAYBE_CAN_NAP   0
 167 #endif
 168
 169 #define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
 170                      !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
 171                      !defined(CONFIG_BOOKE))
 172
 173 enum {
 174         CPU_FTRS_PPC601 = CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE,
 175         CPU_FTRS_603 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
 176             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
 177             CPU_FTR_MAYBE_CAN_NAP,
 178         CPU_FTRS_604 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
 179             CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
 180         CPU_FTRS_740_NOTAU = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
 181             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
 182             CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
 183         CPU_FTRS_740 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
 184             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
 185             CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
 186         CPU_FTRS_750 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
 187             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
 188             CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
 189         CPU_FTRS_750FX1 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
 190             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
 191             CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
 192             CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM,
 193         CPU_FTRS_750FX2 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
 194             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
 195             CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
 196             CPU_FTR_NO_DPM,
 197         CPU_FTRS_750FX = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
 198             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
 199             CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
 200             CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
 201         CPU_FTRS_750GX = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
 202             CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
 203             CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
 204             CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
 205         CPU_FTRS_7400_NOTAU = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
 206             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
 207             CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
 208             CPU_FTR_MAYBE_CAN_NAP,
 209         CPU_FTRS_7400 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
 210             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
 211             CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
 212             CPU_FTR_MAYBE_CAN_NAP,
 213         CPU_FTRS_7450_20 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
 214             CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
 215             CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
 216             CPU_FTR_NEED_COHERENT,
 217         CPU_FTRS_7450_21 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
 218             CPU_FTR_USE_TB |
 219             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
 220             CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
 221             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
 222             CPU_FTR_NEED_COHERENT,
 223         CPU_FTRS_7450_23 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
 224             CPU_FTR_USE_TB |
 225             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
 226             CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
 227             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT,
 228         CPU_FTRS_7455_1 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
 229             CPU_FTR_USE_TB |
 230             CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 231             CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS |
 232             CPU_FTR_NEED_COHERENT,
 233         CPU_FTRS_7455_20 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
 234             CPU_FTR_USE_TB |
 235             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
 236             CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
 237             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
 238             CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS,
 239         CPU_FTRS_7455 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
 240             CPU_FTR_USE_TB |
 241             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
 242             CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
 243             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
 244             CPU_FTR_NEED_COHERENT,
 245         CPU_FTRS_7447_10 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
 246             CPU_FTR_USE_TB |
 247             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
 248             CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
 249             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
 250             CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
 251         CPU_FTRS_7447 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
 252             CPU_FTR_USE_TB |
 253             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
 254             CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
 255             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
 256             CPU_FTR_NEED_COHERENT,
 257         CPU_FTRS_7447A = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
 258             CPU_FTR_USE_TB |
 259             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
 260             CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
 261             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
 262             CPU_FTR_NEED_COHERENT,
 263         CPU_FTRS_82XX = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
 264             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB,
 265         CPU_FTRS_G2_LE = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
 266             CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
 267         CPU_FTRS_E300 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
 268             CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
 269         CPU_FTRS_CLASSIC32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
 270             CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
 271         CPU_FTRS_POWER3_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
 272             CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
 273         CPU_FTRS_POWER4_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
 274             CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_NODSISRALIGN,
 275         CPU_FTRS_970_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
 276             CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_ALTIVEC_COMP |
 277             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN,
 278         CPU_FTRS_8XX = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
 279         CPU_FTRS_40X = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
 280             CPU_FTR_NODSISRALIGN,
 281         CPU_FTRS_44X = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
 282             CPU_FTR_NODSISRALIGN,
 283         CPU_FTRS_E200 = CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN,
 284         CPU_FTRS_E500 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
 285             CPU_FTR_NODSISRALIGN,
 286         CPU_FTRS_E500_2 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
 287             CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN,
 288         CPU_FTRS_GENERIC_32 = CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN,
 289 #ifdef __powerpc64__
 290         CPU_FTRS_POWER3 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
 291             CPU_FTR_HPTE_TABLE | CPU_FTR_IABR,
 292         CPU_FTRS_RS64 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
 293             CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
 294             CPU_FTR_MMCRA | CPU_FTR_CTRL,
 295         CPU_FTRS_POWER4 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
 296             CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA,
 297         CPU_FTRS_PPC970 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
 298             CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
 299             CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA,
 300         CPU_FTRS_POWER5 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
 301             CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
 302             CPU_FTR_MMCRA | CPU_FTR_SMT |
 303             CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE |
 304             CPU_FTR_MMCRA_SIHV,
 305         CPU_FTRS_CELL = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
 306             CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
 307             CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT,
 308         CPU_FTRS_COMPATIBLE = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
 309             CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2,
 310 #endif
 311
 312         CPU_FTRS_POSSIBLE =
 313 #ifdef __powerpc64__
 314             CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 |
 315             CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_CELL |
 316             CPU_FTR_CI_LARGE_PAGE |
 317 #else
 318 #if CLASSIC_PPC
 319             CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
 320             CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
 321             CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
 322             CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
 323             CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
 324             CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
 325             CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
 326             CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_CLASSIC32 |
 327 #else
 328             CPU_FTRS_GENERIC_32 |
 329 #endif
 330 #ifdef CONFIG_PPC64BRIDGE
 331             CPU_FTRS_POWER3_32 |
 332 #endif
 333 #ifdef CONFIG_POWER4
 334             CPU_FTRS_POWER4_32 | CPU_FTRS_970_32 |
 335 #endif
 336 #ifdef CONFIG_8xx
 337             CPU_FTRS_8XX |
 338 #endif
 339 #ifdef CONFIG_40x
 340             CPU_FTRS_40X |
 341 #endif
 342 #ifdef CONFIG_44x
 343             CPU_FTRS_44X |
 344 #endif
 345 #ifdef CONFIG_E200
 346             CPU_FTRS_E200 |
 347 #endif
 348 #ifdef CONFIG_E500
 349             CPU_FTRS_E500 | CPU_FTRS_E500_2 |
 350 #endif
 351 #endif /* __powerpc64__ */
 352             0,
 353
 354         CPU_FTRS_ALWAYS =
 355 #ifdef __powerpc64__
 356             CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 &
 357             CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_CELL &
 358 #else
 359 #if CLASSIC_PPC
 360             CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
 361             CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
 362             CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
 363             CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
 364             CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
 365             CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
 366             CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
 367             CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_CLASSIC32 &
 368 #else
 369             CPU_FTRS_GENERIC_32 &
 370 #endif
 371 #ifdef CONFIG_PPC64BRIDGE
 372             CPU_FTRS_POWER3_32 &
 373 #endif
 374 #ifdef CONFIG_POWER4
 375             CPU_FTRS_POWER4_32 & CPU_FTRS_970_32 &
 376 #endif
 377 #ifdef CONFIG_8xx
 378             CPU_FTRS_8XX &
 379 #endif
 380 #ifdef CONFIG_40x
 381             CPU_FTRS_40X &
 382 #endif
 383 #ifdef CONFIG_44x
 384             CPU_FTRS_44X &
 385 #endif
 386 #ifdef CONFIG_E200
 387             CPU_FTRS_E200 &
 388 #endif
 389 #ifdef CONFIG_E500
 390             CPU_FTRS_E500 & CPU_FTRS_E500_2 &
 391 #endif
 392 #endif /* __powerpc64__ */
 393             CPU_FTRS_POSSIBLE,
 394 };
 395
 396 static inline int cpu_has_feature(unsigned long feature)
 397 {
 398         return (CPU_FTRS_ALWAYS & feature) ||
 399                (CPU_FTRS_POSSIBLE
 400                 & cur_cpu_spec->cpu_features
 401                 & feature);
 402 }
 403
 404 #endif /* !__ASSEMBLY__ */
 405
 406 #ifdef __ASSEMBLY__
 407
 408 #define BEGIN_FTR_SECTION               98:
 409
 410 #ifndef __powerpc64__
 411 #define END_FTR_SECTION(msk, val)               \
 412 99:                                             \
 413         .section __ftr_fixup,"a";               \
 414         .align 2;                               \
 415         .long msk;                              \
 416         .long val;                              \
 417         .long 98b;                              \
 418         .long 99b;                              \
 419         .previous
 420 #else /* __powerpc64__ */
 421 #define END_FTR_SECTION(msk, val)               \
 422 99:                                             \
 423         .section __ftr_fixup,"a";               \
 424         .align 3;                               \
 425         .llong msk;                             \
 426         .llong val;                             \
 427         .llong 98b;                             \
 428         .llong 99b;                             \
 429         .previous
 430 #endif /* __powerpc64__ */
 431
 432 #define END_FTR_SECTION_IFSET(msk)      END_FTR_SECTION((msk), (msk))
 433 #define END_FTR_SECTION_IFCLR(msk)      END_FTR_SECTION((msk), 0)
 434 #endif /* __ASSEMBLY__ */
 435
 436 #endif /* __KERNEL__ */
 437 #endif /* __ASM_POWERPC_CPUTABLE_H */