include/asm-powerpc/mpc52xx.h

   1 /*
   2  * Prototypes, etc. for the Freescale MPC52xx embedded cpu chips
   3  * May need to be cleaned as the port goes on ...
   4  *
   5  * Copyright (C) 2004-2005 Sylvain Munaut <tnt@246tNt.com>
   6  * Copyright (C) 2003 MontaVista, Software, Inc.
   7  *
   8  * This file is licensed under the terms of the GNU General Public License
   9  * version 2. This program is licensed "as is" without any warranty of any
  10  * kind, whether express or implied.
  11  */
  12
  13 #ifndef __ASM_POWERPC_MPC52xx_H__
  14 #define __ASM_POWERPC_MPC52xx_H__
  15
  16 #ifndef __ASSEMBLY__
  17 #include <asm/types.h>
  18 #include <asm/prom.h>
  19 #endif /* __ASSEMBLY__ */
  20
  21
  22 /* ======================================================================== */
  23 /* HW IRQ mapping                                                           */
  24 /* ======================================================================== */
  25
  26 #define MPC52xx_IRQ_L1_CRIT             (0)
  27 #define MPC52xx_IRQ_L1_MAIN             (1)
  28 #define MPC52xx_IRQ_L1_PERP             (2)
  29 #define MPC52xx_IRQ_L1_SDMA             (3)
  30
  31 #define MPC52xx_IRQ_L1_OFFSET           (6)
  32 #define MPC52xx_IRQ_L1_MASK             (0xc0)
  33
  34 #define MPC52xx_IRQ_L2_OFFSET           (0)
  35 #define MPC52xx_IRQ_L2_MASK             (0x3f)
  36
  37 #define MPC52xx_IRQ_HIGHTESTHWIRQ       (0xd0)
  38
  39
  40 /* ======================================================================== */
  41 /* Structures mapping of some unit register set                             */
  42 /* ======================================================================== */
  43
  44 #ifndef __ASSEMBLY__
  45
  46 /* Interrupt controller Register set */
  47 struct mpc52xx_intr {
  48         u32 per_mask;           /* INTR + 0x00 */
  49         u32 per_pri1;           /* INTR + 0x04 */
  50         u32 per_pri2;           /* INTR + 0x08 */
  51         u32 per_pri3;           /* INTR + 0x0c */
  52         u32 ctrl;               /* INTR + 0x10 */
  53         u32 main_mask;          /* INTR + 0x14 */
  54         u32 main_pri1;          /* INTR + 0x18 */
  55         u32 main_pri2;          /* INTR + 0x1c */
  56         u32 reserved1;          /* INTR + 0x20 */
  57         u32 enc_status;         /* INTR + 0x24 */
  58         u32 crit_status;        /* INTR + 0x28 */
  59         u32 main_status;        /* INTR + 0x2c */
  60         u32 per_status;         /* INTR + 0x30 */
  61         u32 reserved2;          /* INTR + 0x34 */
  62         u32 per_error;          /* INTR + 0x38 */
  63 };
  64
  65 /* Memory Mapping Control */
  66 struct mpc52xx_mmap_ctl {
  67         u32 mbar;               /* MMAP_CTRL + 0x00 */
  68
  69         u32 cs0_start;          /* MMAP_CTRL + 0x04 */
  70         u32 cs0_stop;           /* MMAP_CTRL + 0x08 */
  71         u32 cs1_start;          /* MMAP_CTRL + 0x0c */
  72         u32 cs1_stop;           /* MMAP_CTRL + 0x10 */
  73         u32 cs2_start;          /* MMAP_CTRL + 0x14 */
  74         u32 cs2_stop;           /* MMAP_CTRL + 0x18 */
  75         u32 cs3_start;          /* MMAP_CTRL + 0x1c */
  76         u32 cs3_stop;           /* MMAP_CTRL + 0x20 */
  77         u32 cs4_start;          /* MMAP_CTRL + 0x24 */
  78         u32 cs4_stop;           /* MMAP_CTRL + 0x28 */
  79         u32 cs5_start;          /* MMAP_CTRL + 0x2c */
  80         u32 cs5_stop;           /* MMAP_CTRL + 0x30 */
  81
  82         u32 sdram0;             /* MMAP_CTRL + 0x34 */
  83         u32 sdram1;             /* MMAP_CTRL + 0X38 */
  84
  85         u32 reserved[4];        /* MMAP_CTRL + 0x3c .. 0x48 */
  86
  87         u32 boot_start;         /* MMAP_CTRL + 0x4c */
  88         u32 boot_stop;          /* MMAP_CTRL + 0x50 */
  89
  90         u32 ipbi_ws_ctrl;       /* MMAP_CTRL + 0x54 */
  91
  92         u32 cs6_start;          /* MMAP_CTRL + 0x58 */
  93         u32 cs6_stop;           /* MMAP_CTRL + 0x5c */
  94         u32 cs7_start;          /* MMAP_CTRL + 0x60 */
  95         u32 cs7_stop;           /* MMAP_CTRL + 0x64 */
  96 };
  97
  98 /* SDRAM control */
  99 struct mpc52xx_sdram {
 100         u32 mode;               /* SDRAM + 0x00 */
 101         u32 ctrl;               /* SDRAM + 0x04 */
 102         u32 config1;            /* SDRAM + 0x08 */
 103         u32 config2;            /* SDRAM + 0x0c */
 104 };
 105
 106 /* SDMA */
 107 struct mpc52xx_sdma {
 108         u32 taskBar;            /* SDMA + 0x00 */
 109         u32 currentPointer;     /* SDMA + 0x04 */
 110         u32 endPointer;         /* SDMA + 0x08 */
 111         u32 variablePointer;    /* SDMA + 0x0c */
 112
 113         u8 IntVect1;            /* SDMA + 0x10 */
 114         u8 IntVect2;            /* SDMA + 0x11 */
 115         u16 PtdCntrl;           /* SDMA + 0x12 */
 116
 117         u32 IntPend;            /* SDMA + 0x14 */
 118         u32 IntMask;            /* SDMA + 0x18 */
 119
 120         u16 tcr[16];            /* SDMA + 0x1c .. 0x3a */
 121
 122         u8 ipr[32];             /* SDMA + 0x3c .. 0x5b */
 123
 124         u32 cReqSelect;         /* SDMA + 0x5c */
 125         u32 task_size0;         /* SDMA + 0x60 */
 126         u32 task_size1;         /* SDMA + 0x64 */
 127         u32 MDEDebug;           /* SDMA + 0x68 */
 128         u32 ADSDebug;           /* SDMA + 0x6c */
 129         u32 Value1;             /* SDMA + 0x70 */
 130         u32 Value2;             /* SDMA + 0x74 */
 131         u32 Control;            /* SDMA + 0x78 */
 132         u32 Status;             /* SDMA + 0x7c */
 133         u32 PTDDebug;           /* SDMA + 0x80 */
 134 };
 135
 136 /* GPT */
 137 struct mpc52xx_gpt {
 138         u32 mode;               /* GPTx + 0x00 */
 139         u32 count;              /* GPTx + 0x04 */
 140         u32 pwm;                /* GPTx + 0x08 */
 141         u32 status;             /* GPTx + 0X0c */
 142 };
 143
 144 /* GPIO */
 145 struct mpc52xx_gpio {
 146         u32 port_config;        /* GPIO + 0x00 */
 147         u32 simple_gpioe;       /* GPIO + 0x04 */
 148         u32 simple_ode;         /* GPIO + 0x08 */
 149         u32 simple_ddr;         /* GPIO + 0x0c */
 150         u32 simple_dvo;         /* GPIO + 0x10 */
 151         u32 simple_ival;        /* GPIO + 0x14 */
 152         u8 outo_gpioe;          /* GPIO + 0x18 */
 153         u8 reserved1[3];        /* GPIO + 0x19 */
 154         u8 outo_dvo;            /* GPIO + 0x1c */
 155         u8 reserved2[3];        /* GPIO + 0x1d */
 156         u8 sint_gpioe;          /* GPIO + 0x20 */
 157         u8 reserved3[3];        /* GPIO + 0x21 */
 158         u8 sint_ode;            /* GPIO + 0x24 */
 159         u8 reserved4[3];        /* GPIO + 0x25 */
 160         u8 sint_ddr;            /* GPIO + 0x28 */
 161         u8 reserved5[3];        /* GPIO + 0x29 */
 162         u8 sint_dvo;            /* GPIO + 0x2c */
 163         u8 reserved6[3];        /* GPIO + 0x2d */
 164         u8 sint_inten;          /* GPIO + 0x30 */
 165         u8 reserved7[3];        /* GPIO + 0x31 */
 166         u16 sint_itype;         /* GPIO + 0x34 */
 167         u16 reserved8;          /* GPIO + 0x36 */
 168         u8 gpio_control;        /* GPIO + 0x38 */
 169         u8 reserved9[3];        /* GPIO + 0x39 */
 170         u8 sint_istat;          /* GPIO + 0x3c */
 171         u8 sint_ival;           /* GPIO + 0x3d */
 172         u8 bus_errs;            /* GPIO + 0x3e */
 173         u8 reserved10;          /* GPIO + 0x3f */
 174 };
 175
 176 #define MPC52xx_GPIO_PSC_CONFIG_UART_WITHOUT_CD 4
 177 #define MPC52xx_GPIO_PSC_CONFIG_UART_WITH_CD    5
 178 #define MPC52xx_GPIO_PCI_DIS                    (1<<15)
 179
 180 /* GPIO with WakeUp*/
 181 struct mpc52xx_gpio_wkup {
 182         u8 wkup_gpioe;          /* GPIO_WKUP + 0x00 */
 183         u8 reserved1[3];        /* GPIO_WKUP + 0x03 */
 184         u8 wkup_ode;            /* GPIO_WKUP + 0x04 */
 185         u8 reserved2[3];        /* GPIO_WKUP + 0x05 */
 186         u8 wkup_ddr;            /* GPIO_WKUP + 0x08 */
 187         u8 reserved3[3];        /* GPIO_WKUP + 0x09 */
 188         u8 wkup_dvo;            /* GPIO_WKUP + 0x0C */
 189         u8 reserved4[3];        /* GPIO_WKUP + 0x0D */
 190         u8 wkup_inten;          /* GPIO_WKUP + 0x10 */
 191         u8 reserved5[3];        /* GPIO_WKUP + 0x11 */
 192         u8 wkup_iinten;         /* GPIO_WKUP + 0x14 */
 193         u8 reserved6[3];        /* GPIO_WKUP + 0x15 */
 194         u16 wkup_itype;         /* GPIO_WKUP + 0x18 */
 195         u8 reserved7[2];        /* GPIO_WKUP + 0x1A */
 196         u8 wkup_maste;          /* GPIO_WKUP + 0x1C */
 197         u8 reserved8[3];        /* GPIO_WKUP + 0x1D */
 198         u8 wkup_ival;           /* GPIO_WKUP + 0x20 */
 199         u8 reserved9[3];        /* GPIO_WKUP + 0x21 */
 200         u8 wkup_istat;          /* GPIO_WKUP + 0x24 */
 201         u8 reserved10[3];       /* GPIO_WKUP + 0x25 */
 202 };
 203
 204 /* XLB Bus control */
 205 struct mpc52xx_xlb {
 206         u8 reserved[0x40];
 207         u32 config;             /* XLB + 0x40 */
 208         u32 version;            /* XLB + 0x44 */
 209         u32 status;             /* XLB + 0x48 */
 210         u32 int_enable;         /* XLB + 0x4c */
 211         u32 addr_capture;       /* XLB + 0x50 */
 212         u32 bus_sig_capture;    /* XLB + 0x54 */
 213         u32 addr_timeout;       /* XLB + 0x58 */
 214         u32 data_timeout;       /* XLB + 0x5c */
 215         u32 bus_act_timeout;    /* XLB + 0x60 */
 216         u32 master_pri_enable;  /* XLB + 0x64 */
 217         u32 master_priority;    /* XLB + 0x68 */
 218         u32 base_address;       /* XLB + 0x6c */
 219         u32 snoop_window;       /* XLB + 0x70 */
 220 };
 221
 222 #define MPC52xx_XLB_CFG_PLDIS           (1 << 31)
 223 #define MPC52xx_XLB_CFG_SNOOP           (1 << 15)
 224
 225 /* Clock Distribution control */
 226 struct mpc52xx_cdm {
 227         u32 jtag_id;            /* CDM + 0x00  reg0 read only */
 228         u32 rstcfg;             /* CDM + 0x04  reg1 read only */
 229         u32 breadcrumb;         /* CDM + 0x08  reg2 */
 230
 231         u8 mem_clk_sel;         /* CDM + 0x0c  reg3 byte0 */
 232         u8 xlb_clk_sel;         /* CDM + 0x0d  reg3 byte1 read only */
 233         u8 ipb_clk_sel;         /* CDM + 0x0e  reg3 byte2 */
 234         u8 pci_clk_sel;         /* CDM + 0x0f  reg3 byte3 */
 235
 236         u8 ext_48mhz_en;        /* CDM + 0x10  reg4 byte0 */
 237         u8 fd_enable;           /* CDM + 0x11  reg4 byte1 */
 238         u16 fd_counters;        /* CDM + 0x12  reg4 byte2,3 */
 239
 240         u32 clk_enables;        /* CDM + 0x14  reg5 */
 241
 242         u8 osc_disable;         /* CDM + 0x18  reg6 byte0 */
 243         u8 reserved0[3];        /* CDM + 0x19  reg6 byte1,2,3 */
 244
 245         u8 ccs_sleep_enable;    /* CDM + 0x1c  reg7 byte0 */
 246         u8 osc_sleep_enable;    /* CDM + 0x1d  reg7 byte1 */
 247         u8 reserved1;           /* CDM + 0x1e  reg7 byte2 */
 248         u8 ccs_qreq_test;       /* CDM + 0x1f  reg7 byte3 */
 249
 250         u8 soft_reset;          /* CDM + 0x20  u8 byte0 */
 251         u8 no_ckstp;            /* CDM + 0x21  u8 byte0 */
 252         u8 reserved2[2];        /* CDM + 0x22  u8 byte1,2,3 */
 253
 254         u8 pll_lock;            /* CDM + 0x24  reg9 byte0 */
 255         u8 pll_looselock;       /* CDM + 0x25  reg9 byte1 */
 256         u8 pll_sm_lockwin;      /* CDM + 0x26  reg9 byte2 */
 257         u8 reserved3;           /* CDM + 0x27  reg9 byte3 */
 258
 259         u16 reserved4;          /* CDM + 0x28  reg10 byte0,1 */
 260         u16 mclken_div_psc1;    /* CDM + 0x2a  reg10 byte2,3 */
 261
 262         u16 reserved5;          /* CDM + 0x2c  reg11 byte0,1 */
 263         u16 mclken_div_psc2;    /* CDM + 0x2e  reg11 byte2,3 */
 264
 265         u16 reserved6;          /* CDM + 0x30  reg12 byte0,1 */
 266         u16 mclken_div_psc3;    /* CDM + 0x32  reg12 byte2,3 */
 267
 268         u16 reserved7;          /* CDM + 0x34  reg13 byte0,1 */
 269         u16 mclken_div_psc6;    /* CDM + 0x36  reg13 byte2,3 */
 270 };
 271
 272 #endif /* __ASSEMBLY__ */
 273
 274
 275 /* ========================================================================= */
 276 /* Prototypes for MPC52xx sysdev                                             */
 277 /* ========================================================================= */
 278
 279 #ifndef __ASSEMBLY__
 280
 281 extern void mpc52xx_init_irq(void);
 282 extern unsigned int mpc52xx_get_irq(void);
 283
 284 #endif /* __ASSEMBLY__ */
 285
 286 #endif /* __ASM_POWERPC_MPC52xx_H__ */
 287