6 * linux/include/asm-sh/irq.h
8 * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
9 * Copyright (C) 2000 Kazumoto Kojima
10 * Copyright (C) 2003 Paul Mundt
14 #include <asm/machvec.h>
15 #include <asm/ptrace.h> /* for pt_regs */
17 #if defined(CONFIG_SH_HP6XX) || \
18 defined(CONFIG_SH_RTS7751R2D) || \
19 defined(CONFIG_SH_HS7751RVOIP) || \
20 defined(CONFIG_SH_HS7751RVOIP) || \
21 defined(CONFIG_SH_SH03) || \
22 defined(CONFIG_SH_R7780RP) || \
23 defined(CONFIG_SH_LANDISK)
24 #include <asm/mach/ide.h>
27 #ifndef CONFIG_CPU_SUBTYPE_SH7780
29 #define INTC_DMAC0_MSK 0
31 #if defined(CONFIG_CPU_SH3)
32 #define INTC_IPRA 0xfffffee2UL
33 #define INTC_IPRB 0xfffffee4UL
34 #elif defined(CONFIG_CPU_SH4)
35 #define INTC_IPRA 0xffd00004UL
36 #define INTC_IPRB 0xffd00008UL
37 #define INTC_IPRC 0xffd0000cUL
38 #define INTC_IPRD 0xffd00010UL
43 # define IRQ_CFCARD 14
46 # define IRQ_PCMCIA 15
51 #define TIMER_IPR_ADDR INTC_IPRA
52 #define TIMER_IPR_POS 3
53 #define TIMER_PRIORITY 2
56 #define TIMER1_IPR_ADDR INTC_IPRA
57 #define TIMER1_IPR_POS 2
58 #define TIMER1_PRIORITY 4
61 #define RTC_IPR_ADDR INTC_IPRA
63 #define RTC_PRIORITY TIMER_PRIORITY
65 #if defined(CONFIG_CPU_SH3)
70 #define DMA_IPR_ADDR INTC_IPRE
72 #define DMA_PRIORITY 7
73 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
76 #define TIMER2_IPR_ADDR INTC_IPRA
77 #define TIMER2_IPR_POS 1
78 #define TIMER2_PRIORITY 2
82 #define WDT_IPR_ADDR INTC_IPRB
84 #define WDT_PRIORITY 2
86 /* SIM (SIM Card Module) */
87 #define SIM_ERI_IRQ 23
88 #define SIM_RXI_IRQ 24
89 #define SIM_TXI_IRQ 25
90 #define SIM_TEND_IRQ 26
91 #define SIM_IPR_ADDR INTC_IPRB
93 #define SIM_PRIORITY 2
97 #define VIO_IPR_ADDR INTC_IPRE
99 #define VIO_PRIORITY 2
101 /* MFI (Multi Functional Interface) */
103 #define MFI_IPR_ADDR INTC_IPRE
104 #define MFI_IPR_POS 1
105 #define MFI_PRIORITY 2
107 /* VPU (Video Processing Unit) */
109 #define VPU_IPR_ADDR INTC_IPRE
110 #define VPU_IPR_POS 0
111 #define VPU_PRIORITY 2
113 /* KEY (Key Scan Interface) */
115 #define KEY_IPR_ADDR INTC_IPRF
116 #define KEY_IPR_POS 3
117 #define KEY_PRIORITY 2
119 /* CMT (Compare Match Timer) */
121 #define CMT_IPR_ADDR INTC_IPRF
122 #define CMT_IPR_POS 0
123 #define CMT_PRIORITY 2
130 #define DMA1_IPR_ADDR INTC_IPRE
131 #define DMA1_IPR_POS 3
132 #define DMA1_PRIORITY 7
137 #define DMA2_IPR_ADDR INTC_IPRF
138 #define DMA2_IPR_POS 2
139 #define DMA2_PRIORITY 7
143 #define SIOF0_IPR_ADDR INTC_IPRH
144 #define SIOF0_IPR_POS 3
145 #define SIOF0_PRIORITY 3
147 /* FLCTL (Flash Memory Controller) */
149 #define FLTEND_IRQ 93
150 #define FLTRQ0_IRQ 94
151 #define FLTRQ1_IRQ 95
152 #define FLCTL_IPR_ADDR INTC_IPRH
153 #define FLCTL_IPR_POS 1
154 #define FLCTL_PRIORITY 3
156 /* IIC (IIC Bus Interface) */
157 #define IIC_ALI_IRQ 96
158 #define IIC_TACKI_IRQ 97
159 #define IIC_WAITI_IRQ 98
160 #define IIC_DTEI_IRQ 99
161 #define IIC_IPR_ADDR INTC_IPRH
162 #define IIC_IPR_POS 0
163 #define IIC_PRIORITY 3
167 #define SIO0_IPR_ADDR INTC_IPRI
168 #define SIO0_IPR_POS 3
169 #define SIO0_PRIORITY 3
171 /* SIU (Sound Interface Unit) */
173 #define SIU_IPR_ADDR INTC_IPRJ
174 #define SIU_IPR_POS 1
175 #define SIU_PRIORITY 3
178 #elif defined(CONFIG_CPU_SH4)
183 #define DMTE4_IRQ 44 /* 7751R only */
184 #define DMTE5_IRQ 45 /* 7751R only */
185 #define DMTE6_IRQ 46 /* 7751R only */
186 #define DMTE7_IRQ 47 /* 7751R only */
188 #define DMA_IPR_ADDR INTC_IPRC
189 #define DMA_IPR_POS 2
190 #define DMA_PRIORITY 7
193 #if defined (CONFIG_CPU_SUBTYPE_SH7707) || defined (CONFIG_CPU_SUBTYPE_SH7708) || \
194 defined (CONFIG_CPU_SUBTYPE_SH7709) || defined (CONFIG_CPU_SUBTYPE_SH7750) || \
195 defined (CONFIG_CPU_SUBTYPE_SH7751) || defined (CONFIG_CPU_SUBTYPE_SH7706)
196 #define SCI_ERI_IRQ 23
197 #define SCI_RXI_IRQ 24
198 #define SCI_TXI_IRQ 25
199 #define SCI_IPR_ADDR INTC_IPRB
200 #define SCI_IPR_POS 1
201 #define SCI_PRIORITY 3
204 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
206 #define SCIF0_IPR_ADDR INTC_IPRG
207 #define SCIF0_IPR_POS 3
208 #define SCIF0_PRIORITY 3
209 #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
210 defined(CONFIG_CPU_SUBTYPE_SH7706) || \
211 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
212 defined(CONFIG_CPU_SUBTYPE_SH7709)
213 #define SCIF_ERI_IRQ 56
214 #define SCIF_RXI_IRQ 57
215 #define SCIF_BRI_IRQ 58
216 #define SCIF_TXI_IRQ 59
217 #define SCIF_IPR_ADDR INTC_IPRE
218 #define SCIF_IPR_POS 1
219 #define SCIF_PRIORITY 3
221 #define IRDA_ERI_IRQ 52
222 #define IRDA_RXI_IRQ 53
223 #define IRDA_BRI_IRQ 54
224 #define IRDA_TXI_IRQ 55
225 #define IRDA_IPR_ADDR INTC_IPRE
226 #define IRDA_IPR_POS 2
227 #define IRDA_PRIORITY 3
228 #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \
229 defined(CONFIG_CPU_SUBTYPE_ST40STB1) || defined(CONFIG_CPU_SUBTYPE_SH4_202)
230 #define SCIF_ERI_IRQ 40
231 #define SCIF_RXI_IRQ 41
232 #define SCIF_BRI_IRQ 42
233 #define SCIF_TXI_IRQ 43
234 #define SCIF_IPR_ADDR INTC_IPRC
235 #define SCIF_IPR_POS 1
236 #define SCIF_PRIORITY 3
237 #if defined(CONFIG_CPU_SUBTYPE_ST40STB1)
238 #define SCIF1_ERI_IRQ 23
239 #define SCIF1_RXI_IRQ 24
240 #define SCIF1_BRI_IRQ 25
241 #define SCIF1_TXI_IRQ 26
242 #define SCIF1_IPR_ADDR INTC_IPRB
243 #define SCIF1_IPR_POS 1
244 #define SCIF1_PRIORITY 3
245 #endif /* ST40STB1 */
247 #endif /* 775x / SH4-202 / ST40STB1 */
250 /* NR_IRQS is made from three components:
251 * 1. ONCHIP_NR_IRQS - number of IRLS + on-chip peripherial modules
252 * 2. PINT_NR_IRQS - number of PINT interrupts
253 * 3. OFFCHIP_NR_IRQS - numbe of IRQs from off-chip peripherial modules
256 /* 1. ONCHIP_NR_IRQS */
257 #if defined(CONFIG_CPU_SUBTYPE_SH7604)
258 # define ONCHIP_NR_IRQS 24 // Actually 21
259 #elif defined(CONFIG_CPU_SUBTYPE_SH7707)
260 # define ONCHIP_NR_IRQS 64
261 # define PINT_NR_IRQS 16
262 #elif defined(CONFIG_CPU_SUBTYPE_SH7708)
263 # define ONCHIP_NR_IRQS 32
264 #elif defined(CONFIG_CPU_SUBTYPE_SH7709) || \
265 defined(CONFIG_CPU_SUBTYPE_SH7706) || \
266 defined(CONFIG_CPU_SUBTYPE_SH7705)
267 # define ONCHIP_NR_IRQS 64 // Actually 61
268 # define PINT_NR_IRQS 16
269 #elif defined(CONFIG_CPU_SUBTYPE_SH7710)
270 # define ONCHIP_NR_IRQS 104
271 #elif defined(CONFIG_CPU_SUBTYPE_SH7750)
272 # define ONCHIP_NR_IRQS 48 // Actually 44
273 #elif defined(CONFIG_CPU_SUBTYPE_SH7751)
274 # define ONCHIP_NR_IRQS 72
275 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
276 # define ONCHIP_NR_IRQS 112 /* XXX */
277 #elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
278 # define ONCHIP_NR_IRQS 72
279 #elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
280 # define ONCHIP_NR_IRQS 144
281 #elif defined(CONFIG_CPU_SUBTYPE_SH7300) || \
282 defined(CONFIG_CPU_SUBTYPE_SH73180) || \
283 defined(CONFIG_CPU_SUBTYPE_SH7343)
284 # define ONCHIP_NR_IRQS 109
285 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
286 # define ONCHIP_NR_IRQS 111
287 #elif defined(CONFIG_SH_UNKNOWN) /* Most be last */
288 # define ONCHIP_NR_IRQS 144
291 /* 2. PINT_NR_IRQS */
292 #ifdef CONFIG_SH_UNKNOWN
293 # define PINT_NR_IRQS 16
295 # ifndef PINT_NR_IRQS
296 # define PINT_NR_IRQS 0
301 # define PINT_IRQ_BASE ONCHIP_NR_IRQS
304 /* 3. OFFCHIP_NR_IRQS */
305 #if defined(CONFIG_HD64461)
306 # define OFFCHIP_NR_IRQS 18
307 #elif defined (CONFIG_SH_BIGSUR) /* must be before CONFIG_HD64465 */
308 # define OFFCHIP_NR_IRQS 48
309 #elif defined(CONFIG_HD64465)
310 # define OFFCHIP_NR_IRQS 16
311 #elif defined (CONFIG_SH_EC3104)
312 # define OFFCHIP_NR_IRQS 16
313 #elif defined (CONFIG_SH_DREAMCAST)
314 # define OFFCHIP_NR_IRQS 96
315 #elif defined (CONFIG_SH_TITAN)
316 # define OFFCHIP_NR_IRQS 4
317 #elif defined(CONFIG_SH_R7780RP)
318 # define OFFCHIP_NR_IRQS 16
319 #elif defined(CONFIG_SH_UNKNOWN)
320 # define OFFCHIP_NR_IRQS 16 /* Must also be last */
322 # define OFFCHIP_NR_IRQS 0
325 #if OFFCHIP_NR_IRQS > 0
326 # define OFFCHIP_IRQ_BASE (ONCHIP_NR_IRQS + PINT_NR_IRQS)
330 #define NR_IRQS (ONCHIP_NR_IRQS + PINT_NR_IRQS + OFFCHIP_NR_IRQS)
332 extern void disable_irq(unsigned int);
333 extern void disable_irq_nosync(unsigned int);
334 extern void enable_irq(unsigned int);
337 * Simple Mask Register Support
339 extern void make_maskreg_irq(unsigned int irq);
340 extern unsigned short *irq_mask_register;
345 void init_IRQ_pint(void);
348 * Function for "on chip support modules".
350 extern void make_ipr_irq(unsigned int irq, unsigned int addr,
351 int pos, int priority);
352 extern void make_imask_irq(unsigned int irq);
354 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
357 #define INTC_IPRA 0xA414FEE2UL
358 #define INTC_IPRB 0xA414FEE4UL
359 #define INTC_IPRC 0xA4140016UL
360 #define INTC_IPRD 0xA4140018UL
361 #define INTC_IPRE 0xA414001AUL
362 #define INTC_IPRF 0xA4080000UL
363 #define INTC_IPRG 0xA4080002UL
364 #define INTC_IPRH 0xA4080004UL
365 #define INTC_IPRI 0xA4080006UL
366 #define INTC_IPRJ 0xA4080008UL
368 #define INTC_IMR0 0xA4080040UL
369 #define INTC_IMR1 0xA4080042UL
370 #define INTC_IMR2 0xA4080044UL
371 #define INTC_IMR3 0xA4080046UL
372 #define INTC_IMR4 0xA4080048UL
373 #define INTC_IMR5 0xA408004AUL
374 #define INTC_IMR6 0xA408004CUL
375 #define INTC_IMR7 0xA408004EUL
376 #define INTC_IMR8 0xA4080050UL
377 #define INTC_IMR9 0xA4080052UL
378 #define INTC_IMR10 0xA4080054UL
380 #define INTC_IMCR0 0xA4080060UL
381 #define INTC_IMCR1 0xA4080062UL
382 #define INTC_IMCR2 0xA4080064UL
383 #define INTC_IMCR3 0xA4080066UL
384 #define INTC_IMCR4 0xA4080068UL
385 #define INTC_IMCR5 0xA408006AUL
386 #define INTC_IMCR6 0xA408006CUL
387 #define INTC_IMCR7 0xA408006EUL
388 #define INTC_IMCR8 0xA4080070UL
389 #define INTC_IMCR9 0xA4080072UL
390 #define INTC_IMCR10 0xA4080074UL
392 #define INTC_ICR0 0xA414FEE0UL
393 #define INTC_ICR1 0xA4140010UL
395 #define INTC_IRR0 0xA4140004UL
397 #define PORT_PACR 0xA4050100UL
398 #define PORT_PBCR 0xA4050102UL
399 #define PORT_PCCR 0xA4050104UL
400 #define PORT_PDCR 0xA4050106UL
401 #define PORT_PECR 0xA4050108UL
402 #define PORT_PFCR 0xA405010AUL
403 #define PORT_PGCR 0xA405010CUL
404 #define PORT_PHCR 0xA405010EUL
405 #define PORT_PJCR 0xA4050110UL
406 #define PORT_PKCR 0xA4050112UL
407 #define PORT_PLCR 0xA4050114UL
408 #define PORT_SCPCR 0xA4050116UL
409 #define PORT_PMCR 0xA4050118UL
410 #define PORT_PNCR 0xA405011AUL
411 #define PORT_PQCR 0xA405011CUL
413 #define PORT_PSELA 0xA4050140UL
414 #define PORT_PSELB 0xA4050142UL
415 #define PORT_PSELC 0xA4050144UL
417 #define PORT_HIZCRA 0xA4050146UL
418 #define PORT_HIZCRB 0xA4050148UL
419 #define PORT_DRVCR 0xA4050150UL
421 #define PORT_PADR 0xA4050120UL
422 #define PORT_PBDR 0xA4050122UL
423 #define PORT_PCDR 0xA4050124UL
424 #define PORT_PDDR 0xA4050126UL
425 #define PORT_PEDR 0xA4050128UL
426 #define PORT_PFDR 0xA405012AUL
427 #define PORT_PGDR 0xA405012CUL
428 #define PORT_PHDR 0xA405012EUL
429 #define PORT_PJDR 0xA4050130UL
430 #define PORT_PKDR 0xA4050132UL
431 #define PORT_PLDR 0xA4050134UL
432 #define PORT_SCPDR 0xA4050136UL
433 #define PORT_PMDR 0xA4050138UL
434 #define PORT_PNDR 0xA405013AUL
435 #define PORT_PQDR 0xA405013CUL
444 #define IRQ0_IPR_ADDR INTC_IPRC
445 #define IRQ1_IPR_ADDR INTC_IPRC
446 #define IRQ2_IPR_ADDR INTC_IPRC
447 #define IRQ3_IPR_ADDR INTC_IPRC
448 #define IRQ4_IPR_ADDR INTC_IPRD
449 #define IRQ5_IPR_ADDR INTC_IPRD
451 #define IRQ0_IPR_POS 0
452 #define IRQ1_IPR_POS 1
453 #define IRQ2_IPR_POS 2
454 #define IRQ3_IPR_POS 3
455 #define IRQ4_IPR_POS 0
456 #define IRQ5_IPR_POS 1
458 #define IRQ0_PRIORITY 1
459 #define IRQ1_PRIORITY 1
460 #define IRQ2_PRIORITY 1
461 #define IRQ3_PRIORITY 1
462 #define IRQ4_PRIORITY 1
463 #define IRQ5_PRIORITY 1
465 extern int ipr_irq_demux(int irq);
466 #define __irq_demux(irq) ipr_irq_demux(irq)
468 #elif defined(CONFIG_CPU_SUBTYPE_SH7604)
469 #define INTC_IPRA 0xfffffee2UL
470 #define INTC_IPRB 0xfffffe60UL
472 #define INTC_VCRA 0xfffffe62UL
473 #define INTC_VCRB 0xfffffe64UL
474 #define INTC_VCRC 0xfffffe66UL
475 #define INTC_VCRD 0xfffffe68UL
477 #define INTC_VCRWDT 0xfffffee4UL
478 #define INTC_VCRDIV 0xffffff0cUL
479 #define INTC_VCRDMA0 0xffffffa0UL
480 #define INTC_VCRDMA1 0xffffffa8UL
482 #define INTC_ICR 0xfffffee0UL
483 #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
484 defined(CONFIG_CPU_SUBTYPE_SH7706) || \
485 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
486 defined(CONFIG_CPU_SUBTYPE_SH7709) || \
487 defined(CONFIG_CPU_SUBTYPE_SH7710)
488 #define INTC_IRR0 0xa4000004UL
489 #define INTC_IRR1 0xa4000006UL
490 #define INTC_IRR2 0xa4000008UL
492 #define INTC_ICR0 0xfffffee0UL
493 #define INTC_ICR1 0xa4000010UL
494 #define INTC_ICR2 0xa4000012UL
495 #define INTC_INTER 0xa4000014UL
497 #define INTC_IPRC 0xa4000016UL
498 #define INTC_IPRD 0xa4000018UL
499 #define INTC_IPRE 0xa400001aUL
500 #if defined(CONFIG_CPU_SUBTYPE_SH7707)
501 #define INTC_IPRF 0xa400001cUL
502 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
503 #define INTC_IPRF 0xa4080000UL
504 #define INTC_IPRG 0xa4080002UL
505 #define INTC_IPRH 0xa4080004UL
506 #elif defined(CONFIG_CPU_SUBTYPE_SH7710)
507 /* Interrupt Controller Registers */
510 #define INTC_IPRA 0xA414FEE2UL
511 #define INTC_IPRB 0xA414FEE4UL
512 #define INTC_IPRF 0xA4080000UL
513 #define INTC_IPRG 0xA4080002UL
514 #define INTC_IPRH 0xA4080004UL
515 #define INTC_IPRI 0xA4080006UL
519 #define INTC_ICR0 0xA414FEE0UL
520 #define INTC_ICR1 0xA4140010UL
522 #define INTC_IRR0 0xa4000004UL
523 #define INTC_IRR1 0xa4000006UL
524 #define INTC_IRR2 0xa4000008UL
525 #define INTC_IRR3 0xa400000AUL
526 #define INTC_IRR4 0xa400000CUL
527 #define INTC_IRR5 0xa4080020UL
528 #define INTC_IRR7 0xa4080024UL
529 #define INTC_IRR8 0xa4080026UL
531 /* Interrupt numbers */
532 #define TIMER2_IRQ 18
533 #define TIMER2_IPR_ADDR INTC_IPRA
534 #define TIMER2_IPR_POS 1
535 #define TIMER2_PRIORITY 2
539 #define WDT_IPR_ADDR INTC_IPRB
540 #define WDT_IPR_POS 3
541 #define WDT_PRIORITY 2
543 #define SCIF0_ERI_IRQ 52
544 #define SCIF0_RXI_IRQ 53
545 #define SCIF0_BRI_IRQ 54
546 #define SCIF0_TXI_IRQ 55
547 #define SCIF0_IPR_ADDR INTC_IPRE
548 #define SCIF0_IPR_POS 2
549 #define SCIF0_PRIORITY 3
553 #define DMA2_IPR_ADDR INTC_IPRF
554 #define DMA2_IPR_POS 2
555 #define DMA2_PRIORITY 7
558 #define IPSEC_IPR_ADDR INTC_IPRF
559 #define IPSEC_IPR_POS 3
560 #define IPSEC_PRIORITY 3
563 #define EDMAC0_IRQ 80
564 #define EDMAC0_IPR_ADDR INTC_IPRG
565 #define EDMAC0_IPR_POS 3
566 #define EDMAC0_PRIORITY 3
568 #define EDMAC1_IRQ 81
569 #define EDMAC1_IPR_ADDR INTC_IPRG
570 #define EDMAC1_IPR_POS 2
571 #define EDMAC1_PRIORITY 3
573 #define EDMAC2_IRQ 82
574 #define EDMAC2_IPR_ADDR INTC_IPRG
575 #define EDMAC2_IPR_POS 1
576 #define EDMAC2_PRIORITY 3
579 #define SIOF0_ERI_IRQ 96
580 #define SIOF0_TXI_IRQ 97
581 #define SIOF0_RXI_IRQ 98
582 #define SIOF0_CCI_IRQ 99
583 #define SIOF0_IPR_ADDR INTC_IPRH
584 #define SIOF0_IPR_POS 0
585 #define SIOF0_PRIORITY 7
587 #define SIOF1_ERI_IRQ 100
588 #define SIOF1_TXI_IRQ 101
589 #define SIOF1_RXI_IRQ 102
590 #define SIOF1_CCI_IRQ 103
591 #define SIOF1_IPR_ADDR INTC_IPRI
592 #define SIOF1_IPR_POS 1
593 #define SIOF1_PRIORITY 7
594 #endif /* CONFIG_CPU_SUBTYPE_SH7710 */
596 #if defined(CONFIG_CPU_SUBTYPE_SH7710)
597 #define PORT_PACR 0xa4050100UL
598 #define PORT_PBCR 0xa4050102UL
599 #define PORT_PCCR 0xa4050104UL
600 #define PORT_PETCR 0xa4050106UL
601 #define PORT_PADR 0xa4050120UL
602 #define PORT_PBDR 0xa4050122UL
603 #define PORT_PCDR 0xa4050124UL
605 #define PORT_PACR 0xa4000100UL
606 #define PORT_PBCR 0xa4000102UL
607 #define PORT_PCCR 0xa4000104UL
608 #define PORT_PFCR 0xa400010aUL
609 #define PORT_PADR 0xa4000120UL
610 #define PORT_PBDR 0xa4000122UL
611 #define PORT_PCDR 0xa4000124UL
612 #define PORT_PFDR 0xa400012aUL
622 #define IRQ0_IPR_ADDR INTC_IPRC
623 #define IRQ1_IPR_ADDR INTC_IPRC
624 #define IRQ2_IPR_ADDR INTC_IPRC
625 #define IRQ3_IPR_ADDR INTC_IPRC
626 #define IRQ4_IPR_ADDR INTC_IPRD
627 #define IRQ5_IPR_ADDR INTC_IPRD
629 #define IRQ0_IPR_POS 0
630 #define IRQ1_IPR_POS 1
631 #define IRQ2_IPR_POS 2
632 #define IRQ3_IPR_POS 3
633 #define IRQ4_IPR_POS 0
634 #define IRQ5_IPR_POS 1
636 #define IRQ0_PRIORITY 1
637 #define IRQ1_PRIORITY 1
638 #define IRQ2_PRIORITY 1
639 #define IRQ3_PRIORITY 1
640 #define IRQ4_PRIORITY 1
641 #define IRQ5_PRIORITY 1
646 #define PINT0_IPR_ADDR INTC_IPRD
647 #define PINT8_IPR_ADDR INTC_IPRD
649 #define PINT0_IPR_POS 3
650 #define PINT8_IPR_POS 2
651 #define PINT0_PRIORITY 2
652 #define PINT8_PRIORITY 2
654 extern int ipr_irq_demux(int irq);
655 #define __irq_demux(irq) ipr_irq_demux(irq)
656 #endif /* CONFIG_CPU_SUBTYPE_SH7707 || CONFIG_CPU_SUBTYPE_SH7709 */
658 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \
659 defined(CONFIG_CPU_SUBTYPE_ST40STB1) || defined(CONFIG_CPU_SUBTYPE_SH4_202)
660 #define INTC_ICR 0xffd00000
661 #define INTC_ICR_NMIL (1<<15)
662 #define INTC_ICR_MAI (1<<14)
663 #define INTC_ICR_NMIB (1<<9)
664 #define INTC_ICR_NMIE (1<<8)
665 #define INTC_ICR_IRLM (1<<7)
668 #ifdef CONFIG_CPU_SUBTYPE_SH7780
669 #include <asm/irq-sh7780.h>
672 /* SH with INTC2-style interrupts */
673 #ifdef CONFIG_CPU_HAS_INTC2_IRQ
674 #if defined(CONFIG_CPU_SUBTYPE_ST40STB1)
675 #define INTC2_BASE 0xfe080000
676 #define INTC2_FIRST_IRQ 64
677 #define INTC2_INTREQ_OFFSET 0x20
678 #define INTC2_INTMSK_OFFSET 0x40
679 #define INTC2_INTMSKCLR_OFFSET 0x60
680 #define NR_INTC2_IRQS 25
681 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
682 #define INTC2_BASE 0xfe080000
683 #define INTC2_FIRST_IRQ 48 /* INTEVT 0x800 */
684 #define INTC2_INTREQ_OFFSET 0x20
685 #define INTC2_INTMSK_OFFSET 0x40
686 #define INTC2_INTMSKCLR_OFFSET 0x60
687 #define NR_INTC2_IRQS 64
688 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
689 #define INTC2_BASE 0xffd40000
690 #define INTC2_FIRST_IRQ 21
691 #define INTC2_INTMSK_OFFSET (0x38)
692 #define INTC2_INTMSKCLR_OFFSET (0x3c)
693 #define NR_INTC2_IRQS 60
696 #define INTC2_INTPRI_OFFSET 0x00
698 void make_intc2_irq(unsigned int irq,
699 unsigned int ipr_offset, unsigned int ipr_shift,
700 unsigned int msk_offset, unsigned int msk_shift,
701 unsigned int priority);
702 void init_IRQ_intc2(void);
703 void intc2_add_clear_irq(int irq, int (*fn)(int));
707 extern int shmse_irq_demux(int irq);
709 static inline int generic_irq_demux(int irq)
715 #define __irq_demux(irq) (irq)
717 #define irq_canonicalize(irq) (irq)
718 #define irq_demux(irq) __irq_demux(sh_mv.mv_irq_demux(irq))
720 #if defined(CONFIG_CPU_SUBTYPE_SH73180)
721 #include <asm/irq-sh73180.h>
724 #if defined(CONFIG_CPU_SUBTYPE_SH7343)
725 #include <asm/irq-sh7343.h>
728 #endif /* __ASM_SH_IRQ_H */