1 /* pbm.h: UltraSparc PCI controller software state.
3 * Copyright (C) 1997, 1998, 1999, 2007 David S. Miller (davem@davemloft.net)
6 #ifndef __SPARC64_PBM_H
7 #define __SPARC64_PBM_H
9 #include <linux/types.h>
10 #include <linux/pci.h>
11 #include <linux/ioport.h>
12 #include <linux/spinlock.h>
13 #include <linux/msi.h>
17 #include <asm/oplib.h>
19 #include <asm/of_device.h>
20 #include <asm/iommu.h>
22 /* The abstraction used here is that there are PCI controllers,
23 * each with one (Sabre) or two (PSYCHO/SCHIZO) PCI bus modules
24 * underneath. Each PCI bus module uses an IOMMU (shared by both
25 * PBMs of a controller, or per-PBM), and if a streaming buffer
26 * is present, each PCI bus module has it's own. (ie. the IOMMU
27 * might be shared between PBMs, the STC is never shared)
28 * Furthermore, each PCI bus module controls it's own autonomous
32 extern void pci_iommu_table_init(struct iommu *iommu, int tsbsize, u32 dma_offset, u32 dma_addr_mask);
34 #define PCI_STC_FLUSHFLAG_INIT(STC) \
35 (*((STC)->strbuf_flushflag) = 0UL)
36 #define PCI_STC_FLUSHFLAG_SET(STC) \
37 (*((STC)->strbuf_flushflag) != 0UL)
39 struct pci_controller_info;
42 struct pci_pbm_info *next;
45 /* PCI controller we sit under. */
46 struct pci_controller_info *parent;
48 /* Physical address base of controller registers. */
49 unsigned long controller_regs;
51 /* Physical address base of PBM registers. */
52 unsigned long pbm_regs;
54 /* Physical address of DMA sync register, if any. */
55 unsigned long sync_reg;
57 /* Opaque 32-bit system bus Port ID. */
60 /* Opaque 32-bit handle used for hypervisor calls. */
63 /* Chipset version information. */
65 #define PBM_CHIP_TYPE_SABRE 1
66 #define PBM_CHIP_TYPE_PSYCHO 2
67 #define PBM_CHIP_TYPE_SCHIZO 3
68 #define PBM_CHIP_TYPE_SCHIZO_PLUS 4
69 #define PBM_CHIP_TYPE_TOMATILLO 5
73 /* Name used for top-level resources. */
76 /* OBP specific information. */
77 struct device_node *prom_node;
80 /* PBM I/O and Memory space resources. */
81 struct resource io_space;
82 struct resource mem_space;
84 /* Base of PCI Config space, can be per-PBM or shared. */
85 unsigned long config_space;
87 /* State of 66MHz capabilities on this PBM. */
96 u32 msiq_first_devino;
106 unsigned long *msi_bitmap;
107 int (*setup_msi_irq)(unsigned int *virt_irq_p, struct pci_dev *pdev,
108 struct msi_desc *entry);
109 void (*teardown_msi_irq)(unsigned int virt_irq, struct pci_dev *pdev);
110 #endif /* !(CONFIG_PCI_MSI) */
112 /* This PBM's streaming buffer. */
115 /* IOMMU state, potentially shared by both PBM segments. */
118 /* Now things for the actual PCI bus probes. */
119 unsigned int pci_first_busno;
120 unsigned int pci_last_busno;
121 struct pci_bus *pci_bus;
122 void (*scan_bus)(struct pci_pbm_info *);
123 struct pci_ops *pci_ops;
126 struct pci_controller_info {
127 /* The PCI bus modules controlled by us. */
128 struct pci_pbm_info pbm_A;
129 struct pci_pbm_info pbm_B;
132 #endif /* !(__SPARC64_PBM_H) */