include/asm-x86/apicdef.h

   1 #ifndef _ASM_X86_APICDEF_H
   2 #define _ASM_X86_APICDEF_H
   3
   4 /*
   5  * Constants for various Intel APICs. (local APIC, IOAPIC, etc.)
   6  *
   7  * Alan Cox <Alan.Cox@linux.org>, 1995.
   8  * Ingo Molnar <mingo@redhat.com>, 1999, 2000
   9  */
  10
  11 #define APIC_DEFAULT_PHYS_BASE  0xfee00000
  12
  13 #define APIC_ID         0x20
  14
  15 #ifdef CONFIG_X86_64
  16 # define        APIC_ID_MASK            (0xFFu<<24)
  17 # define        GET_APIC_ID(x)          (((x)>>24)&0xFFu)
  18 # define        SET_APIC_ID(x)          (((x)<<24))
  19 #endif
  20
  21 #define APIC_LVR        0x30
  22 #define         APIC_LVR_MASK           0xFF00FF
  23 #define         GET_APIC_VERSION(x)     ((x)&0xFFu)
  24 #define         GET_APIC_MAXLVT(x)      (((x)>>16)&0xFFu)
  25 #define         APIC_INTEGRATED(x)      ((x)&0xF0u)
  26 #define         APIC_XAPIC(x)           ((x) >= 0x14)
  27 #define APIC_TASKPRI    0x80
  28 #define         APIC_TPRI_MASK          0xFFu
  29 #define APIC_ARBPRI     0x90
  30 #define         APIC_ARBPRI_MASK        0xFFu
  31 #define APIC_PROCPRI    0xA0
  32 #define APIC_EOI        0xB0
  33 #define         APIC_EIO_ACK            0x0
  34 #define APIC_RRR        0xC0
  35 #define APIC_LDR        0xD0
  36 #define         APIC_LDR_MASK           (0xFFu<<24)
  37 #define         GET_APIC_LOGICAL_ID(x)  (((x)>>24)&0xFFu)
  38 #define         SET_APIC_LOGICAL_ID(x)  (((x)<<24))
  39 #define         APIC_ALL_CPUS           0xFFu
  40 #define APIC_DFR        0xE0
  41 #define         APIC_DFR_CLUSTER                0x0FFFFFFFul
  42 #define         APIC_DFR_FLAT                   0xFFFFFFFFul
  43 #define APIC_SPIV       0xF0
  44 #define         APIC_SPIV_FOCUS_DISABLED        (1<<9)
  45 #define         APIC_SPIV_APIC_ENABLED          (1<<8)
  46 #define APIC_ISR        0x100
  47 #define APIC_ISR_NR     0x8     /* Number of 32 bit ISR registers. */
  48 #define APIC_TMR        0x180
  49 #define APIC_IRR        0x200
  50 #define APIC_ESR        0x280
  51 #define         APIC_ESR_SEND_CS        0x00001
  52 #define         APIC_ESR_RECV_CS        0x00002
  53 #define         APIC_ESR_SEND_ACC       0x00004
  54 #define         APIC_ESR_RECV_ACC       0x00008
  55 #define         APIC_ESR_SENDILL        0x00020
  56 #define         APIC_ESR_RECVILL        0x00040
  57 #define         APIC_ESR_ILLREGA        0x00080
  58 #define APIC_ICR        0x300
  59 #define         APIC_DEST_SELF          0x40000
  60 #define         APIC_DEST_ALLINC        0x80000
  61 #define         APIC_DEST_ALLBUT        0xC0000
  62 #define         APIC_ICR_RR_MASK        0x30000
  63 #define         APIC_ICR_RR_INVALID     0x00000
  64 #define         APIC_ICR_RR_INPROG      0x10000
  65 #define         APIC_ICR_RR_VALID       0x20000
  66 #define         APIC_INT_LEVELTRIG      0x08000
  67 #define         APIC_INT_ASSERT         0x04000
  68 #define         APIC_ICR_BUSY           0x01000
  69 #define         APIC_DEST_LOGICAL       0x00800
  70 #define         APIC_DEST_PHYSICAL      0x00000
  71 #define         APIC_DM_FIXED           0x00000
  72 #define         APIC_DM_LOWEST          0x00100
  73 #define         APIC_DM_SMI             0x00200
  74 #define         APIC_DM_REMRD           0x00300
  75 #define         APIC_DM_NMI             0x00400
  76 #define         APIC_DM_INIT            0x00500
  77 #define         APIC_DM_STARTUP         0x00600
  78 #define         APIC_DM_EXTINT          0x00700
  79 #define         APIC_VECTOR_MASK        0x000FF
  80 #define APIC_ICR2       0x310
  81 #define         GET_APIC_DEST_FIELD(x)  (((x)>>24)&0xFF)
  82 #define         SET_APIC_DEST_FIELD(x)  ((x)<<24)
  83 #define APIC_LVTT       0x320
  84 #define APIC_LVTTHMR    0x330
  85 #define APIC_LVTPC      0x340
  86 #define APIC_LVT0       0x350
  87 #define         APIC_LVT_TIMER_BASE_MASK        (0x3<<18)
  88 #define         GET_APIC_TIMER_BASE(x)          (((x)>>18)&0x3)
  89 #define         SET_APIC_TIMER_BASE(x)          (((x)<<18))
  90 #define         APIC_TIMER_BASE_CLKIN           0x0
  91 #define         APIC_TIMER_BASE_TMBASE          0x1
  92 #define         APIC_TIMER_BASE_DIV             0x2
  93 #define         APIC_LVT_TIMER_PERIODIC         (1<<17)
  94 #define         APIC_LVT_MASKED                 (1<<16)
  95 #define         APIC_LVT_LEVEL_TRIGGER          (1<<15)
  96 #define         APIC_LVT_REMOTE_IRR             (1<<14)
  97 #define         APIC_INPUT_POLARITY             (1<<13)
  98 #define         APIC_SEND_PENDING               (1<<12)
  99 #define         APIC_MODE_MASK                  0x700
 100 #define         GET_APIC_DELIVERY_MODE(x)       (((x)>>8)&0x7)
 101 #define         SET_APIC_DELIVERY_MODE(x, y)    (((x)&~0x700)|((y)<<8))
 102 #define                 APIC_MODE_FIXED         0x0
 103 #define                 APIC_MODE_NMI           0x4
 104 #define                 APIC_MODE_EXTINT        0x7
 105 #define APIC_LVT1       0x360
 106 #define APIC_LVTERR     0x370
 107 #define APIC_TMICT      0x380
 108 #define APIC_TMCCT      0x390
 109 #define APIC_TDCR       0x3E0
 110 #define         APIC_TDR_DIV_TMBASE     (1<<2)
 111 #define         APIC_TDR_DIV_1          0xB
 112 #define         APIC_TDR_DIV_2          0x0
 113 #define         APIC_TDR_DIV_4          0x1
 114 #define         APIC_TDR_DIV_8          0x2
 115 #define         APIC_TDR_DIV_16         0x3
 116 #define         APIC_TDR_DIV_32         0x8
 117 #define         APIC_TDR_DIV_64         0x9
 118 #define         APIC_TDR_DIV_128        0xA
 119
 120 #define K8_APIC_EXT_LVT_BASE            0x500
 121 #define K8_APIC_EXT_INT_MSG_FIX         0x0
 122 #define K8_APIC_EXT_INT_MSG_SMI         0x2
 123 #define K8_APIC_EXT_INT_MSG_NMI         0x4
 124 #define K8_APIC_EXT_INT_MSG_EXT         0x7
 125 #define K8_APIC_EXT_LVT_ENTRY_THRESHOLD 0
 126
 127 #define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
 128
 129 #ifdef CONFIG_X86_32
 130 # define MAX_IO_APICS 64
 131 #else
 132 # define MAX_IO_APICS 128
 133 # define MAX_LOCAL_APIC 256
 134 #endif
 135
 136 /*
 137  * All x86-64 systems are xAPIC compatible.
 138  * In the following, "apicid" is a physical APIC ID.
 139  */
 140 #define XAPIC_DEST_CPUS_SHIFT   4
 141 #define XAPIC_DEST_CPUS_MASK    ((1u << XAPIC_DEST_CPUS_SHIFT) - 1)
 142 #define XAPIC_DEST_CLUSTER_MASK (XAPIC_DEST_CPUS_MASK << XAPIC_DEST_CPUS_SHIFT)
 143 #define APIC_CLUSTER(apicid)    ((apicid) & XAPIC_DEST_CLUSTER_MASK)
 144 #define APIC_CLUSTERID(apicid)  (APIC_CLUSTER(apicid) >> XAPIC_DEST_CPUS_SHIFT)
 145 #define APIC_CPUID(apicid)      ((apicid) & XAPIC_DEST_CPUS_MASK)
 146 #define NUM_APIC_CLUSTERS       ((BAD_APICID + 1) >> XAPIC_DEST_CPUS_SHIFT)
 147
 148 /*
 149  * the local APIC register structure, memory mapped. Not terribly well
 150  * tested, but we might eventually use this one in the future - the
 151  * problem why we cannot use it right now is the P5 APIC, it has an
 152  * errata which cannot take 8-bit reads and writes, only 32-bit ones ...
 153  */
 154 #define u32 unsigned int
 155
 156 struct local_apic {
 157
 158 /*000*/ struct { u32 __reserved[4]; } __reserved_01;
 159
 160 /*010*/ struct { u32 __reserved[4]; } __reserved_02;
 161
 162 /*020*/ struct { /* APIC ID Register */
 163                 u32   __reserved_1      : 24,
 164                         phys_apic_id    :  4,
 165                         __reserved_2    :  4;
 166                 u32 __reserved[3];
 167         } id;
 168
 169 /*030*/ const
 170         struct { /* APIC Version Register */
 171                 u32   version           :  8,
 172                         __reserved_1    :  8,
 173                         max_lvt         :  8,
 174                         __reserved_2    :  8;
 175                 u32 __reserved[3];
 176         } version;
 177
 178 /*040*/ struct { u32 __reserved[4]; } __reserved_03;
 179
 180 /*050*/ struct { u32 __reserved[4]; } __reserved_04;
 181
 182 /*060*/ struct { u32 __reserved[4]; } __reserved_05;
 183
 184 /*070*/ struct { u32 __reserved[4]; } __reserved_06;
 185
 186 /*080*/ struct { /* Task Priority Register */
 187                 u32   priority  :  8,
 188                         __reserved_1    : 24;
 189                 u32 __reserved_2[3];
 190         } tpr;
 191
 192 /*090*/ const
 193         struct { /* Arbitration Priority Register */
 194                 u32   priority  :  8,
 195                         __reserved_1    : 24;
 196                 u32 __reserved_2[3];
 197         } apr;
 198
 199 /*0A0*/ const
 200         struct { /* Processor Priority Register */
 201                 u32   priority  :  8,
 202                         __reserved_1    : 24;
 203                 u32 __reserved_2[3];
 204         } ppr;
 205
 206 /*0B0*/ struct { /* End Of Interrupt Register */
 207                 u32   eoi;
 208                 u32 __reserved[3];
 209         } eoi;
 210
 211 /*0C0*/ struct { u32 __reserved[4]; } __reserved_07;
 212
 213 /*0D0*/ struct { /* Logical Destination Register */
 214                 u32   __reserved_1      : 24,
 215                         logical_dest    :  8;
 216                 u32 __reserved_2[3];
 217         } ldr;
 218
 219 /*0E0*/ struct { /* Destination Format Register */
 220                 u32   __reserved_1      : 28,
 221                         model           :  4;
 222                 u32 __reserved_2[3];
 223         } dfr;
 224
 225 /*0F0*/ struct { /* Spurious Interrupt Vector Register */
 226                 u32     spurious_vector :  8,
 227                         apic_enabled    :  1,
 228                         focus_cpu       :  1,
 229                         __reserved_2    : 22;
 230                 u32 __reserved_3[3];
 231         } svr;
 232
 233 /*100*/ struct { /* In Service Register */
 234 /*170*/         u32 bitfield;
 235                 u32 __reserved[3];
 236         } isr [8];
 237
 238 /*180*/ struct { /* Trigger Mode Register */
 239 /*1F0*/         u32 bitfield;
 240                 u32 __reserved[3];
 241         } tmr [8];
 242
 243 /*200*/ struct { /* Interrupt Request Register */
 244 /*270*/         u32 bitfield;
 245                 u32 __reserved[3];
 246         } irr [8];
 247
 248 /*280*/ union { /* Error Status Register */
 249                 struct {
 250                         u32   send_cs_error                     :  1,
 251                                 receive_cs_error                :  1,
 252                                 send_accept_error               :  1,
 253                                 receive_accept_error            :  1,
 254                                 __reserved_1                    :  1,
 255                                 send_illegal_vector             :  1,
 256                                 receive_illegal_vector          :  1,
 257                                 illegal_register_address        :  1,
 258                                 __reserved_2                    : 24;
 259                         u32 __reserved_3[3];
 260                 } error_bits;
 261                 struct {
 262                         u32 errors;
 263                         u32 __reserved_3[3];
 264                 } all_errors;
 265         } esr;
 266
 267 /*290*/ struct { u32 __reserved[4]; } __reserved_08;
 268
 269 /*2A0*/ struct { u32 __reserved[4]; } __reserved_09;
 270
 271 /*2B0*/ struct { u32 __reserved[4]; } __reserved_10;
 272
 273 /*2C0*/ struct { u32 __reserved[4]; } __reserved_11;
 274
 275 /*2D0*/ struct { u32 __reserved[4]; } __reserved_12;
 276
 277 /*2E0*/ struct { u32 __reserved[4]; } __reserved_13;
 278
 279 /*2F0*/ struct { u32 __reserved[4]; } __reserved_14;
 280
 281 /*300*/ struct { /* Interrupt Command Register 1 */
 282                 u32   vector                    :  8,
 283                         delivery_mode           :  3,
 284                         destination_mode        :  1,
 285                         delivery_status         :  1,
 286                         __reserved_1            :  1,
 287                         level                   :  1,
 288                         trigger                 :  1,
 289                         __reserved_2            :  2,
 290                         shorthand               :  2,
 291                         __reserved_3            :  12;
 292                 u32 __reserved_4[3];
 293         } icr1;
 294
 295 /*310*/ struct { /* Interrupt Command Register 2 */
 296                 union {
 297                         u32   __reserved_1      : 24,
 298                                 phys_dest       :  4,
 299                                 __reserved_2    :  4;
 300                         u32   __reserved_3      : 24,
 301                                 logical_dest    :  8;
 302                 } dest;
 303                 u32 __reserved_4[3];
 304         } icr2;
 305
 306 /*320*/ struct { /* LVT - Timer */
 307                 u32   vector            :  8,
 308                         __reserved_1    :  4,
 309                         delivery_status :  1,
 310                         __reserved_2    :  3,
 311                         mask            :  1,
 312                         timer_mode      :  1,
 313                         __reserved_3    : 14;
 314                 u32 __reserved_4[3];
 315         } lvt_timer;
 316
 317 /*330*/ struct { /* LVT - Thermal Sensor */
 318                 u32  vector             :  8,
 319                         delivery_mode   :  3,
 320                         __reserved_1    :  1,
 321                         delivery_status :  1,
 322                         __reserved_2    :  3,
 323                         mask            :  1,
 324                         __reserved_3    : 15;
 325                 u32 __reserved_4[3];
 326         } lvt_thermal;
 327
 328 /*340*/ struct { /* LVT - Performance Counter */
 329                 u32   vector            :  8,
 330                         delivery_mode   :  3,
 331                         __reserved_1    :  1,
 332                         delivery_status :  1,
 333                         __reserved_2    :  3,
 334                         mask            :  1,
 335                         __reserved_3    : 15;
 336                 u32 __reserved_4[3];
 337         } lvt_pc;
 338
 339 /*350*/ struct { /* LVT - LINT0 */
 340                 u32   vector            :  8,
 341                         delivery_mode   :  3,
 342                         __reserved_1    :  1,
 343                         delivery_status :  1,
 344                         polarity        :  1,
 345                         remote_irr      :  1,
 346                         trigger         :  1,
 347                         mask            :  1,
 348                         __reserved_2    : 15;
 349                 u32 __reserved_3[3];
 350         } lvt_lint0;
 351
 352 /*360*/ struct { /* LVT - LINT1 */
 353                 u32   vector            :  8,
 354                         delivery_mode   :  3,
 355                         __reserved_1    :  1,
 356                         delivery_status :  1,
 357                         polarity        :  1,
 358                         remote_irr      :  1,
 359                         trigger         :  1,
 360                         mask            :  1,
 361                         __reserved_2    : 15;
 362                 u32 __reserved_3[3];
 363         } lvt_lint1;
 364
 365 /*370*/ struct { /* LVT - Error */
 366                 u32   vector            :  8,
 367                         __reserved_1    :  4,
 368                         delivery_status :  1,
 369                         __reserved_2    :  3,
 370                         mask            :  1,
 371                         __reserved_3    : 15;
 372                 u32 __reserved_4[3];
 373         } lvt_error;
 374
 375 /*380*/ struct { /* Timer Initial Count Register */
 376                 u32   initial_count;
 377                 u32 __reserved_2[3];
 378         } timer_icr;
 379
 380 /*390*/ const
 381         struct { /* Timer Current Count Register */
 382                 u32   curr_count;
 383                 u32 __reserved_2[3];
 384         } timer_ccr;
 385
 386 /*3A0*/ struct { u32 __reserved[4]; } __reserved_16;
 387
 388 /*3B0*/ struct { u32 __reserved[4]; } __reserved_17;
 389
 390 /*3C0*/ struct { u32 __reserved[4]; } __reserved_18;
 391
 392 /*3D0*/ struct { u32 __reserved[4]; } __reserved_19;
 393
 394 /*3E0*/ struct { /* Timer Divide Configuration Register */
 395                 u32   divisor           :  4,
 396                         __reserved_1    : 28;
 397                 u32 __reserved_2[3];
 398         } timer_dcr;
 399
 400 /*3F0*/ struct { u32 __reserved[4]; } __reserved_20;
 401
 402 } __attribute__ ((packed));
 403
 404 #undef u32
 405
 406 #define BAD_APICID 0xFFu
 407
 408 #endif