include/asm-x86/spinlock.h

   1 #ifndef _X86_SPINLOCK_H_
   2 #define _X86_SPINLOCK_H_
   3
   4 #include <asm/atomic.h>
   5 #include <asm/rwlock.h>
   6 #include <asm/page.h>
   7 #include <asm/processor.h>
   8
   9 /*
  10  * Your basic SMP spinlocks, allowing only a single CPU anywhere
  11  *
  12  * Simple spin lock operations.  There are two variants, one clears IRQ's
  13  * on the local processor, one does not.
  14  *
  15  * We make no fairness assumptions. They have a cost.
  16  *
  17  * (the type definitions are in asm/spinlock_types.h)
  18  */
  19
  20 #ifdef CONFIG_PARAVIRT
  21 #include <asm/paravirt.h>
  22 #else
  23 #define CLI_STRING      "cli"
  24 #define STI_STRING      "sti"
  25 #define CLI_STI_CLOBBERS
  26 #define CLI_STI_INPUT_ARGS
  27 #endif /* CONFIG_PARAVIRT */
  28
  29 #ifdef CONFIG_X86_32
  30 typedef char _slock_t;
  31 # define LOCK_INS_DEC "decb"
  32 # define LOCK_INS_XCH "xchgb"
  33 # define LOCK_INS_MOV "movb"
  34 # define LOCK_INS_CMP "cmpb"
  35 # define LOCK_PTR_REG "a"
  36 #else
  37 typedef int _slock_t;
  38 # define LOCK_INS_DEC "decl"
  39 # define LOCK_INS_XCH "xchgl"
  40 # define LOCK_INS_MOV "movl"
  41 # define LOCK_INS_CMP "cmpl"
  42 # define LOCK_PTR_REG "D"
  43 #endif
  44
  45 static inline int __raw_spin_is_locked(raw_spinlock_t *lock)
  46 {
  47         return *(volatile _slock_t *)(&(lock)->slock) <= 0;
  48 }
  49
  50 static inline void __raw_spin_lock(raw_spinlock_t *lock)
  51 {
  52         asm volatile(
  53                 "\n1:\t"
  54                 LOCK_PREFIX " ; " LOCK_INS_DEC " %0\n\t"
  55                 "jns 3f\n"
  56                 "2:\t"
  57                 "rep;nop\n\t"
  58                 LOCK_INS_CMP " $0,%0\n\t"
  59                 "jle 2b\n\t"
  60                 "jmp 1b\n"
  61                 "3:\n\t"
  62                 : "+m" (lock->slock) : : "memory");
  63 }
  64
  65 /*
  66  * It is easier for the lock validator if interrupts are not re-enabled
  67  * in the middle of a lock-acquire. This is a performance feature anyway
  68  * so we turn it off:
  69  *
  70  * NOTE: there's an irqs-on section here, which normally would have to be
  71  * irq-traced, but on CONFIG_TRACE_IRQFLAGS we never use this variant.
  72  */
  73 #ifndef CONFIG_PROVE_LOCKING
  74 static inline void __raw_spin_lock_flags(raw_spinlock_t *lock,
  75                                          unsigned long flags)
  76 {
  77         asm volatile(
  78                 "\n1:\t"
  79                 LOCK_PREFIX " ; " LOCK_INS_DEC " %[slock]\n\t"
  80                 "jns 5f\n"
  81                 "testl $0x200, %[flags]\n\t"
  82                 "jz 4f\n\t"
  83                 STI_STRING "\n"
  84                 "3:\t"
  85                 "rep;nop\n\t"
  86                 LOCK_INS_CMP " $0, %[slock]\n\t"
  87                 "jle 3b\n\t"
  88                 CLI_STRING "\n\t"
  89                 "jmp 1b\n"
  90                 "4:\t"
  91                 "rep;nop\n\t"
  92                 LOCK_INS_CMP " $0, %[slock]\n\t"
  93                 "jg 1b\n\t"
  94                 "jmp 4b\n"
  95                 "5:\n\t"
  96                 : [slock] "+m" (lock->slock)
  97                 : [flags] "r" ((u32)flags)
  98                   CLI_STI_INPUT_ARGS
  99                 : "memory" CLI_STI_CLOBBERS);
 100 }
 101 #endif
 102
 103 static inline int __raw_spin_trylock(raw_spinlock_t *lock)
 104 {
 105         _slock_t oldval;
 106
 107         asm volatile(
 108                 LOCK_INS_XCH " %0,%1"
 109                 :"=q" (oldval), "+m" (lock->slock)
 110                 :"0" (0) : "memory");
 111
 112         return oldval > 0;
 113 }
 114
 115 /*
 116  * __raw_spin_unlock based on writing $1 to the low byte.
 117  * This method works. Despite all the confusion.
 118  * (except on PPro SMP or if we are using OOSTORE, so we use xchgb there)
 119  * (PPro errata 66, 92)
 120  */
 121 #if defined(X86_64) || \
 122         (!defined(CONFIG_X86_OOSTORE) && !defined(CONFIG_X86_PPRO_FENCE))
 123
 124 static inline void __raw_spin_unlock(raw_spinlock_t *lock)
 125 {
 126         asm volatile(LOCK_INS_MOV " $1,%0" : "=m" (lock->slock) :: "memory");
 127 }
 128
 129 #else
 130
 131 static inline void __raw_spin_unlock(raw_spinlock_t *lock)
 132 {
 133         unsigned char oldval = 1;
 134
 135         asm volatile("xchgb %b0, %1"
 136                      : "=q" (oldval), "+m" (lock->slock)
 137                      : "0" (oldval) : "memory");
 138 }
 139
 140 #endif
 141
 142 static inline void __raw_spin_unlock_wait(raw_spinlock_t *lock)
 143 {
 144         while (__raw_spin_is_locked(lock))
 145                 cpu_relax();
 146 }
 147
 148 /*
 149  * Read-write spinlocks, allowing multiple readers
 150  * but only one writer.
 151  *
 152  * NOTE! it is quite common to have readers in interrupts
 153  * but no interrupt writers. For those circumstances we
 154  * can "mix" irq-safe locks - any writer needs to get a
 155  * irq-safe write-lock, but readers can get non-irqsafe
 156  * read-locks.
 157  *
 158  * On x86, we implement read-write locks as a 32-bit counter
 159  * with the high bit (sign) being the "contended" bit.
 160  */
 161
 162 static inline int __raw_read_can_lock(raw_rwlock_t *lock)
 163 {
 164         return (int)(lock)->lock > 0;
 165 }
 166
 167 static inline int __raw_write_can_lock(raw_rwlock_t *lock)
 168 {
 169         return (lock)->lock == RW_LOCK_BIAS;
 170 }
 171
 172 static inline void __raw_read_lock(raw_rwlock_t *rw)
 173 {
 174         asm volatile(LOCK_PREFIX " subl $1,(%0)\n\t"
 175                      "jns 1f\n"
 176                      "call __read_lock_failed\n\t"
 177                      "1:\n"
 178                      ::LOCK_PTR_REG (rw) : "memory");
 179 }
 180
 181 static inline void __raw_write_lock(raw_rwlock_t *rw)
 182 {
 183         asm volatile(LOCK_PREFIX " subl %1,(%0)\n\t"
 184                      "jz 1f\n"
 185                      "call __write_lock_failed\n\t"
 186                      "1:\n"
 187                      ::LOCK_PTR_REG (rw), "i" (RW_LOCK_BIAS) : "memory");
 188 }
 189
 190 static inline int __raw_read_trylock(raw_rwlock_t *lock)
 191 {
 192         atomic_t *count = (atomic_t *)lock;
 193
 194         atomic_dec(count);
 195         if (atomic_read(count) >= 0)
 196                 return 1;
 197         atomic_inc(count);
 198         return 0;
 199 }
 200
 201 static inline int __raw_write_trylock(raw_rwlock_t *lock)
 202 {
 203         atomic_t *count = (atomic_t *)lock;
 204
 205         if (atomic_sub_and_test(RW_LOCK_BIAS, count))
 206                 return 1;
 207         atomic_add(RW_LOCK_BIAS, count);
 208         return 0;
 209 }
 210
 211 static inline void __raw_read_unlock(raw_rwlock_t *rw)
 212 {
 213         asm volatile(LOCK_PREFIX "incl %0" :"+m" (rw->lock) : : "memory");
 214 }
 215
 216 static inline void __raw_write_unlock(raw_rwlock_t *rw)
 217 {
 218         asm volatile(LOCK_PREFIX "addl %1, %0"
 219                      : "+m" (rw->lock) : "i" (RW_LOCK_BIAS) : "memory");
 220 }
 221
 222 #define _raw_spin_relax(lock)   cpu_relax()
 223 #define _raw_read_relax(lock)   cpu_relax()
 224 #define _raw_write_relax(lock)  cpu_relax()
 225
 226 #endif