3 * Copyright (C) Igor Sysoev
8 * "casa [r1] 0x80, r2, r0" and
9 * "casxa [r1] 0x80, r2, r0" do the following:
17 * so "r0 == r2" means that the operation was successfull.
20 * The "r" means the general register.
21 * The "+r" means the general register used for both input and output.
25 #if (NGX_PTR_SIZE == 4)
26 #define NGX_CASA "casa"
28 #define NGX_CASA "casxa"
32 static ngx_inline ngx_atomic_uint_t
33 ngx_atomic_cmp_set(ngx_atomic_t *lock, ngx_atomic_uint_t old,
34 ngx_atomic_uint_t set)
38 NGX_CASA " [%1] 0x80, %2, %0"
40 : "+r" (set) : "r" (lock), "r" (old) : "memory");
46 static ngx_inline ngx_atomic_int_t
47 ngx_atomic_fetch_add(ngx_atomic_t *value, ngx_atomic_int_t add)
49 ngx_atomic_uint_t old, res;
59 NGX_CASA " [%1] 0x80, %2, %0"
61 : "+r" (res) : "r" (value), "r" (old) : "memory");
73 #define ngx_memory_barrier() \
75 "membar #LoadLoad | #LoadStore | #StoreStore | #StoreLoad" \
78 #define ngx_memory_barrier() __asm__ volatile ("" ::: "memory")
81 #define ngx_cpu_pause()