4 Copyright 2008, 2009 Michel Pollet <buserror@gmail.com>
6 This file is part of simavr.
8 simavr is free software: you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation, either version 3 of the License, or
11 (at your option) any later version.
13 simavr is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with simavr. If not, see <http://www.gnu.org/licenses/>.
23 #include "sim_core_declare.h"
24 #include "avr_eeprom.h"
25 #include "avr_flash.h"
26 #include "avr_watchdog.h"
27 #include "avr_extint.h"
28 #include "avr_ioport.h"
31 #include "avr_timer.h"
35 void m128_init(struct avr_t * avr);
36 void m128_reset(struct avr_t * avr);
40 #include "avr/iom128.h"
43 * This is a template for all of the 128 devices, hopefully
49 avr_watchdog_t watchdog;
51 avr_ioport_t porta, portb, portc, portd, porte, portf, portg;
52 avr_uart_t uart0,uart1;
54 avr_timer_t timer0,timer1,timer2,timer3;
65 .rampz = RAMPZ, // extended program memory access
67 AVR_EEPROM_DECLARE_NOEEPM(EE_READY_vect),
68 AVR_SELFPROG_DECLARE(SPMCSR, SPMEN, SPM_READY_vect),
69 AVR_WATCHDOG_DECLARE_128(WDTCR, _VECTOR(0)),
71 AVR_EXTINT_MEGA_DECLARE(0, 'D', PD0, A),
72 AVR_EXTINT_MEGA_DECLARE(1, 'D', PD1, A),
73 AVR_EXTINT_MEGA_DECLARE(2, 'D', PD2, A),
74 AVR_EXTINT_MEGA_DECLARE(3, 'D', PD3, A),
75 AVR_EXTINT_MEGA_DECLARE(4, 'E', PE4, B),
76 AVR_EXTINT_MEGA_DECLARE(5, 'E', PE5, B),
77 AVR_EXTINT_MEGA_DECLARE(6, 'E', PE6, B),
78 AVR_EXTINT_MEGA_DECLARE(7, 'E', PE7, B),
80 .porta = { // no PCINTs in atmega128
81 .name = 'A', .r_port = PORTA, .r_ddr = DDRA, .r_pin = PINA,
84 .name = 'B', .r_port = PORTB, .r_ddr = DDRB, .r_pin = PINB,
87 .name = 'C', .r_port = PORTC, .r_ddr = DDRC, .r_pin = PINC,
90 .name = 'D', .r_port = PORTD, .r_ddr = DDRD, .r_pin = PIND,
93 .name = 'E', .r_port = PORTE, .r_ddr = DDRE, .r_pin = PINE,
96 .name = 'F', .r_port = PORTF, .r_ddr = DDRF, .r_pin = PINF,
99 .name = 'G', .r_port = PORTG, .r_ddr = DDRG, .r_pin = PING,
103 // no PRUSART .disabled = AVR_IO_REGBIT(PRR,PRUSART0),
107 .txen = AVR_IO_REGBIT(UCSR0B, TXEN0),
108 .rxen = AVR_IO_REGBIT(UCSR0B, RXEN0),
109 .ucsz = AVR_IO_REGBITS(UCSR0C, UCSZ00, 0x3), // 2 bits
110 .ucsz2 = AVR_IO_REGBIT(UCSR0B, UCSZ02), // 1 bits
118 .enable = AVR_IO_REGBIT(UCSR0B, RXCIE0),
119 .raised = AVR_IO_REGBIT(UCSR0A, RXC0),
120 .vector = USART0_RX_vect,
123 .enable = AVR_IO_REGBIT(UCSR0B, TXCIE0),
124 .raised = AVR_IO_REGBIT(UCSR0A, TXC0),
125 .vector = USART0_TX_vect,
128 .enable = AVR_IO_REGBIT(UCSR0B, UDRIE0),
129 .raised = AVR_IO_REGBIT(UCSR0A, UDRE0),
130 .vector = USART0_UDRE_vect,
134 // no PRUSART .disabled = AVR_IO_REGBIT(PRR,PRUSART1),
138 .txen = AVR_IO_REGBIT(UCSR1B, TXEN1),
139 .rxen = AVR_IO_REGBIT(UCSR1B, RXEN1),
140 .ucsz = AVR_IO_REGBITS(UCSR1C, UCSZ10, 0x3), // 2 bits
141 .ucsz2 = AVR_IO_REGBIT(UCSR1B, UCSZ12), // 1 bits
149 .enable = AVR_IO_REGBIT(UCSR1B, RXCIE1),
150 .raised = AVR_IO_REGBIT(UCSR1A, RXC1),
151 .vector = USART1_RX_vect,
154 .enable = AVR_IO_REGBIT(UCSR1B, TXCIE1),
155 .raised = AVR_IO_REGBIT(UCSR1A, TXC1),
156 .vector = USART1_TX_vect,
159 .enable = AVR_IO_REGBIT(UCSR1B, UDRIE1),
160 .raised = AVR_IO_REGBIT(UCSR1A, UDRE1),
161 .vector = USART1_UDRE_vect,
166 .mux = { AVR_IO_REGBIT(ADMUX, MUX0), AVR_IO_REGBIT(ADMUX, MUX1),
167 AVR_IO_REGBIT(ADMUX, MUX2), AVR_IO_REGBIT(ADMUX, MUX3),
168 AVR_IO_REGBIT(ADMUX, MUX4),},
169 .ref = { AVR_IO_REGBIT(ADMUX, REFS0), AVR_IO_REGBIT(ADMUX, REFS1)},
170 .ref_values = { [1] = ADC_VREF_AVCC, [3] = ADC_VREF_V256 },
172 .adlar = AVR_IO_REGBIT(ADMUX, ADLAR),
174 .aden = AVR_IO_REGBIT(ADCSRA, ADEN),
175 .adsc = AVR_IO_REGBIT(ADCSRA, ADSC),
176 // no ADATE .adate = AVR_IO_REGBIT(ADCSRA, ADATE),
177 .adps = { AVR_IO_REGBIT(ADCSRA, ADPS0), AVR_IO_REGBIT(ADCSRA, ADPS1), AVR_IO_REGBIT(ADCSRA, ADPS2),},
182 //.r_adcsrb = ADCSRB,
183 // .adts = { AVR_IO_REGBIT(ADCSRB, ADTS0), AVR_IO_REGBIT(ADCSRB, ADTS1), AVR_IO_REGBIT(ADCSRB, ADTS2),},
186 [0] = AVR_ADC_SINGLE(0), [1] = AVR_ADC_SINGLE(1),
187 [2] = AVR_ADC_SINGLE(2), [3] = AVR_ADC_SINGLE(3),
188 [4] = AVR_ADC_SINGLE(4), [5] = AVR_ADC_SINGLE(5),
189 [6] = AVR_ADC_SINGLE(6), [7] = AVR_ADC_SINGLE(7),
191 [ 8] = AVR_ADC_DIFF(0, 0, 10), [ 9] = AVR_ADC_DIFF(1, 0, 10),
192 [10] = AVR_ADC_DIFF(0, 0, 200), [11] = AVR_ADC_DIFF(1, 0, 200),
193 [12] = AVR_ADC_DIFF(2, 2, 10), [13] = AVR_ADC_DIFF(3, 2, 10),
194 [14] = AVR_ADC_DIFF(2, 2, 200), [15] = AVR_ADC_DIFF(3, 2, 200),
196 [16] = AVR_ADC_DIFF(0, 1, 1), [17] = AVR_ADC_DIFF(1, 1, 1),
197 [18] = AVR_ADC_DIFF(2, 1, 1), [19] = AVR_ADC_DIFF(3, 1, 1),
198 [20] = AVR_ADC_DIFF(4, 1, 1), [21] = AVR_ADC_DIFF(5, 1, 1),
199 [22] = AVR_ADC_DIFF(6, 1, 1), [23] = AVR_ADC_DIFF(7, 1, 1),
201 [24] = AVR_ADC_DIFF(0, 2, 1), [25] = AVR_ADC_DIFF(1, 2, 1),
202 [26] = AVR_ADC_DIFF(2, 2, 1), [27] = AVR_ADC_DIFF(3, 2, 1),
203 [28] = AVR_ADC_DIFF(4, 2, 1), [29] = AVR_ADC_DIFF(5, 2, 1),
205 [30] = AVR_ADC_REF(1230), // 1.1V
206 [31] = AVR_ADC_REF(0), // GND
210 .enable = AVR_IO_REGBIT(ADCSRA, ADIE),
211 .raised = AVR_IO_REGBIT(ADCSRA, ADIF),
217 .wgm = { AVR_IO_REGBIT(TCCR0, WGM00), AVR_IO_REGBIT(TCCR0, WGM01) },
219 [0] = AVR_TIMER_WGM_NORMAL8(),
221 [2] = AVR_TIMER_WGM_CTC(),
222 [3] = AVR_TIMER_WGM_FASTPWM8(),
224 .cs = { AVR_IO_REGBIT(TCCR0, CS00), AVR_IO_REGBIT(TCCR0, CS01), AVR_IO_REGBIT(TCCR0, CS02) },
225 // .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ },
226 .cs_div = { 0, 0, 3 /* 8 */, 5 /* 32 */, 6 /* 64 */, 7 /* 128 */, 8 /* 256 */, 10 /* 1024 */},
228 // asynchronous timer source bit.. if set, use 32khz frequency
229 .as2 = AVR_IO_REGBIT(ASSR, AS0),
234 .enable = AVR_IO_REGBIT(TIMSK, TOIE0),
235 .raised = AVR_IO_REGBIT(TIFR, TOV0),
236 .vector = TIMER0_OVF_vect,
239 [AVR_TIMER_COMPA] = {
241 .com = AVR_IO_REGBITS(TCCR0, COM00, 0x3),
242 .com_pin = AVR_IO_REGBIT(PORTB, PB4),
244 .enable = AVR_IO_REGBIT(TIMSK, OCIE0),
245 .raised = AVR_IO_REGBIT(TIFR, OCF0),
246 .vector = TIMER0_COMP_vect,
253 .wgm = { AVR_IO_REGBIT(TCCR1A, WGM10), AVR_IO_REGBIT(TCCR1A, WGM11),
254 AVR_IO_REGBIT(TCCR1B, WGM12), AVR_IO_REGBIT(TCCR1B, WGM13) },
256 [0] = AVR_TIMER_WGM_NORMAL16(),
257 // TODO: 1 PWM phase correct 8bit
258 // 2 PWM phase correct 9bit
259 // 3 PWM phase correct 10bit
260 [4] = AVR_TIMER_WGM_CTC(),
261 [5] = AVR_TIMER_WGM_FASTPWM8(),
262 [6] = AVR_TIMER_WGM_FASTPWM9(),
263 [7] = AVR_TIMER_WGM_FASTPWM10(),
264 // TODO: 8, 9 PWM phase and freq correct ICR & 10, 11
265 [12] = AVR_TIMER_WGM_ICCTC(),
266 [14] = AVR_TIMER_WGM_ICPWM(),
267 [15] = AVR_TIMER_WGM_OCPWM(),
269 .cs = { AVR_IO_REGBIT(TCCR1B, CS10), AVR_IO_REGBIT(TCCR1B, CS11), AVR_IO_REGBIT(TCCR1B, CS12) },
270 .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ /* TODO: 2 External clocks */},
277 .ices = AVR_IO_REGBIT(TCCR1B, ICES1),
278 .icp = AVR_IO_REGBIT(PORTD, 4),
281 .enable = AVR_IO_REGBIT(TIMSK, TOIE1),
282 .raised = AVR_IO_REGBIT(TIFR, TOV1),
283 .vector = TIMER1_OVF_vect,
286 .enable = AVR_IO_REGBIT(TIMSK, TICIE1),
287 .raised = AVR_IO_REGBIT(TIFR, ICF1),
288 .vector = TIMER1_CAPT_vect,
291 [AVR_TIMER_COMPA] = {
293 .r_ocrh = OCR1AH, // 16 bits timers have two bytes of it
294 .com = AVR_IO_REGBITS(TCCR1A, COM1A0, 0x3),
295 .com_pin = AVR_IO_REGBIT(PORTB, PB5),
297 .enable = AVR_IO_REGBIT(TIMSK, OCIE1A),
298 .raised = AVR_IO_REGBIT(TIFR, OCF1A),
299 .vector = TIMER1_COMPA_vect,
302 [AVR_TIMER_COMPB] = {
305 .com = AVR_IO_REGBITS(TCCR1A, COM1B0, 0x3),
306 .com_pin = AVR_IO_REGBIT(PORTB, PB6),
308 .enable = AVR_IO_REGBIT(TIMSK, OCIE1B),
309 .raised = AVR_IO_REGBIT(TIFR, OCF1B),
310 .vector = TIMER1_COMPB_vect,
313 [AVR_TIMER_COMPC] = {
316 .com = AVR_IO_REGBITS(TCCR1A, COM1C0, 0x3),
317 .com_pin = AVR_IO_REGBIT(PORTB, PB7), // same as timer2
319 .enable = AVR_IO_REGBIT(ETIMSK, OCIE1C),
320 .raised = AVR_IO_REGBIT(ETIFR, OCF1C),
321 .vector = TIMER1_COMPC_vect,
329 .wgm = { AVR_IO_REGBIT(TCCR2, WGM20), AVR_IO_REGBIT(TCCR2, WGM21) },
331 [0] = AVR_TIMER_WGM_NORMAL8(),
332 // TODO 1 pwm phase correct
333 [2] = AVR_TIMER_WGM_CTC(),
334 [3] = AVR_TIMER_WGM_FASTPWM8(),
336 .cs = { AVR_IO_REGBIT(TCCR2, CS20), AVR_IO_REGBIT(TCCR2, CS21), AVR_IO_REGBIT(TCCR2, CS22) },
337 .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ /* TODO external clock */ },
342 .enable = AVR_IO_REGBIT(TIMSK, TOIE2),
343 .raised = AVR_IO_REGBIT(TIFR, TOV2),
344 .vector = TIMER2_OVF_vect,
347 [AVR_TIMER_COMPA] = {
349 .com = AVR_IO_REGBITS(TCCR2, COM20, 0x3),
350 .com_pin = AVR_IO_REGBIT(PORTB, PB7), // same as timer1C
352 .enable = AVR_IO_REGBIT(TIMSK, OCIE2),
353 .raised = AVR_IO_REGBIT(TIFR, OCF2),
354 .vector = TIMER2_COMP_vect,
361 .wgm = { AVR_IO_REGBIT(TCCR3A, WGM30), AVR_IO_REGBIT(TCCR3A, WGM31),
362 AVR_IO_REGBIT(TCCR3B, WGM32), AVR_IO_REGBIT(TCCR3B, WGM33) },
364 [0] = AVR_TIMER_WGM_NORMAL16(),
365 // TODO: 1 PWM phase correct 8bit
366 // 2 PWM phase correct 9bit
367 // 3 PWM phase correct 10bit
368 [4] = AVR_TIMER_WGM_CTC(),
369 [5] = AVR_TIMER_WGM_FASTPWM8(),
370 [6] = AVR_TIMER_WGM_FASTPWM9(),
371 [7] = AVR_TIMER_WGM_FASTPWM10(),
372 // TODO: 8 PWM phase and freq correct ICR
373 // 9 PWM phase and freq correct OCR
376 [12] = AVR_TIMER_WGM_ICCTC(),
377 [14] = AVR_TIMER_WGM_ICPWM(),
378 [15] = AVR_TIMER_WGM_OCPWM(),
380 .cs = { AVR_IO_REGBIT(TCCR3B, CS30), AVR_IO_REGBIT(TCCR3B, CS31), AVR_IO_REGBIT(TCCR3B, CS32) },
381 .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ /* TODO: 2 External clocks */},
388 .ices = AVR_IO_REGBIT(TCCR3B, ICES3),
389 .icp = AVR_IO_REGBIT(PORTE, 7),
392 .enable = AVR_IO_REGBIT(ETIMSK, TOIE3),
393 .raised = AVR_IO_REGBIT(ETIFR, TOV3),
394 .vector = TIMER3_OVF_vect,
397 [AVR_TIMER_COMPA] = {
399 .r_ocrh = OCR3AH, // 16 bits timers have two bytes of it
400 .com = AVR_IO_REGBITS(TCCR3A, COM3A0, 0x3),
401 .com_pin = AVR_IO_REGBIT(PORTE, PE3),
403 .enable = AVR_IO_REGBIT(ETIMSK, OCIE3A),
404 .raised = AVR_IO_REGBIT(ETIFR, OCF3A),
405 .vector = TIMER3_COMPA_vect,
408 [AVR_TIMER_COMPB] = {
411 .com = AVR_IO_REGBITS(TCCR3A, COM3B0, 0x3),
412 .com_pin = AVR_IO_REGBIT(PORTE, PE4),
414 .enable = AVR_IO_REGBIT(ETIMSK, OCIE3B),
415 .raised = AVR_IO_REGBIT(ETIFR, OCF3B),
416 .vector = TIMER3_COMPB_vect,
419 [AVR_TIMER_COMPC] = {
422 .com = AVR_IO_REGBITS(TCCR3A, COM3C0, 0x3),
423 .com_pin = AVR_IO_REGBIT(PORTE, PE5),
425 .enable = AVR_IO_REGBIT(ETIMSK, OCIE3C),
426 .raised = AVR_IO_REGBIT(ETIFR, OCF3C),
427 .vector = TIMER3_COMPC_vect,
432 .enable = AVR_IO_REGBIT(ETIMSK, TICIE3),
433 .raised = AVR_IO_REGBIT(ETIFR, ICF3),
434 .vector = TIMER3_CAPT_vect,
443 .spe = AVR_IO_REGBIT(SPCR, SPE),
444 .mstr = AVR_IO_REGBIT(SPCR, MSTR),
446 .spr = { AVR_IO_REGBIT(SPCR, SPR0), AVR_IO_REGBIT(SPCR, SPR1), AVR_IO_REGBIT(SPSR, SPI2X) },
448 .enable = AVR_IO_REGBIT(SPCR, SPIE),
449 .raised = AVR_IO_REGBIT(SPSR, SPIF),
450 .vector = SPI_STC_vect,
461 // no .r_twamr = TWAMR,
463 .twen = AVR_IO_REGBIT(TWCR, TWEN),
464 .twea = AVR_IO_REGBIT(TWCR, TWEA),
465 .twsta = AVR_IO_REGBIT(TWCR, TWSTA),
466 .twsto = AVR_IO_REGBIT(TWCR, TWSTO),
467 .twwc = AVR_IO_REGBIT(TWCR, TWWC),
469 .twsr = AVR_IO_REGBITS(TWSR, TWS3, 0x1f), // 5 bits
470 .twps = AVR_IO_REGBITS(TWSR, TWPS0, 0x3), // 2 bits
473 .enable = AVR_IO_REGBIT(TWCR, TWIE),
474 .raised = AVR_IO_REGBIT(TWCR, TWINT),
482 static avr_t * make()
484 return avr_core_allocate(&mcu_mega128.core, sizeof(struct mcu_t));
487 avr_kind_t mega128 = {
488 .names = { "atmega128", "atmega128L" },
492 void m128_init(struct avr_t * avr)
494 struct mcu_t * mcu = (struct mcu_t*)avr;
496 avr_eeprom_init(avr, &mcu->eeprom);
497 avr_flash_init(avr, &mcu->selfprog);
498 avr_extint_init(avr, &mcu->extint);
499 avr_watchdog_init(avr, &mcu->watchdog);
500 avr_ioport_init(avr, &mcu->porta);
501 avr_ioport_init(avr, &mcu->portb);
502 avr_ioport_init(avr, &mcu->portc);
503 avr_ioport_init(avr, &mcu->portd);
504 avr_ioport_init(avr, &mcu->porte);
505 avr_ioport_init(avr, &mcu->portf);
506 avr_ioport_init(avr, &mcu->portg);
507 avr_uart_init(avr, &mcu->uart0);
508 avr_uart_init(avr, &mcu->uart1);
509 avr_adc_init(avr, &mcu->adc);
510 avr_timer_init(avr, &mcu->timer0);
511 avr_timer_init(avr, &mcu->timer1);
512 avr_timer_init(avr, &mcu->timer2);
513 avr_timer_init(avr, &mcu->timer3);
514 avr_spi_init(avr, &mcu->spi);
515 avr_twi_init(avr, &mcu->twi);
518 void m128_reset(struct avr_t * avr)
520 // struct mcu_t * mcu = (struct mcu_t*)avr;