4 Copyright 2008, 2009 Michel Pollet <buserror@gmail.com>
6 This file is part of simavr.
8 simavr is free software: you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation, either version 3 of the License, or
11 (at your option) any later version.
13 simavr is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with simavr. If not, see <http://www.gnu.org/licenses/>.
24 #include "sim_core_declare.h"
25 #include "avr_eeprom.h"
26 #include "avr_flash.h"
27 #include "avr_watchdog.h"
28 #include "avr_extint.h"
29 #include "avr_ioport.h"
32 #include "avr_timer.h"
36 void m128_init(struct avr_t * avr);
37 void m128_reset(struct avr_t * avr);
41 #include "avr/iom128.h"
44 * This is a template for all of the 128 devices, hopefuly
50 avr_watchdog_t watchdog;
52 avr_ioport_t porta, portb, portc, portd, porte, portf, portg;
53 avr_uart_t uart0,uart1;
55 avr_timer_t timer0,timer1,timer2,timer3;
66 .rampz = RAMPZ, // extended program memory access
68 AVR_EEPROM_DECLARE_NOEEPM(EE_READY_vect),
69 AVR_SELFPROG_DECLARE(SPMCSR, SPMEN, SPM_READY_vect),
70 AVR_WATCHDOG_DECLARE_128(WDTCR, _VECTOR(0)),
72 AVR_EXTINT_DECLARE(0, 'D', PD0),
73 AVR_EXTINT_DECLARE(1, 'D', PD1),
74 AVR_EXTINT_DECLARE(2, 'D', PD2),
75 AVR_EXTINT_DECLARE(3, 'D', PD3),
76 AVR_EXTINT_DECLARE(4, 'E', PE4),
77 AVR_EXTINT_DECLARE(5, 'E', PE5),
78 AVR_EXTINT_DECLARE(6, 'E', PE6),
79 AVR_EXTINT_DECLARE(7, 'E', PE7),
81 .porta = { // no PCINTs in atmega128
82 .name = 'A', .r_port = PORTA, .r_ddr = DDRA, .r_pin = PINA,
85 .name = 'B', .r_port = PORTB, .r_ddr = DDRB, .r_pin = PINB,
88 .name = 'C', .r_port = PORTC, .r_ddr = DDRC, .r_pin = PINC,
91 .name = 'D', .r_port = PORTD, .r_ddr = DDRD, .r_pin = PIND,
94 .name = 'E', .r_port = PORTE, .r_ddr = DDRE, .r_pin = PINE,
97 .name = 'F', .r_port = PORTF, .r_ddr = DDRF, .r_pin = PINF,
100 .name = 'G', .r_port = PORTG, .r_ddr = DDRG, .r_pin = PING,
104 // no PRUSART .disabled = AVR_IO_REGBIT(PRR,PRUSART0),
108 .txen = AVR_IO_REGBIT(UCSR0B, TXEN0),
109 .rxen = AVR_IO_REGBIT(UCSR0B, RXEN0),
117 .enable = AVR_IO_REGBIT(UCSR0B, RXCIE0),
118 .raised = AVR_IO_REGBIT(UCSR0A, RXC0),
119 .vector = USART0_RX_vect,
122 .enable = AVR_IO_REGBIT(UCSR0B, TXCIE0),
123 .raised = AVR_IO_REGBIT(UCSR0A, TXC0),
124 .vector = USART0_TX_vect,
127 .enable = AVR_IO_REGBIT(UCSR0B, UDRIE0),
128 .raised = AVR_IO_REGBIT(UCSR0A, UDRE0),
129 .vector = USART0_UDRE_vect,
133 // no PRUSART .disabled = AVR_IO_REGBIT(PRR,PRUSART1),
137 .txen = AVR_IO_REGBIT(UCSR1B, TXEN1),
138 .rxen = AVR_IO_REGBIT(UCSR1B, RXEN1),
146 .enable = AVR_IO_REGBIT(UCSR1B, RXCIE1),
147 .raised = AVR_IO_REGBIT(UCSR1A, RXC1),
148 .vector = USART1_RX_vect,
151 .enable = AVR_IO_REGBIT(UCSR1B, TXCIE1),
152 .raised = AVR_IO_REGBIT(UCSR1A, TXC1),
153 .vector = USART1_TX_vect,
156 .enable = AVR_IO_REGBIT(UCSR1B, UDRIE1),
157 .raised = AVR_IO_REGBIT(UCSR1A, UDRE1),
158 .vector = USART1_UDRE_vect,
163 .mux = { AVR_IO_REGBIT(ADMUX, MUX0), AVR_IO_REGBIT(ADMUX, MUX1),
164 AVR_IO_REGBIT(ADMUX, MUX2), AVR_IO_REGBIT(ADMUX, MUX3),
165 AVR_IO_REGBIT(ADMUX, MUX4),},
166 .ref = { AVR_IO_REGBIT(ADMUX, REFS0), AVR_IO_REGBIT(ADMUX, REFS1)},
167 .adlar = AVR_IO_REGBIT(ADMUX, ADLAR),
169 .aden = AVR_IO_REGBIT(ADCSRA, ADEN),
170 .adsc = AVR_IO_REGBIT(ADCSRA, ADSC),
171 // no ADATE .adate = AVR_IO_REGBIT(ADCSRA, ADATE),
172 .adps = { AVR_IO_REGBIT(ADCSRA, ADPS0), AVR_IO_REGBIT(ADCSRA, ADPS1), AVR_IO_REGBIT(ADCSRA, ADPS2),},
177 //.r_adcsrb = ADCSRB,
178 // .adts = { AVR_IO_REGBIT(ADCSRB, ADTS0), AVR_IO_REGBIT(ADCSRB, ADTS1), AVR_IO_REGBIT(ADCSRB, ADTS2),},
181 .enable = AVR_IO_REGBIT(ADCSRA, ADIE),
182 .raised = AVR_IO_REGBIT(ADCSRA, ADIF),
188 .wgm = { AVR_IO_REGBIT(TCCR0, WGM00), AVR_IO_REGBIT(TCCR0, WGM01) },
190 [0] = AVR_TIMER_WGM_NORMAL8(),
192 [2] = AVR_TIMER_WGM_CTC(),
193 [3] = AVR_TIMER_WGM_FASTPWM8(),
195 .cs = { AVR_IO_REGBIT(TCCR0, CS00), AVR_IO_REGBIT(TCCR0, CS01), AVR_IO_REGBIT(TCCR0, CS02) },
196 // .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ },
197 .cs_div = { 0, 0, 3 /* 8 */, 5 /* 32 */, 6 /* 64 */, 7 /* 128 */, 8 /* 256 */, 10 /* 1024 */},
199 // asynchronous timer source bit.. if set, use 32khz frequency
200 .as2 = AVR_IO_REGBIT(ASSR, AS0),
205 .enable = AVR_IO_REGBIT(TIMSK, TOIE0),
206 .raised = AVR_IO_REGBIT(TIFR, TOV0),
207 .vector = TIMER0_OVF_vect,
210 [AVR_TIMER_COMPA] = {
213 .enable = AVR_IO_REGBIT(TIMSK, OCIE0),
214 .raised = AVR_IO_REGBIT(TIFR, OCF0),
215 .vector = TIMER0_COMP_vect,
222 .wgm = { AVR_IO_REGBIT(TCCR1A, WGM10), AVR_IO_REGBIT(TCCR1A, WGM11),
223 AVR_IO_REGBIT(TCCR1B, WGM12), AVR_IO_REGBIT(TCCR1B, WGM13) },
225 [0] = AVR_TIMER_WGM_NORMAL16(),
226 // TODO: 1 PWM phase corret 8bit
227 // 2 PWM phase corret 9bit
228 // 3 PWM phase corret 10bit
229 [4] = AVR_TIMER_WGM_CTC(),
230 [5] = AVR_TIMER_WGM_FASTPWM8(),
231 [6] = AVR_TIMER_WGM_FASTPWM9(),
232 [7] = AVR_TIMER_WGM_FASTPWM10(),
233 // TODO: 8, 9 PWM phase and freq correct ICR & 10, 11
234 [12] = AVR_TIMER_WGM_ICCTC(),
235 [14] = AVR_TIMER_WGM_ICPWM(),
236 [15] = AVR_TIMER_WGM_OCPWM(),
238 .cs = { AVR_IO_REGBIT(TCCR1B, CS10), AVR_IO_REGBIT(TCCR1B, CS11), AVR_IO_REGBIT(TCCR1B, CS12) },
239 .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ /* TODO: 2 External clocks */},
247 .enable = AVR_IO_REGBIT(TIMSK, TOIE1),
248 .raised = AVR_IO_REGBIT(TIFR, TOV1),
249 .vector = TIMER1_OVF_vect,
252 .enable = AVR_IO_REGBIT(TIMSK, TICIE1),
253 .raised = AVR_IO_REGBIT(TIFR, ICF1),
254 .vector = TIMER1_CAPT_vect,
257 [AVR_TIMER_COMPA] = {
259 .r_ocrh = OCR1AH, // 16 bits timers have two bytes of it
261 .enable = AVR_IO_REGBIT(TIMSK, OCIE1A),
262 .raised = AVR_IO_REGBIT(TIFR, OCF1A),
263 .vector = TIMER1_COMPA_vect,
266 [AVR_TIMER_COMPB] = {
270 .enable = AVR_IO_REGBIT(TIMSK, OCIE1B),
271 .raised = AVR_IO_REGBIT(TIFR, OCF1B),
272 .vector = TIMER1_COMPB_vect,
275 [AVR_TIMER_COMPC] = {
279 .enable = AVR_IO_REGBIT(ETIMSK, OCIE1C),
280 .raised = AVR_IO_REGBIT(ETIFR, OCF1C),
281 .vector = TIMER1_COMPC_vect,
289 .wgm = { AVR_IO_REGBIT(TCCR2, WGM20), AVR_IO_REGBIT(TCCR2, WGM21) },
291 [0] = AVR_TIMER_WGM_NORMAL8(),
292 // TODO 1 pwm phase correct
293 [2] = AVR_TIMER_WGM_CTC(),
294 [3] = AVR_TIMER_WGM_FASTPWM8(),
296 .cs = { AVR_IO_REGBIT(TCCR2, CS20), AVR_IO_REGBIT(TCCR2, CS21), AVR_IO_REGBIT(TCCR2, CS22) },
297 .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ /* TODO external clock */ },
302 .enable = AVR_IO_REGBIT(TIMSK, TOIE2),
303 .raised = AVR_IO_REGBIT(TIFR, TOV2),
304 .vector = TIMER2_OVF_vect,
307 [AVR_TIMER_COMPA] = {
310 .enable = AVR_IO_REGBIT(TIMSK, OCIE2),
311 .raised = AVR_IO_REGBIT(TIFR, OCF2),
312 .vector = TIMER2_COMP_vect,
319 .wgm = { AVR_IO_REGBIT(TCCR3A, WGM30), AVR_IO_REGBIT(TCCR3A, WGM31),
320 AVR_IO_REGBIT(TCCR3B, WGM32), AVR_IO_REGBIT(TCCR3B, WGM33) },
322 [0] = AVR_TIMER_WGM_NORMAL16(),
323 // TODO: 1 PWM phase corret 8bit
324 // 2 PWM phase corret 9bit
325 // 3 PWM phase corret 10bit
326 [4] = AVR_TIMER_WGM_CTC(),
327 [5] = AVR_TIMER_WGM_FASTPWM8(),
328 [6] = AVR_TIMER_WGM_FASTPWM9(),
329 [7] = AVR_TIMER_WGM_FASTPWM10(),
330 // TODO: 8 PWM phase and freq corret ICR
331 // 9 PWM phase and freq corret OCR
334 [12] = AVR_TIMER_WGM_ICCTC(),
335 [14] = AVR_TIMER_WGM_ICPWM(),
336 [15] = AVR_TIMER_WGM_OCPWM(),
338 .cs = { AVR_IO_REGBIT(TCCR3B, CS30), AVR_IO_REGBIT(TCCR3B, CS31), AVR_IO_REGBIT(TCCR3B, CS32) },
339 .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ /* TODO: 2 External clocks */},
347 .enable = AVR_IO_REGBIT(ETIMSK, TOIE3),
348 .raised = AVR_IO_REGBIT(ETIFR, TOV3),
349 .vector = TIMER3_OVF_vect,
352 [AVR_TIMER_COMPA] = {
354 .r_ocrh = OCR3AH, // 16 bits timers have two bytes of it
355 .com = { AVR_IO_REGBIT(TCCR3A, COM3A1), AVR_IO_REGBIT(TCCR3A, COM3A0) },
356 .com_pin = AVR_IO_REGBIT(PORTE, PE3),
358 .enable = AVR_IO_REGBIT(ETIMSK, OCIE3A),
359 .raised = AVR_IO_REGBIT(ETIFR, OCF3A),
360 .vector = TIMER3_COMPA_vect,
363 [AVR_TIMER_COMPB] = {
366 .com = { AVR_IO_REGBIT(TCCR3A, COM3B1), AVR_IO_REGBIT(TCCR3A, COM3B0) },
367 .com_pin = AVR_IO_REGBIT(PORTE, PE4),
369 .enable = AVR_IO_REGBIT(ETIMSK, OCIE3B),
370 .raised = AVR_IO_REGBIT(ETIFR, OCF3B),
371 .vector = TIMER3_COMPB_vect,
374 [AVR_TIMER_COMPC] = {
377 .com = { AVR_IO_REGBIT(TCCR3A, COM3C1), AVR_IO_REGBIT(TCCR3A, COM3C0) },
378 .com_pin = AVR_IO_REGBIT(PORTE, PE5),
380 .enable = AVR_IO_REGBIT(ETIMSK, OCIE3C),
381 .raised = AVR_IO_REGBIT(ETIFR, OCF3C),
382 .vector = TIMER3_COMPC_vect,
387 .enable = AVR_IO_REGBIT(ETIMSK, TICIE3),
388 .raised = AVR_IO_REGBIT(ETIFR, ICF3),
389 .vector = TIMER3_CAPT_vect,
398 .spe = AVR_IO_REGBIT(SPCR, SPE),
399 .mstr = AVR_IO_REGBIT(SPCR, MSTR),
401 .spr = { AVR_IO_REGBIT(SPCR, SPR0), AVR_IO_REGBIT(SPCR, SPR1), AVR_IO_REGBIT(SPSR, SPI2X) },
403 .enable = AVR_IO_REGBIT(SPCR, SPIE),
404 .raised = AVR_IO_REGBIT(SPSR, SPIF),
405 .vector = SPI_STC_vect,
416 // no .r_twamr = TWAMR,
418 .twen = AVR_IO_REGBIT(TWCR, TWEN),
419 .twea = AVR_IO_REGBIT(TWCR, TWEA),
420 .twsta = AVR_IO_REGBIT(TWCR, TWSTA),
421 .twsto = AVR_IO_REGBIT(TWCR, TWSTO),
422 .twwc = AVR_IO_REGBIT(TWCR, TWWC),
424 .twsr = AVR_IO_REGBITS(TWSR, TWS3, 0x1f), // 5 bits
425 .twps = AVR_IO_REGBITS(TWSR, TWPS0, 0x3), // 2 bits
428 .enable = AVR_IO_REGBIT(TWCR, TWIE),
429 .raised = AVR_IO_REGBIT(TWSR, TWINT),
436 static avr_t * make()
438 return &mcu_mega128.core;
441 avr_kind_t mega128 = {
442 .names = { "atmega128", "atmega128L" },
446 void m128_init(struct avr_t * avr)
448 struct mcu_t * mcu = (struct mcu_t*)avr;
450 printf("%s init\n", avr->mmcu);
452 avr_eeprom_init(avr, &mcu->eeprom);
453 avr_flash_init(avr, &mcu->selfprog);
454 avr_extint_init(avr, &mcu->extint);
455 avr_watchdog_init(avr, &mcu->watchdog);
456 avr_ioport_init(avr, &mcu->porta);
457 avr_ioport_init(avr, &mcu->portb);
458 avr_ioport_init(avr, &mcu->portc);
459 avr_ioport_init(avr, &mcu->portd);
460 avr_ioport_init(avr, &mcu->porte);
461 avr_ioport_init(avr, &mcu->portf);
462 avr_ioport_init(avr, &mcu->portg);
463 avr_uart_init(avr, &mcu->uart0);
464 avr_uart_init(avr, &mcu->uart1);
465 avr_adc_init(avr, &mcu->adc);
466 avr_timer_init(avr, &mcu->timer0);
467 avr_timer_init(avr, &mcu->timer1);
468 avr_timer_init(avr, &mcu->timer2);
469 avr_timer_init(avr, &mcu->timer3);
470 avr_spi_init(avr, &mcu->spi);
471 avr_twi_init(avr, &mcu->twi);
474 void m128_reset(struct avr_t * avr)
476 // struct mcu_t * mcu = (struct mcu_t*)avr;