4 Copyright 2008, 2009 Michel Pollet <buserror@gmail.com>
6 This file is part of simavr.
8 simavr is free software: you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation, either version 3 of the License, or
11 (at your option) any later version.
13 simavr is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with simavr. If not, see <http://www.gnu.org/licenses/>.
24 #include "sim_core_declare.h"
25 #include "avr_eeprom.h"
26 #include "avr_flash.h"
27 #include "avr_watchdog.h"
28 #include "avr_extint.h"
29 #include "avr_ioport.h"
32 #include "avr_timer.h"
36 void m128_init(struct avr_t * avr);
37 void m128_reset(struct avr_t * avr);
41 #include "avr/iom128.h"
44 * This is a template for all of the 128 devices, hopefuly
50 avr_watchdog_t watchdog;
52 avr_ioport_t porta, portb, portc, portd, porte, portf, portg;
53 avr_uart_t uart0,uart1;
55 avr_timer_t timer0,timer1,timer2,timer3;
66 .rampz = RAMPZ, // extended program memory access
68 AVR_EEPROM_DECLARE_NOEEPM(EE_READY_vect),
69 AVR_SELFPROG_DECLARE(SPMCSR, SPMEN, SPM_READY_vect),
70 AVR_WATCHDOG_DECLARE_128(WDTCR, _VECTOR(0)),
72 AVR_EXTINT_DECLARE(0, 'D', PD0),
73 AVR_EXTINT_DECLARE(1, 'D', PD1),
74 AVR_EXTINT_DECLARE(2, 'D', PD2),
75 AVR_EXTINT_DECLARE(3, 'D', PD3),
76 AVR_EXTINT_DECLARE(4, 'E', PE4),
77 AVR_EXTINT_DECLARE(5, 'E', PE5),
78 AVR_EXTINT_DECLARE(6, 'E', PE6),
79 AVR_EXTINT_DECLARE(7, 'E', PE7),
81 .porta = { // no PCINTs in atmega128
82 .name = 'A', .r_port = PORTA, .r_ddr = DDRA, .r_pin = PINA,
85 .name = 'B', .r_port = PORTB, .r_ddr = DDRB, .r_pin = PINB,
88 .name = 'C', .r_port = PORTC, .r_ddr = DDRC, .r_pin = PINC,
91 .name = 'D', .r_port = PORTD, .r_ddr = DDRD, .r_pin = PIND,
94 .name = 'E', .r_port = PORTE, .r_ddr = DDRE, .r_pin = PINE,
97 .name = 'F', .r_port = PORTF, .r_ddr = DDRF, .r_pin = PINF,
100 .name = 'G', .r_port = PORTG, .r_ddr = DDRG, .r_pin = PING,
104 // no PRUSART .disabled = AVR_IO_REGBIT(PRR,PRUSART0),
108 .txen = AVR_IO_REGBIT(UCSR0B, TXEN0),
109 .rxen = AVR_IO_REGBIT(UCSR0B, RXEN0),
117 .enable = AVR_IO_REGBIT(UCSR0B, RXCIE0),
118 .raised = AVR_IO_REGBIT(UCSR0A, RXC0),
119 .vector = USART0_RX_vect,
122 .enable = AVR_IO_REGBIT(UCSR0B, TXCIE0),
123 .raised = AVR_IO_REGBIT(UCSR0A, TXC0),
124 .vector = USART0_TX_vect,
127 .enable = AVR_IO_REGBIT(UCSR0B, UDRIE0),
128 .raised = AVR_IO_REGBIT(UCSR0A, UDRE0),
129 .vector = USART0_UDRE_vect,
133 // no PRUSART .disabled = AVR_IO_REGBIT(PRR,PRUSART1),
137 .txen = AVR_IO_REGBIT(UCSR1B, TXEN1),
138 .rxen = AVR_IO_REGBIT(UCSR1B, RXEN1),
146 .enable = AVR_IO_REGBIT(UCSR1B, RXCIE1),
147 .raised = AVR_IO_REGBIT(UCSR1A, RXC1),
148 .vector = USART1_RX_vect,
151 .enable = AVR_IO_REGBIT(UCSR1B, TXCIE1),
152 .raised = AVR_IO_REGBIT(UCSR1A, TXC1),
153 .vector = USART1_TX_vect,
156 .enable = AVR_IO_REGBIT(UCSR1B, UDRIE1),
157 .raised = AVR_IO_REGBIT(UCSR1A, UDRE1),
158 .vector = USART1_UDRE_vect,
163 .mux = { AVR_IO_REGBIT(ADMUX, MUX0), AVR_IO_REGBIT(ADMUX, MUX1),
164 AVR_IO_REGBIT(ADMUX, MUX2), AVR_IO_REGBIT(ADMUX, MUX3),
165 AVR_IO_REGBIT(ADMUX, MUX4),},
166 .ref = { AVR_IO_REGBIT(ADMUX, REFS0), AVR_IO_REGBIT(ADMUX, REFS1)},
167 .ref_values = { [1] = ADC_VREF_AVCC, [3] = ADC_VREF_V256 },
169 .adlar = AVR_IO_REGBIT(ADMUX, ADLAR),
171 .aden = AVR_IO_REGBIT(ADCSRA, ADEN),
172 .adsc = AVR_IO_REGBIT(ADCSRA, ADSC),
173 // no ADATE .adate = AVR_IO_REGBIT(ADCSRA, ADATE),
174 .adps = { AVR_IO_REGBIT(ADCSRA, ADPS0), AVR_IO_REGBIT(ADCSRA, ADPS1), AVR_IO_REGBIT(ADCSRA, ADPS2),},
179 //.r_adcsrb = ADCSRB,
180 // .adts = { AVR_IO_REGBIT(ADCSRB, ADTS0), AVR_IO_REGBIT(ADCSRB, ADTS1), AVR_IO_REGBIT(ADCSRB, ADTS2),},
183 [0] = AVR_ADC_SINGLE(0), [1] = AVR_ADC_SINGLE(1),
184 [2] = AVR_ADC_SINGLE(2), [3] = AVR_ADC_SINGLE(3),
185 [4] = AVR_ADC_SINGLE(4), [5] = AVR_ADC_SINGLE(5),
186 [6] = AVR_ADC_SINGLE(6), [7] = AVR_ADC_SINGLE(7),
188 [ 8] = AVR_ADC_DIFF(0, 0, 10), [ 9] = AVR_ADC_DIFF(1, 0, 10),
189 [10] = AVR_ADC_DIFF(0, 0, 200), [11] = AVR_ADC_DIFF(1, 0, 200),
190 [12] = AVR_ADC_DIFF(2, 2, 10), [13] = AVR_ADC_DIFF(3, 2, 10),
191 [14] = AVR_ADC_DIFF(2, 2, 200), [15] = AVR_ADC_DIFF(3, 2, 200),
193 [16] = AVR_ADC_DIFF(0, 1, 1), [17] = AVR_ADC_DIFF(1, 1, 1),
194 [18] = AVR_ADC_DIFF(2, 1, 1), [19] = AVR_ADC_DIFF(3, 1, 1),
195 [20] = AVR_ADC_DIFF(4, 1, 1), [21] = AVR_ADC_DIFF(5, 1, 1),
196 [22] = AVR_ADC_DIFF(6, 1, 1), [23] = AVR_ADC_DIFF(7, 1, 1),
198 [24] = AVR_ADC_DIFF(0, 2, 1), [25] = AVR_ADC_DIFF(1, 2, 1),
199 [26] = AVR_ADC_DIFF(2, 2, 1), [27] = AVR_ADC_DIFF(3, 2, 1),
200 [28] = AVR_ADC_DIFF(4, 2, 1), [29] = AVR_ADC_DIFF(5, 2, 1),
202 [30] = AVR_ADC_REF(1230), // 1.1V
203 [31] = AVR_ADC_REF(0), // GND
207 .enable = AVR_IO_REGBIT(ADCSRA, ADIE),
208 .raised = AVR_IO_REGBIT(ADCSRA, ADIF),
214 .wgm = { AVR_IO_REGBIT(TCCR0, WGM00), AVR_IO_REGBIT(TCCR0, WGM01) },
216 [0] = AVR_TIMER_WGM_NORMAL8(),
218 [2] = AVR_TIMER_WGM_CTC(),
219 [3] = AVR_TIMER_WGM_FASTPWM8(),
221 .cs = { AVR_IO_REGBIT(TCCR0, CS00), AVR_IO_REGBIT(TCCR0, CS01), AVR_IO_REGBIT(TCCR0, CS02) },
222 // .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ },
223 .cs_div = { 0, 0, 3 /* 8 */, 5 /* 32 */, 6 /* 64 */, 7 /* 128 */, 8 /* 256 */, 10 /* 1024 */},
225 // asynchronous timer source bit.. if set, use 32khz frequency
226 .as2 = AVR_IO_REGBIT(ASSR, AS0),
231 .enable = AVR_IO_REGBIT(TIMSK, TOIE0),
232 .raised = AVR_IO_REGBIT(TIFR, TOV0),
233 .vector = TIMER0_OVF_vect,
236 [AVR_TIMER_COMPA] = {
238 .com = AVR_IO_REGBITS(TCCR0, COM00, 0x3),
239 .com_pin = AVR_IO_REGBIT(PORTB, PB4),
241 .enable = AVR_IO_REGBIT(TIMSK, OCIE0),
242 .raised = AVR_IO_REGBIT(TIFR, OCF0),
243 .vector = TIMER0_COMP_vect,
250 .wgm = { AVR_IO_REGBIT(TCCR1A, WGM10), AVR_IO_REGBIT(TCCR1A, WGM11),
251 AVR_IO_REGBIT(TCCR1B, WGM12), AVR_IO_REGBIT(TCCR1B, WGM13) },
253 [0] = AVR_TIMER_WGM_NORMAL16(),
254 // TODO: 1 PWM phase corret 8bit
255 // 2 PWM phase corret 9bit
256 // 3 PWM phase corret 10bit
257 [4] = AVR_TIMER_WGM_CTC(),
258 [5] = AVR_TIMER_WGM_FASTPWM8(),
259 [6] = AVR_TIMER_WGM_FASTPWM9(),
260 [7] = AVR_TIMER_WGM_FASTPWM10(),
261 // TODO: 8, 9 PWM phase and freq correct ICR & 10, 11
262 [12] = AVR_TIMER_WGM_ICCTC(),
263 [14] = AVR_TIMER_WGM_ICPWM(),
264 [15] = AVR_TIMER_WGM_OCPWM(),
266 .cs = { AVR_IO_REGBIT(TCCR1B, CS10), AVR_IO_REGBIT(TCCR1B, CS11), AVR_IO_REGBIT(TCCR1B, CS12) },
267 .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ /* TODO: 2 External clocks */},
275 .enable = AVR_IO_REGBIT(TIMSK, TOIE1),
276 .raised = AVR_IO_REGBIT(TIFR, TOV1),
277 .vector = TIMER1_OVF_vect,
280 .enable = AVR_IO_REGBIT(TIMSK, TICIE1),
281 .raised = AVR_IO_REGBIT(TIFR, ICF1),
282 .vector = TIMER1_CAPT_vect,
285 [AVR_TIMER_COMPA] = {
287 .r_ocrh = OCR1AH, // 16 bits timers have two bytes of it
288 .com = AVR_IO_REGBITS(TCCR1A, COM1A0, 0x3),
289 .com_pin = AVR_IO_REGBIT(PORTB, PB5),
291 .enable = AVR_IO_REGBIT(TIMSK, OCIE1A),
292 .raised = AVR_IO_REGBIT(TIFR, OCF1A),
293 .vector = TIMER1_COMPA_vect,
296 [AVR_TIMER_COMPB] = {
299 .com = AVR_IO_REGBITS(TCCR1A, COM1B0, 0x3),
300 .com_pin = AVR_IO_REGBIT(PORTB, PB6),
302 .enable = AVR_IO_REGBIT(TIMSK, OCIE1B),
303 .raised = AVR_IO_REGBIT(TIFR, OCF1B),
304 .vector = TIMER1_COMPB_vect,
307 [AVR_TIMER_COMPC] = {
310 .com = AVR_IO_REGBITS(TCCR1A, COM1C0, 0x3),
311 .com_pin = AVR_IO_REGBIT(PORTB, PB7), // same as timer2
313 .enable = AVR_IO_REGBIT(ETIMSK, OCIE1C),
314 .raised = AVR_IO_REGBIT(ETIFR, OCF1C),
315 .vector = TIMER1_COMPC_vect,
323 .wgm = { AVR_IO_REGBIT(TCCR2, WGM20), AVR_IO_REGBIT(TCCR2, WGM21) },
325 [0] = AVR_TIMER_WGM_NORMAL8(),
326 // TODO 1 pwm phase correct
327 [2] = AVR_TIMER_WGM_CTC(),
328 [3] = AVR_TIMER_WGM_FASTPWM8(),
330 .cs = { AVR_IO_REGBIT(TCCR2, CS20), AVR_IO_REGBIT(TCCR2, CS21), AVR_IO_REGBIT(TCCR2, CS22) },
331 .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ /* TODO external clock */ },
336 .enable = AVR_IO_REGBIT(TIMSK, TOIE2),
337 .raised = AVR_IO_REGBIT(TIFR, TOV2),
338 .vector = TIMER2_OVF_vect,
341 [AVR_TIMER_COMPA] = {
343 .com = AVR_IO_REGBITS(TCCR2, COM20, 0x3),
344 .com_pin = AVR_IO_REGBIT(PORTB, PB7), // same as timer1C
346 .enable = AVR_IO_REGBIT(TIMSK, OCIE2),
347 .raised = AVR_IO_REGBIT(TIFR, OCF2),
348 .vector = TIMER2_COMP_vect,
355 .wgm = { AVR_IO_REGBIT(TCCR3A, WGM30), AVR_IO_REGBIT(TCCR3A, WGM31),
356 AVR_IO_REGBIT(TCCR3B, WGM32), AVR_IO_REGBIT(TCCR3B, WGM33) },
358 [0] = AVR_TIMER_WGM_NORMAL16(),
359 // TODO: 1 PWM phase corret 8bit
360 // 2 PWM phase corret 9bit
361 // 3 PWM phase corret 10bit
362 [4] = AVR_TIMER_WGM_CTC(),
363 [5] = AVR_TIMER_WGM_FASTPWM8(),
364 [6] = AVR_TIMER_WGM_FASTPWM9(),
365 [7] = AVR_TIMER_WGM_FASTPWM10(),
366 // TODO: 8 PWM phase and freq corret ICR
367 // 9 PWM phase and freq corret OCR
370 [12] = AVR_TIMER_WGM_ICCTC(),
371 [14] = AVR_TIMER_WGM_ICPWM(),
372 [15] = AVR_TIMER_WGM_OCPWM(),
374 .cs = { AVR_IO_REGBIT(TCCR3B, CS30), AVR_IO_REGBIT(TCCR3B, CS31), AVR_IO_REGBIT(TCCR3B, CS32) },
375 .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ /* TODO: 2 External clocks */},
383 .enable = AVR_IO_REGBIT(ETIMSK, TOIE3),
384 .raised = AVR_IO_REGBIT(ETIFR, TOV3),
385 .vector = TIMER3_OVF_vect,
388 [AVR_TIMER_COMPA] = {
390 .r_ocrh = OCR3AH, // 16 bits timers have two bytes of it
391 .com = AVR_IO_REGBITS(TCCR3A, COM3A0, 0x3),
392 .com_pin = AVR_IO_REGBIT(PORTE, PE3),
394 .enable = AVR_IO_REGBIT(ETIMSK, OCIE3A),
395 .raised = AVR_IO_REGBIT(ETIFR, OCF3A),
396 .vector = TIMER3_COMPA_vect,
399 [AVR_TIMER_COMPB] = {
402 .com = AVR_IO_REGBITS(TCCR3A, COM3B0, 0x3),
403 .com_pin = AVR_IO_REGBIT(PORTE, PE4),
405 .enable = AVR_IO_REGBIT(ETIMSK, OCIE3B),
406 .raised = AVR_IO_REGBIT(ETIFR, OCF3B),
407 .vector = TIMER3_COMPB_vect,
410 [AVR_TIMER_COMPC] = {
413 .com = AVR_IO_REGBITS(TCCR3A, COM3C0, 0x3),
414 .com_pin = AVR_IO_REGBIT(PORTE, PE5),
416 .enable = AVR_IO_REGBIT(ETIMSK, OCIE3C),
417 .raised = AVR_IO_REGBIT(ETIFR, OCF3C),
418 .vector = TIMER3_COMPC_vect,
423 .enable = AVR_IO_REGBIT(ETIMSK, TICIE3),
424 .raised = AVR_IO_REGBIT(ETIFR, ICF3),
425 .vector = TIMER3_CAPT_vect,
434 .spe = AVR_IO_REGBIT(SPCR, SPE),
435 .mstr = AVR_IO_REGBIT(SPCR, MSTR),
437 .spr = { AVR_IO_REGBIT(SPCR, SPR0), AVR_IO_REGBIT(SPCR, SPR1), AVR_IO_REGBIT(SPSR, SPI2X) },
439 .enable = AVR_IO_REGBIT(SPCR, SPIE),
440 .raised = AVR_IO_REGBIT(SPSR, SPIF),
441 .vector = SPI_STC_vect,
452 // no .r_twamr = TWAMR,
454 .twen = AVR_IO_REGBIT(TWCR, TWEN),
455 .twea = AVR_IO_REGBIT(TWCR, TWEA),
456 .twsta = AVR_IO_REGBIT(TWCR, TWSTA),
457 .twsto = AVR_IO_REGBIT(TWCR, TWSTO),
458 .twwc = AVR_IO_REGBIT(TWCR, TWWC),
460 .twsr = AVR_IO_REGBITS(TWSR, TWS3, 0x1f), // 5 bits
461 .twps = AVR_IO_REGBITS(TWSR, TWPS0, 0x3), // 2 bits
464 .enable = AVR_IO_REGBIT(TWCR, TWIE),
465 .raised = AVR_IO_REGBIT(TWSR, TWINT),
472 static avr_t * make()
474 return &mcu_mega128.core;
477 avr_kind_t mega128 = {
478 .names = { "atmega128", "atmega128L" },
482 void m128_init(struct avr_t * avr)
484 struct mcu_t * mcu = (struct mcu_t*)avr;
486 printf("%s init\n", avr->mmcu);
488 avr_eeprom_init(avr, &mcu->eeprom);
489 avr_flash_init(avr, &mcu->selfprog);
490 avr_extint_init(avr, &mcu->extint);
491 avr_watchdog_init(avr, &mcu->watchdog);
492 avr_ioport_init(avr, &mcu->porta);
493 avr_ioport_init(avr, &mcu->portb);
494 avr_ioport_init(avr, &mcu->portc);
495 avr_ioport_init(avr, &mcu->portd);
496 avr_ioport_init(avr, &mcu->porte);
497 avr_ioport_init(avr, &mcu->portf);
498 avr_ioport_init(avr, &mcu->portg);
499 avr_uart_init(avr, &mcu->uart0);
500 avr_uart_init(avr, &mcu->uart1);
501 avr_adc_init(avr, &mcu->adc);
502 avr_timer_init(avr, &mcu->timer0);
503 avr_timer_init(avr, &mcu->timer1);
504 avr_timer_init(avr, &mcu->timer2);
505 avr_timer_init(avr, &mcu->timer3);
506 avr_spi_init(avr, &mcu->spi);
507 avr_twi_init(avr, &mcu->twi);
510 void m128_reset(struct avr_t * avr)
512 // struct mcu_t * mcu = (struct mcu_t*)avr;