git.rot13.org Git - simavr/blob - simavr/cores/sim_mega1280.c

   1 /*
   2         sim_mega1280.c
   3
   4         Copyright 2008, 2009 Michel Pollet <buserror@gmail.com>
   5
   6         This file is part of simavr.
   7
   8         simavr is free software: you can redistribute it and/or modify
   9         it under the terms of the GNU General Public License as published by
  10         the Free Software Foundation, either version 3 of the License, or
  11         (at your option) any later version.
  12
  13         simavr is distributed in the hope that it will be useful,
  14         but WITHOUT ANY WARRANTY; without even the implied warranty of
  15         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16         GNU General Public License for more details.
  17
  18         You should have received a copy of the GNU General Public License
  19         along with simavr.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include <stdio.h>
  23 #include "sim_avr.h"
  24 #include "sim_core_declare.h"
  25 #include "avr_eeprom.h"
  26 #include "avr_flash.h"
  27 #include "avr_watchdog.h"
  28 #include "avr_extint.h"
  29 #include "avr_ioport.h"
  30 #include "avr_uart.h"
  31 #include "avr_adc.h"
  32 #include "avr_timer.h"
  33 #include "avr_spi.h"
  34 #include "avr_twi.h"
  35
  36 void m1280_init(struct avr_t * avr);
  37 void m1280_reset(struct avr_t * avr);
  38
  39 #define _AVR_IO_H_
  40 #define __ASSEMBLER__
  41 #ifndef __AVR_ATmega1280__
  42 #define __AVR_ATmega1280__
  43 #endif
  44 #include "avr/iom1280.h"
  45
  46 /*
  47  * This is a template for all of the 1280 devices, hopefully
  48  */
  49 const struct mcu_t {
  50         avr_t          core;
  51         avr_eeprom_t    eeprom;
  52         avr_flash_t     selfprog;
  53         avr_watchdog_t  watchdog;
  54         avr_extint_t    extint;
  55         avr_ioport_t    porta, portb, portc, portd, porte, portf, portg, porth, portj, portk, portl;
  56         avr_uart_t              uart0,uart1;
  57         avr_uart_t              uart2,uart3;
  58         avr_adc_t               adc;
  59         avr_timer_t             timer0,timer1,timer2,timer3,timer4,timer5;
  60         avr_spi_t               spi;
  61         avr_twi_t               twi;
  62  }mcu_mega1280 = {
  63         .core = {
  64                 .mmcu = "atmega1280",
  65                 DEFAULT_CORE(4),
  66
  67                 .init = m1280_init,
  68                 .reset = m1280_reset,
  69
  70                 .rampz = RAMPZ, // extended program memory access
  71         },
  72         AVR_EEPROM_DECLARE(EE_READY_vect),
  73         AVR_SELFPROG_DECLARE(SPMCSR, SPMEN, SPM_READY_vect),
  74         AVR_WATCHDOG_DECLARE(WDTCSR, WDT_vect),
  75         .extint = {
  76                 AVR_EXTINT_DECLARE(0, 'D', PD0),
  77                 AVR_EXTINT_DECLARE(1, 'D', PD1),
  78                 AVR_EXTINT_DECLARE(2, 'D', PD2),
  79                 AVR_EXTINT_DECLARE(3, 'D', PD3),
  80                 AVR_EXTINT_DECLARE(4, 'E', PE4),
  81                 AVR_EXTINT_DECLARE(5, 'E', PE5),
  82                 AVR_EXTINT_DECLARE(6, 'E', PE6),
  83                 AVR_EXTINT_DECLARE(7, 'E', PE7),
  84         },
  85         .porta = {
  86                 .name = 'A', .r_port = PORTA, .r_ddr = DDRA, .r_pin = PINA,
  87         },
  88         .portb = {
  89                 .name = 'B', .r_port = PORTB, .r_ddr = DDRB, .r_pin = PINB,
  90                 .pcint = {
  91                         .enable = AVR_IO_REGBIT(PCICR, PCIE0),
  92                         .raised = AVR_IO_REGBIT(PCIFR, PCIF0),
  93                         .vector = PCINT0_vect,
  94                 },
  95                 .r_pcint = PCMSK0,
  96         },
  97         .portc = {
  98                 .name = 'C', .r_port = PORTC, .r_ddr = DDRC, .r_pin = PINC,
  99         },
 100         .portd = {
 101                 .name = 'D', .r_port = PORTD, .r_ddr = DDRD, .r_pin = PIND,
 102         },
 103         .porte = {
 104                 .name = 'E', .r_port = PORTE, .r_ddr = DDRE, .r_pin = PINE,
 105         },
 106         .portf = {
 107                 .name = 'F', .r_port = PORTF, .r_ddr = DDRF, .r_pin = PINF,
 108         },
 109         .portg = {
 110                 .name = 'G', .r_port = PORTG, .r_ddr = DDRG, .r_pin = PING,
 111         },
 112
 113         .porth = {
 114                 .name = 'H', .r_port = PORTH, .r_ddr = DDRH, .r_pin = PINH,
 115         },
 116         .portj = {
 117                 .name = 'J', .r_port = PORTJ, .r_ddr = DDRJ, .r_pin = PINJ,
 118         },
 119         .portk = {
 120                 .name = 'K', .r_port = PORTK, .r_ddr = DDRK, .r_pin = PINK,
 121         },
 122         .portl = {
 123                 .name = 'L', .r_port = PORTL, .r_ddr = DDRL, .r_pin = PINL,
 124         },
 125
 126         .uart0 = {
 127                 .disabled = AVR_IO_REGBIT(PRR0,PRUSART0),
 128                 .name = '0',
 129                 .r_udr = UDR0,
 130
 131                 .txen = AVR_IO_REGBIT(UCSR0B, TXEN0),
 132                 .rxen = AVR_IO_REGBIT(UCSR0B, RXEN0),
 133                 .ucsz = AVR_IO_REGBITS(UCSR0C, UCSZ00, 0x3), // 2 bits
 134                 .ucsz2 = AVR_IO_REGBIT(UCSR0B, UCSZ02),         // 1 bits
 135
 136                 .r_ucsra = UCSR0A,
 137                 .r_ucsrb = UCSR0B,
 138                 .r_ucsrc = UCSR0C,
 139                 .r_ubrrl = UBRR0L,
 140                 .r_ubrrh = UBRR0H,
 141                 .rxc = {
 142                         .enable = AVR_IO_REGBIT(UCSR0B, RXCIE0),
 143                         .raised = AVR_IO_REGBIT(UCSR0A, RXC0),
 144                         .vector = USART0_RX_vect,
 145                 },
 146                 .txc = {
 147                         .enable = AVR_IO_REGBIT(UCSR0B, TXCIE0),
 148                         .raised = AVR_IO_REGBIT(UCSR0A, TXC0),
 149                         .vector = USART0_TX_vect,
 150                 },
 151                 .udrc = {
 152                         .enable = AVR_IO_REGBIT(UCSR0B, UDRIE0),
 153                         .raised = AVR_IO_REGBIT(UCSR0A, UDRE0),
 154                         .vector = USART0_UDRE_vect,
 155                 },
 156         },
 157         .uart1 = {
 158                 .disabled = AVR_IO_REGBIT(PRR1,PRUSART1),
 159                 .name = '1',
 160                 .r_udr = UDR1,
 161
 162                 .txen = AVR_IO_REGBIT(UCSR1B, TXEN1),
 163                 .rxen = AVR_IO_REGBIT(UCSR1B, RXEN1),
 164                 .ucsz = AVR_IO_REGBITS(UCSR1C, UCSZ10, 0x3), // 2 bits
 165                 .ucsz2 = AVR_IO_REGBIT(UCSR1B, UCSZ12),         // 1 bits
 166
 167                 .r_ucsra = UCSR1A,
 168                 .r_ucsrb = UCSR1B,
 169                 .r_ucsrc = UCSR1C,
 170                 .r_ubrrl = UBRR1L,
 171                 .r_ubrrh = UBRR1H,
 172                 .rxc = {
 173                         .enable = AVR_IO_REGBIT(UCSR1B, RXCIE1),
 174                         .raised = AVR_IO_REGBIT(UCSR1A, RXC1),
 175                         .vector = USART1_RX_vect,
 176                 },
 177                 .txc = {
 178                         .enable = AVR_IO_REGBIT(UCSR1B, TXCIE1),
 179                         .raised = AVR_IO_REGBIT(UCSR1A, TXC1),
 180                         .vector = USART1_TX_vect,
 181                 },
 182                 .udrc = {
 183                         .enable = AVR_IO_REGBIT(UCSR1B, UDRIE1),
 184                         .raised = AVR_IO_REGBIT(UCSR1A, UDRE1),
 185                         .vector = USART1_UDRE_vect,
 186                 },
 187         },
 188
 189         .uart2 = {
 190                 .disabled = AVR_IO_REGBIT(PRR1,PRUSART2),
 191                 .name = '2',
 192                 .r_udr = UDR2,
 193
 194                 .txen = AVR_IO_REGBIT(UCSR2B, TXEN2),
 195                 .rxen = AVR_IO_REGBIT(UCSR2B, RXEN2),
 196                 .ucsz = AVR_IO_REGBITS(UCSR2C, UCSZ20, 0x3), // 2 bits
 197                 .ucsz2 = AVR_IO_REGBIT(UCSR2B, UCSZ22),         // 1 bits
 198
 199                 .r_ucsra = UCSR2A,
 200                 .r_ucsrb = UCSR2B,
 201                 .r_ucsrc = UCSR2C,
 202                 .r_ubrrl = UBRR2L,
 203                 .r_ubrrh = UBRR2H,
 204                 .rxc = {
 205                         .enable = AVR_IO_REGBIT(UCSR2B, RXCIE2),
 206                         .raised = AVR_IO_REGBIT(UCSR2A, RXC2),
 207                         .vector = USART2_RX_vect,
 208                 },
 209                 .txc = {
 210                         .enable = AVR_IO_REGBIT(UCSR2B, TXCIE2),
 211                         .raised = AVR_IO_REGBIT(UCSR2A, TXC2),
 212                         .vector = USART2_TX_vect,
 213                 },
 214                 .udrc = {
 215                         .enable = AVR_IO_REGBIT(UCSR2B, UDRIE2),
 216                         .raised = AVR_IO_REGBIT(UCSR2A, UDRE2),
 217                         .vector = USART2_UDRE_vect,
 218                 },
 219         },
 220
 221         .uart3 = {
 222                 .disabled = AVR_IO_REGBIT(PRR1,PRUSART3),
 223                 .name = '3',
 224                 .r_udr = UDR3,
 225
 226                 .txen = AVR_IO_REGBIT(UCSR3B, TXEN3),
 227                 .rxen = AVR_IO_REGBIT(UCSR3B, RXEN3),
 228                 .ucsz = AVR_IO_REGBITS(UCSR3C, UCSZ30, 0x3), // 2 bits
 229                 .ucsz2 = AVR_IO_REGBIT(UCSR3B, UCSZ32),         // 1 bits
 230
 231                 .r_ucsra = UCSR3A,
 232                 .r_ucsrb = UCSR3B,
 233                 .r_ucsrc = UCSR3C,
 234                 .r_ubrrl = UBRR3L,
 235                 .r_ubrrh = UBRR3H,
 236                 .rxc = {
 237                         .enable = AVR_IO_REGBIT(UCSR3B, RXCIE3),
 238                         .raised = AVR_IO_REGBIT(UCSR3A, RXC3),
 239                         .vector = USART3_RX_vect,
 240                 },
 241                 .txc = {
 242                         .enable = AVR_IO_REGBIT(UCSR3B, TXCIE3),
 243                         .raised = AVR_IO_REGBIT(UCSR3A, TXC3),
 244                         .vector = USART3_TX_vect,
 245                 },
 246                 .udrc = {
 247                         .enable = AVR_IO_REGBIT(UCSR3B, UDRIE3),
 248                         .raised = AVR_IO_REGBIT(UCSR3A, UDRE3),
 249                         .vector = USART3_UDRE_vect,
 250                 },
 251         },
 252         .adc = {
 253                 .r_admux = ADMUX,
 254                 .mux = { AVR_IO_REGBIT(ADMUX, MUX0), AVR_IO_REGBIT(ADMUX, MUX1),
 255                                         AVR_IO_REGBIT(ADMUX, MUX2), AVR_IO_REGBIT(ADMUX, MUX3),
 256                                         AVR_IO_REGBIT(ADMUX, MUX4),AVR_IO_REGBIT(ADCSRB, MUX5),},
 257                 .ref = { AVR_IO_REGBIT(ADMUX, REFS0), AVR_IO_REGBIT(ADMUX, REFS1)},
 258                 .ref_values = { [1] = ADC_VREF_AVCC, [2] = ADC_VREF_V110, [3] = ADC_VREF_V256 },
 259
 260                 .adlar = AVR_IO_REGBIT(ADMUX, ADLAR),
 261                 .r_adcsra = ADCSRA,
 262                 .aden = AVR_IO_REGBIT(ADCSRA, ADEN),
 263                 .adsc = AVR_IO_REGBIT(ADCSRA, ADSC),
 264                 .adate = AVR_IO_REGBIT(ADCSRA, ADATE),
 265                 .adps = { AVR_IO_REGBIT(ADCSRA, ADPS0), AVR_IO_REGBIT(ADCSRA, ADPS1), AVR_IO_REGBIT(ADCSRA, ADPS2),},
 266
 267                 .r_adch = ADCH,
 268                 .r_adcl = ADCL,
 269
 270                 .r_adcsrb = ADCSRB,
 271                 .adts = { AVR_IO_REGBIT(ADCSRB, ADTS0), AVR_IO_REGBIT(ADCSRB, ADTS1), AVR_IO_REGBIT(ADCSRB, ADTS2),},
 272
 273                 .muxmode = {
 274                         [0] = AVR_ADC_SINGLE(0), [1] = AVR_ADC_SINGLE(1),
 275                         [2] = AVR_ADC_SINGLE(2), [3] = AVR_ADC_SINGLE(3),
 276                         [4] = AVR_ADC_SINGLE(4), [5] = AVR_ADC_SINGLE(5),
 277                         [6] = AVR_ADC_SINGLE(6), [7] = AVR_ADC_SINGLE(7),
 278
 279                         [ 8] = AVR_ADC_DIFF(0, 0,  10), [ 9] = AVR_ADC_DIFF(1, 0,  10),
 280                         [10] = AVR_ADC_DIFF(0, 0, 200), [11] = AVR_ADC_DIFF(1, 0, 200),
 281                         [12] = AVR_ADC_DIFF(2, 2,  10), [13] = AVR_ADC_DIFF(3, 2,  10),
 282                         [14] = AVR_ADC_DIFF(2, 2, 200), [15] = AVR_ADC_DIFF(3, 2, 200),
 283
 284                         [16] = AVR_ADC_DIFF(0, 1,   1), [17] = AVR_ADC_DIFF(1, 1,   1),
 285                         [18] = AVR_ADC_DIFF(2, 1,   1), [19] = AVR_ADC_DIFF(3, 1,   1),
 286                         [20] = AVR_ADC_DIFF(4, 1,   1), [21] = AVR_ADC_DIFF(5, 1,   1),
 287                         [22] = AVR_ADC_DIFF(6, 1,   1), [23] = AVR_ADC_DIFF(7, 1,   1),
 288
 289                         [24] = AVR_ADC_DIFF(0, 2,   1), [25] = AVR_ADC_DIFF(1, 2,   1),
 290                         [26] = AVR_ADC_DIFF(2, 2,   1), [27] = AVR_ADC_DIFF(3, 2,   1),
 291                         [28] = AVR_ADC_DIFF(4, 2,   1), [29] = AVR_ADC_DIFF(5, 2,   1),
 292
 293                         [30] = AVR_ADC_REF(1100),       // 1.1V
 294                         [31] = AVR_ADC_REF(0),          // GND
 295
 296                         [32] = AVR_ADC_SINGLE( 8), [33] = AVR_ADC_SINGLE( 9),
 297                         [34] = AVR_ADC_SINGLE(10), [35] = AVR_ADC_SINGLE(11),
 298                         [36] = AVR_ADC_SINGLE(12), [37] = AVR_ADC_SINGLE(13),
 299                         [38] = AVR_ADC_SINGLE(14), [39] = AVR_ADC_SINGLE(15),
 300
 301                         [40] = AVR_ADC_DIFF( 8,  8,  10), [41] = AVR_ADC_DIFF( 9,  8,  10),
 302                         [42] = AVR_ADC_DIFF( 8,  8, 200), [43] = AVR_ADC_DIFF( 9,  8, 200),
 303
 304                         [44] = AVR_ADC_DIFF(10, 10,  10), [45] = AVR_ADC_DIFF(11, 10,  10),
 305                         [46] = AVR_ADC_DIFF(10, 10, 200), [47] = AVR_ADC_DIFF(11, 10, 200),
 306
 307                         [48] = AVR_ADC_DIFF( 8,  9,   1), [49] = AVR_ADC_DIFF( 9,  9,   1),
 308                         [50] = AVR_ADC_DIFF(10,  9,   1), [51] = AVR_ADC_DIFF(11,  9,   1),
 309                         [52] = AVR_ADC_DIFF(12,  9,   1), [53] = AVR_ADC_DIFF(13,  9,   1),
 310                         [54] = AVR_ADC_DIFF(14,  9,   1), [55] = AVR_ADC_DIFF(15,  9,   1),
 311
 312                         [56] = AVR_ADC_DIFF( 8, 10,   1), [57] = AVR_ADC_DIFF( 9, 10,   1),
 313                         [58] = AVR_ADC_DIFF(10, 10,   1), [59] = AVR_ADC_DIFF(11, 10,   1),
 314                         [60] = AVR_ADC_DIFF(12, 10,   1), [61] = AVR_ADC_DIFF(13, 10,   1),
 315                 },
 316
 317                 .adc = {
 318                         .enable = AVR_IO_REGBIT(ADCSRA, ADIE),
 319                         .raised = AVR_IO_REGBIT(ADCSRA, ADIF),
 320                         .vector = ADC_vect,
 321                 },
 322         },
 323         .timer0 = {
 324                 .name = '0',
 325                 .wgm = { AVR_IO_REGBIT(TCCR0A, WGM00), AVR_IO_REGBIT(TCCR0A, WGM01), AVR_IO_REGBIT(TCCR0B, WGM02) },
 326                 .wgm_op = {
 327                         [0] = AVR_TIMER_WGM_NORMAL8(),
 328                         [2] = AVR_TIMER_WGM_CTC(),
 329                         [3] = AVR_TIMER_WGM_FASTPWM8(),
 330                         [7] = AVR_TIMER_WGM_OCPWM(),
 331                 },
 332                 .cs = { AVR_IO_REGBIT(TCCR0B, CS00), AVR_IO_REGBIT(TCCR0B, CS01), AVR_IO_REGBIT(TCCR0B, CS02) },
 333                 .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ },
 334
 335                 .r_tcnt = TCNT0,
 336
 337                 .overflow = {
 338                         .enable = AVR_IO_REGBIT(TIMSK0, TOIE0),
 339                         .raised = AVR_IO_REGBIT(TIFR0, TOV0),
 340                         .vector = TIMER0_OVF_vect,
 341                 },
 342                 .comp = {
 343                         [AVR_TIMER_COMPA] = {
 344                                 .r_ocr = OCR0A,
 345                                 .com = AVR_IO_REGBITS(TCCR0A, COM0A0, 0x3),
 346                                 .com_pin = AVR_IO_REGBIT(PORTB, PB7), // same as timer1C
 347                                 .interrupt = {
 348                                         .enable = AVR_IO_REGBIT(TIMSK0, OCIE0A),
 349                                         .raised = AVR_IO_REGBIT(TIFR0, OCF0A),
 350                                         .vector = TIMER0_COMPA_vect,
 351                                 },
 352                         },
 353                         [AVR_TIMER_COMPB] = {
 354                                 .r_ocr = OCR0B,
 355                                 .com = AVR_IO_REGBITS(TCCR0A, COM0B0, 0x3),
 356                                 .com_pin = AVR_IO_REGBIT(PORTG, PG5),
 357                                 .interrupt = {
 358                                         .enable = AVR_IO_REGBIT(TIMSK0, OCIE0B),
 359                                         .raised = AVR_IO_REGBIT(TIFR0, OCF0B),
 360                                         .vector = TIMER0_COMPB_vect,
 361                                 },
 362                         },
 363                 },
 364         },
 365         .timer1 = {
 366                 .name = '1',
 367                 .disabled = AVR_IO_REGBIT(PRR0,PRTIM1),
 368                 .wgm = { AVR_IO_REGBIT(TCCR1A, WGM10), AVR_IO_REGBIT(TCCR1A, WGM11),
 369                                         AVR_IO_REGBIT(TCCR1B, WGM12), AVR_IO_REGBIT(TCCR1B, WGM13) },
 370                 .wgm_op = {
 371                         [0] = AVR_TIMER_WGM_NORMAL16(),
 372                         // TODO: 1 PWM phase correct 8bit
 373                         //               2 PWM phase correct 9bit
 374                         //       3 PWM phase correct 10bit
 375                         [4] = AVR_TIMER_WGM_CTC(),
 376                         [5] = AVR_TIMER_WGM_FASTPWM8(),
 377                         [6] = AVR_TIMER_WGM_FASTPWM9(),
 378                         [7] = AVR_TIMER_WGM_FASTPWM10(),
 379                         // TODO: 8, 9 PWM phase and freq correct ICR & 10, 11
 380                         [12] = AVR_TIMER_WGM_ICCTC(),
 381                         [14] = AVR_TIMER_WGM_ICPWM(),
 382                         [15] = AVR_TIMER_WGM_OCPWM(),
 383                 },
 384                 .cs = { AVR_IO_REGBIT(TCCR1B, CS10), AVR_IO_REGBIT(TCCR1B, CS11), AVR_IO_REGBIT(TCCR1B, CS12) },
 385                 .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */  /* External clock T1 is not handled */},
 386
 387                 .r_tcnt = TCNT1L,
 388                 .r_tcnth = TCNT1H,
 389                 .r_icr = ICR1L,
 390                 .r_icrh = ICR1H,
 391
 392                 .ices = AVR_IO_REGBIT(TCCR1B, ICES1),
 393                 .icp = AVR_IO_REGBIT(PORTD, PD4),
 394
 395                 .overflow = {
 396                         .enable = AVR_IO_REGBIT(TIMSK1, TOIE1),
 397                         .raised = AVR_IO_REGBIT(TIFR1, TOV1),
 398                         .vector = TIMER1_OVF_vect,
 399                 },
 400                 .icr = {
 401                         .enable = AVR_IO_REGBIT(TIMSK1, ICIE1),
 402                         .raised = AVR_IO_REGBIT(TIFR1, ICF1),
 403                         .vector = TIMER1_CAPT_vect,
 404                 },
 405                 .comp = {
 406                         [AVR_TIMER_COMPA] = {
 407                                 .r_ocr = OCR1AL,
 408                                 .r_ocrh = OCR1AH,       // 16 bits timers have two bytes of it
 409                                 .com = AVR_IO_REGBITS(TCCR1A, COM1A0, 0x3),
 410                                 .com_pin = AVR_IO_REGBIT(PORTB, PB5),
 411                                 .interrupt = {
 412                                         .enable = AVR_IO_REGBIT(TIMSK1, OCIE1A),
 413                                         .raised = AVR_IO_REGBIT(TIFR1, OCF1A),
 414                                         .vector = TIMER1_COMPA_vect,
 415                                 },
 416                         },
 417                         [AVR_TIMER_COMPB] = {
 418                                 .r_ocr = OCR1BL,
 419                                 .r_ocrh = OCR1BH,
 420                                 .com = AVR_IO_REGBITS(TCCR1A, COM1B0, 0x3),
 421                                 .com_pin = AVR_IO_REGBIT(PORTB, PB6),
 422                                 .interrupt = {
 423                                         .enable = AVR_IO_REGBIT(TIMSK1, OCIE1B),
 424                                         .raised = AVR_IO_REGBIT(TIFR1, OCF1B),
 425                                         .vector = TIMER1_COMPB_vect,
 426                                 },
 427                         },
 428                         [AVR_TIMER_COMPC] = {
 429                                 .r_ocr = OCR1CL,
 430                                 .r_ocrh = OCR1CH,
 431                                 .com = AVR_IO_REGBITS(TCCR1A, COM1C0, 0x3),
 432                                 .com_pin = AVR_IO_REGBIT(PORTB, PB7), // same as timer0A
 433                                 .interrupt = {
 434                                         .enable = AVR_IO_REGBIT(TIMSK1, OCIE1C),
 435                                         .raised = AVR_IO_REGBIT(TIFR1, OCF1C),
 436                                         .vector = TIMER1_COMPC_vect,
 437                                 },
 438                         },
 439                 },
 440
 441         },
 442         .timer2 = {
 443                 .name = '2',
 444                 .wgm = { AVR_IO_REGBIT(TCCR2A, WGM20), AVR_IO_REGBIT(TCCR2A, WGM21), AVR_IO_REGBIT(TCCR2B, WGM22) },
 445                 .wgm_op = {
 446                         [0] = AVR_TIMER_WGM_NORMAL8(),
 447                         // TODO 1 pwm phase correct
 448                         [2] = AVR_TIMER_WGM_CTC(),
 449                         [3] = AVR_TIMER_WGM_FASTPWM8(),
 450                         [7] = AVR_TIMER_WGM_OCPWM(),
 451                 },
 452                 .cs = { AVR_IO_REGBIT(TCCR2B, CS20), AVR_IO_REGBIT(TCCR2B, CS21), AVR_IO_REGBIT(TCCR2B, CS22) },
 453                 .cs_div = { 0, 0, 3 /* 8 */, 5 /* 32 */, 6 /* 64 */, 7 /* 128 */, 8 /* 256 */, 10 /* 1024 */ },
 454
 455                 .r_tcnt = TCNT2,
 456                 // asynchronous timer source bit.. if set, use 32khz frequency
 457                 .as2 = AVR_IO_REGBIT(ASSR, AS2),
 458
 459                 .overflow = {
 460                         .enable = AVR_IO_REGBIT(TIMSK2, TOIE2),
 461                         .raised = AVR_IO_REGBIT(TIFR2, TOV2),
 462                         .vector = TIMER2_OVF_vect,
 463                 },
 464                 .comp = {
 465                         [AVR_TIMER_COMPA] = {
 466                                 .r_ocr = OCR2A,
 467                                 .com = AVR_IO_REGBITS(TCCR2A, COM2A0, 0x3),
 468                                 .com_pin = AVR_IO_REGBIT(PORTB, PB4),
 469                                 .interrupt = {
 470                                         .enable = AVR_IO_REGBIT(TIMSK2, OCIE2A),
 471                                         .raised = AVR_IO_REGBIT(TIFR2, OCF2A),
 472                                         .vector = TIMER2_COMPA_vect,
 473                                 },
 474                         },
 475             // TIMER2_COMPB is only appeared in 1280
 476                         //[AVR_TIMER_COMPB] = {
 477                         //      .r_ocr = OCR2B,
 478                         //      .com = AVR_IO_REGBITS(TCCR2A, COM2B0, 0x3),
 479                         //      .com_pin = AVR_IO_REGBIT(PORTH, PH6),
 480                         //      .interrupt = {
 481                         //              .enable = AVR_IO_REGBIT(TIMSK2, OCIE2B),
 482                         //              .raised = AVR_IO_REGBIT(TIFR2, OCF2B),
 483                         //              .vector = TIMER2_COMPB_vect,
 484                         //      },
 485                         //},
 486                 },
 487         },
 488         .timer3 = {
 489                 .name = '3',
 490                 .wgm = { AVR_IO_REGBIT(TCCR3A, WGM30), AVR_IO_REGBIT(TCCR3A, WGM31),
 491                                         AVR_IO_REGBIT(TCCR3B, WGM32), AVR_IO_REGBIT(TCCR3B, WGM33) },
 492                 .wgm_op = {
 493                         [0] = AVR_TIMER_WGM_NORMAL16(),
 494                         // TODO: 1 PWM phase correct 8bit
 495                         //       2 PWM phase correct 9bit
 496                         //       3 PWM phase correct 10bit
 497                         [4] = AVR_TIMER_WGM_CTC(),
 498                         [5] = AVR_TIMER_WGM_FASTPWM8(),
 499                         [6] = AVR_TIMER_WGM_FASTPWM9(),
 500                         [7] = AVR_TIMER_WGM_FASTPWM10(),
 501                         // TODO: 8 PWM phase and freq correct ICR
 502                         //       9 PWM phase and freq correct OCR
 503                         //       10
 504                         //       11
 505                         [12] = AVR_TIMER_WGM_ICCTC(),
 506                         [14] = AVR_TIMER_WGM_ICPWM(),
 507                         [15] = AVR_TIMER_WGM_OCPWM(),
 508                 },
 509                 .cs = { AVR_IO_REGBIT(TCCR3B, CS30), AVR_IO_REGBIT(TCCR3B, CS31), AVR_IO_REGBIT(TCCR3B, CS32) },
 510                 .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */  /* TODO: 2 External clocks */},
 511
 512                 .r_tcnt = TCNT3L,
 513                 .r_icr = ICR3L,
 514                 .r_icrh = ICR3H,
 515                 .r_tcnth = TCNT3H,
 516
 517                 .ices = AVR_IO_REGBIT(TCCR3B, ICES3),
 518                 .icp = AVR_IO_REGBIT(PORTE, PE7),
 519
 520                 .overflow = {
 521                         .enable = AVR_IO_REGBIT(TIMSK3, TOIE3),
 522                         .raised = AVR_IO_REGBIT(TIFR3, TOV3),
 523                         .vector = TIMER3_OVF_vect,
 524                 },
 525                 .comp = {
 526                         [AVR_TIMER_COMPA] = {
 527                                 .r_ocr = OCR3AL,
 528                                 .r_ocrh = OCR3AH,       // 16 bits timers have two bytes of it
 529                                 .com = AVR_IO_REGBITS(TCCR3A, COM3A0, 0x3),
 530                                 .com_pin = AVR_IO_REGBIT(PORTE, PE3),
 531                                 .interrupt = {
 532                                         .enable = AVR_IO_REGBIT(TIMSK3, OCIE3A),
 533                                         .raised = AVR_IO_REGBIT(TIFR3, OCF3A),
 534                                         .vector = TIMER3_COMPA_vect,
 535                                 }
 536                         },
 537                         [AVR_TIMER_COMPB] = {
 538                                 .r_ocr = OCR3BL,
 539                                 .r_ocrh = OCR3BH,
 540                                 .com = AVR_IO_REGBITS(TCCR3A, COM3B0, 0x3),
 541                                 .com_pin = AVR_IO_REGBIT(PORTE, PE4),
 542                                 .interrupt = {
 543                                         .enable = AVR_IO_REGBIT(TIMSK3, OCIE3B),
 544                                         .raised = AVR_IO_REGBIT(TIFR3, OCF3B),
 545                                         .vector = TIMER3_COMPB_vect,
 546                                 }
 547                         },
 548                         [AVR_TIMER_COMPC] = {
 549                                 .r_ocr = OCR3CL,
 550                                 .r_ocrh = OCR3CH,
 551                                 .com = AVR_IO_REGBITS(TCCR3A, COM3C0, 0x3),
 552                                 .com_pin = AVR_IO_REGBIT(PORTE, PE5),
 553                                 .interrupt = {
 554                                         .enable = AVR_IO_REGBIT(TIMSK3, OCIE3C),
 555                                         .raised = AVR_IO_REGBIT(TIFR3, OCF3C),
 556                                         .vector = TIMER3_COMPC_vect,
 557                                 }
 558                         }
 559                 },
 560                 .icr = {
 561                         .enable = AVR_IO_REGBIT(TIMSK3, ICIE3),
 562                         .raised = AVR_IO_REGBIT(TIFR3, ICF3),
 563                         .vector = TIMER3_CAPT_vect,
 564                 },
 565         },
 566         .timer4 = {
 567                 .name = '4',
 568                 .disabled = AVR_IO_REGBIT(PRR1,PRTIM4),
 569                 .wgm = { AVR_IO_REGBIT(TCCR4A, WGM40), AVR_IO_REGBIT(TCCR4A, WGM41),
 570                                         AVR_IO_REGBIT(TCCR4B, WGM42), AVR_IO_REGBIT(TCCR4B, WGM43) },
 571                 .wgm_op = {
 572                         [0] = AVR_TIMER_WGM_NORMAL16(),
 573                         // TODO: 1 PWM phase correct 8bit
 574                         //               2 PWM phase correct 9bit
 575                         //       3 PWM phase correct 10bit
 576                         [4] = AVR_TIMER_WGM_CTC(),
 577                         [5] = AVR_TIMER_WGM_FASTPWM8(),
 578                         [6] = AVR_TIMER_WGM_FASTPWM9(),
 579                         [7] = AVR_TIMER_WGM_FASTPWM10(),
 580                         // TODO: 8, 9 PWM phase and freq correct ICR & 10, 11
 581                         [12] = AVR_TIMER_WGM_ICCTC(),
 582                         [14] = AVR_TIMER_WGM_ICPWM(),
 583                         [15] = AVR_TIMER_WGM_OCPWM(),
 584                 },
 585                 .cs = { AVR_IO_REGBIT(TCCR4B, CS40), AVR_IO_REGBIT(TCCR4B, CS41), AVR_IO_REGBIT(TCCR4B, CS42) },
 586                 .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */  /* External clock T1 is not handled */},
 587
 588                 .r_tcnt = TCNT4L,
 589                 .r_tcnth = TCNT4H,
 590                 .r_icr = ICR4L,
 591                 .r_icrh = ICR4H,
 592
 593                 .ices = AVR_IO_REGBIT(TCCR4B, ICES4),
 594                 .icp = AVR_IO_REGBIT(PORTL, PL0),
 595
 596                 .overflow = {
 597                         .enable = AVR_IO_REGBIT(TIMSK4, TOIE4),
 598                         .raised = AVR_IO_REGBIT(TIFR4, TOV4),
 599                         .vector = TIMER4_OVF_vect,
 600                 },
 601                 .icr = {
 602                         .enable = AVR_IO_REGBIT(TIMSK4, ICIE4),
 603                         .raised = AVR_IO_REGBIT(TIFR4, ICF4),
 604                         .vector = TIMER4_CAPT_vect,
 605                 },
 606                 .comp = {
 607                         [AVR_TIMER_COMPA] = {
 608                                 .r_ocr = OCR4AL,
 609                                 .r_ocrh = OCR4AH,       // 16 bits timers have two bytes of it
 610                                 .com = AVR_IO_REGBITS(TCCR4A, COM4A0, 0x3),
 611                                 .com_pin = AVR_IO_REGBIT(PORTH, PH3),
 612                                 .interrupt = {
 613                                         .enable = AVR_IO_REGBIT(TIMSK4, OCIE4A),
 614                                         .raised = AVR_IO_REGBIT(TIFR4, OCF4A),
 615                                         .vector = TIMER4_COMPA_vect,
 616                                 },
 617                         },
 618                         [AVR_TIMER_COMPB] = {
 619                                 .r_ocr = OCR4BL,
 620                                 .r_ocrh = OCR4BH,
 621                                 .com = AVR_IO_REGBITS(TCCR4A, COM4B0, 0x3),
 622                                 .com_pin = AVR_IO_REGBIT(PORTH, PH4),
 623                                 .interrupt = {
 624                                         .enable = AVR_IO_REGBIT(TIMSK4, OCIE4B),
 625                                         .raised = AVR_IO_REGBIT(TIFR4, OCF4B),
 626                                         .vector = TIMER4_COMPB_vect,
 627                                 },
 628                         },
 629                         [AVR_TIMER_COMPC] = {
 630                                 .r_ocr = OCR4CL,
 631                                 .r_ocrh = OCR4CH,
 632                                 .com = AVR_IO_REGBITS(TCCR4A, COM4C0, 0x3),
 633                                 .com_pin = AVR_IO_REGBIT(PORTH, PH5),
 634                                 .interrupt = {
 635                                         .enable = AVR_IO_REGBIT(TIMSK4, OCIE4C),
 636                                         .raised = AVR_IO_REGBIT(TIFR4, OCF4C),
 637                                         .vector = TIMER4_COMPC_vect,
 638                                 },
 639                         },
 640                 },
 641
 642         },
 643         .timer5 = {
 644                 .name = '5',
 645                 .disabled = AVR_IO_REGBIT(PRR1,PRTIM5),
 646                 .wgm = { AVR_IO_REGBIT(TCCR5A, WGM50), AVR_IO_REGBIT(TCCR5A, WGM51),
 647                                         AVR_IO_REGBIT(TCCR5B, WGM52), AVR_IO_REGBIT(TCCR5B, WGM53) },
 648                 .wgm_op = {
 649                         [0] = AVR_TIMER_WGM_NORMAL16(),
 650                         // TODO: 1 PWM phase correct 8bit
 651                         //               2 PWM phase correct 9bit
 652                         //       3 PWM phase correct 10bit
 653                         [4] = AVR_TIMER_WGM_CTC(),
 654                         [5] = AVR_TIMER_WGM_FASTPWM8(),
 655                         [6] = AVR_TIMER_WGM_FASTPWM9(),
 656                         [7] = AVR_TIMER_WGM_FASTPWM10(),
 657                         // TODO: 8, 9 PWM phase and freq correct ICR & 10, 11
 658                         [12] = AVR_TIMER_WGM_ICCTC(),
 659                         [14] = AVR_TIMER_WGM_ICPWM(),
 660                         [15] = AVR_TIMER_WGM_OCPWM(),
 661                 },
 662                 .cs = { AVR_IO_REGBIT(TCCR5B, CS50), AVR_IO_REGBIT(TCCR5B, CS51), AVR_IO_REGBIT(TCCR5B, CS52) },
 663                 .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */  /* External clock T1 is not handled */},
 664
 665                 .r_tcnt = TCNT5L,
 666                 .r_tcnth = TCNT5H,
 667                 .r_icr = ICR5L,
 668                 .r_icrh = ICR5H,
 669
 670                 .ices = AVR_IO_REGBIT(TCCR5B, ICES5),
 671                 .icp = AVR_IO_REGBIT(PORTL, PL1),
 672
 673                 .overflow = {
 674                         .enable = AVR_IO_REGBIT(TIMSK5, TOIE5),
 675                         .raised = AVR_IO_REGBIT(TIFR5, TOV5),
 676                         .vector = TIMER5_OVF_vect,
 677                 },
 678                 .icr = {
 679                         .enable = AVR_IO_REGBIT(TIMSK5, ICIE5),
 680                         .raised = AVR_IO_REGBIT(TIFR5, ICF5),
 681                         .vector = TIMER5_CAPT_vect,
 682                 },
 683                 .comp = {
 684                         [AVR_TIMER_COMPA] = {
 685                                 .r_ocr = OCR5AL,
 686                                 .r_ocrh = OCR5AH,       // 16 bits timers have two bytes of it
 687                                 .com = AVR_IO_REGBITS(TCCR5A, COM5A0, 0x3),
 688                                 .com_pin = AVR_IO_REGBIT(PORTL, PL3),
 689                                 .interrupt = {
 690                                         .enable = AVR_IO_REGBIT(TIMSK5, OCIE5A),
 691                                         .raised = AVR_IO_REGBIT(TIFR5, OCF5A),
 692                                         .vector = TIMER5_COMPA_vect,
 693                                 },
 694                         },
 695                         [AVR_TIMER_COMPB] = {
 696                                 .r_ocr = OCR5BL,
 697                                 .r_ocrh = OCR5BH,
 698                                 .com = AVR_IO_REGBITS(TCCR5A, COM5B0, 0x3),
 699                                 .com_pin = AVR_IO_REGBIT(PORTL, PL4),
 700                                 .interrupt = {
 701                                         .enable = AVR_IO_REGBIT(TIMSK5, OCIE5B),
 702                                         .raised = AVR_IO_REGBIT(TIFR5, OCF5B),
 703                                         .vector = TIMER5_COMPB_vect,
 704                                 },
 705                         },
 706                         [AVR_TIMER_COMPC] = {
 707                                 .r_ocr = OCR5CL,
 708                                 .r_ocrh = OCR5CH,
 709                                 .com = AVR_IO_REGBITS(TCCR5A, COM5C0, 0x3),
 710                                 .com_pin = AVR_IO_REGBIT(PORTL, PL5),
 711                                 .interrupt = {
 712                                         .enable = AVR_IO_REGBIT(TIMSK5, OCIE5C),
 713                                         .raised = AVR_IO_REGBIT(TIFR5, OCF5C),
 714                                         .vector = TIMER5_COMPC_vect,
 715                                 },
 716                         },
 717                 },
 718
 719         },
 720         .spi = {
 721                 .disabled = AVR_IO_REGBIT(PRR0,PRSPI),
 722
 723                 .r_spdr = SPDR,
 724                 .r_spcr = SPCR,
 725                 .r_spsr = SPSR,
 726
 727                 .spe = AVR_IO_REGBIT(SPCR, SPE),
 728                 .mstr = AVR_IO_REGBIT(SPCR, MSTR),
 729
 730                 .spr = { AVR_IO_REGBIT(SPCR, SPR0), AVR_IO_REGBIT(SPCR, SPR1), AVR_IO_REGBIT(SPSR, SPI2X) },
 731                 .spi = {
 732                         .enable = AVR_IO_REGBIT(SPCR, SPIE),
 733                         .raised = AVR_IO_REGBIT(SPSR, SPIF),
 734                         .vector = SPI_STC_vect,
 735                 },
 736         },
 737
 738         .twi = {
 739
 740                 .r_twcr = TWCR,
 741                 .r_twsr = TWSR,
 742                 .r_twbr = TWBR,
 743                 .r_twdr = TWDR,
 744                 .r_twar = TWAR,
 745                 .r_twamr = TWAMR,
 746
 747                 .twen = AVR_IO_REGBIT(TWCR, TWEN),
 748                 .twea = AVR_IO_REGBIT(TWCR, TWEA),
 749                 .twsta = AVR_IO_REGBIT(TWCR, TWSTA),
 750                 .twsto = AVR_IO_REGBIT(TWCR, TWSTO),
 751                 .twwc = AVR_IO_REGBIT(TWCR, TWWC),
 752
 753                 .twsr = AVR_IO_REGBITS(TWSR, TWS3, 0x1f),       // 5 bits
 754                 .twps = AVR_IO_REGBITS(TWSR, TWPS0, 0x3),       // 2 bits
 755
 756                 .twi = {
 757                         .enable = AVR_IO_REGBIT(TWCR, TWIE),
 758                         .raised = AVR_IO_REGBIT(TWCR, TWINT),
 759                         .raise_sticky = 1,
 760                         .vector = TWI_vect,
 761                 },
 762         },
 763
 764 };
 765
 766 static avr_t * make()
 767 {
 768         return avr_core_allocate(&mcu_mega1280.core, sizeof(struct mcu_t));
 769 }
 770
 771 avr_kind_t mega1280 = {
 772         .names = { "atmega1280" },
 773         .make = make
 774 };
 775
 776 void m1280_init(struct avr_t * avr)
 777 {
 778         struct mcu_t * mcu = (struct mcu_t*)avr;
 779
 780         //printf("%s init\n", avr->mmcu);
 781
 782         avr_eeprom_init(avr, &mcu->eeprom);
 783         avr_flash_init(avr, &mcu->selfprog);
 784         avr_extint_init(avr, &mcu->extint);
 785         avr_watchdog_init(avr, &mcu->watchdog);
 786         avr_ioport_init(avr, &mcu->porta);
 787         avr_ioport_init(avr, &mcu->portb);
 788         avr_ioport_init(avr, &mcu->portc);
 789         avr_ioport_init(avr, &mcu->portd);
 790         avr_ioport_init(avr, &mcu->porte);
 791         avr_ioport_init(avr, &mcu->portf);
 792         avr_ioport_init(avr, &mcu->portg);
 793         avr_ioport_init(avr, &mcu->porth);
 794         avr_ioport_init(avr, &mcu->portj);
 795         avr_ioport_init(avr, &mcu->portk);
 796         avr_ioport_init(avr, &mcu->portl);
 797
 798         avr_uart_init(avr, &mcu->uart0);
 799         avr_uart_init(avr, &mcu->uart1);
 800         avr_uart_init(avr, &mcu->uart2);
 801         avr_uart_init(avr, &mcu->uart3);
 802         avr_adc_init(avr, &mcu->adc);
 803         avr_timer_init(avr, &mcu->timer0);
 804         avr_timer_init(avr, &mcu->timer1);
 805         avr_timer_init(avr, &mcu->timer2);
 806         avr_timer_init(avr, &mcu->timer3);
 807         avr_timer_init(avr, &mcu->timer4);
 808         avr_timer_init(avr, &mcu->timer5);
 809         avr_spi_init(avr, &mcu->spi);
 810         avr_twi_init(avr, &mcu->twi);
 811 }
 812
 813 void m1280_reset(struct avr_t * avr)
 814 {
 815 //      struct mcu_t * mcu = (struct mcu_t*)avr;
 816 }