git.rot13.org Git - simavr/blob - simavr/cores/sim_mega1280.c

   1 /*
   2         sim_mega1280.c
   3
   4         Copyright 2008, 2009 Michel Pollet <buserror@gmail.com>
   5
   6         This file is part of simavr.
   7
   8         simavr is free software: you can redistribute it and/or modify
   9         it under the terms of the GNU General Public License as published by
  10         the Free Software Foundation, either version 3 of the License, or
  11         (at your option) any later version.
  12
  13         simavr is distributed in the hope that it will be useful,
  14         but WITHOUT ANY WARRANTY; without even the implied warranty of
  15         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16         GNU General Public License for more details.
  17
  18         You should have received a copy of the GNU General Public License
  19         along with simavr.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include "sim_avr.h"
  23 #include "sim_core_declare.h"
  24 #include "avr_eeprom.h"
  25 #include "avr_flash.h"
  26 #include "avr_watchdog.h"
  27 #include "avr_extint.h"
  28 #include "avr_ioport.h"
  29 #include "avr_uart.h"
  30 #include "avr_adc.h"
  31 #include "avr_timer.h"
  32 #include "avr_spi.h"
  33 #include "avr_twi.h"
  34
  35 void m1280_init(struct avr_t * avr);
  36 void m1280_reset(struct avr_t * avr);
  37
  38 #define _AVR_IO_H_
  39 #define __ASSEMBLER__
  40 #ifndef __AVR_ATmega1280__
  41 #define __AVR_ATmega1280__
  42 #endif
  43 #include "avr/iom1280.h"
  44
  45 /*
  46  * This is a template for all of the 1280 devices, hopefully
  47  */
  48 const struct mcu_t {
  49         avr_t          core;
  50         avr_eeprom_t    eeprom;
  51         avr_flash_t     selfprog;
  52         avr_watchdog_t  watchdog;
  53         avr_extint_t    extint;
  54         avr_ioport_t    porta, portb, portc, portd, porte, portf, portg, porth, portj, portk, portl;
  55         avr_uart_t              uart0,uart1;
  56         avr_uart_t              uart2,uart3;
  57         avr_adc_t               adc;
  58         avr_timer_t             timer0,timer1,timer2,timer3,timer4,timer5;
  59         avr_spi_t               spi;
  60         avr_twi_t               twi;
  61  }mcu_mega1280 = {
  62         .core = {
  63                 .mmcu = "atmega1280",
  64                 DEFAULT_CORE(4),
  65
  66                 .init = m1280_init,
  67                 .reset = m1280_reset,
  68
  69                 .rampz = RAMPZ, // extended program memory access
  70         },
  71         AVR_EEPROM_DECLARE(EE_READY_vect),
  72         AVR_SELFPROG_DECLARE(SPMCSR, SPMEN, SPM_READY_vect),
  73         AVR_WATCHDOG_DECLARE(WDTCSR, WDT_vect),
  74         .extint = {
  75                 AVR_EXTINT_MEGA_DECLARE(0, 'D', PD0, A),
  76                 AVR_EXTINT_MEGA_DECLARE(1, 'D', PD1, A),
  77                 AVR_EXTINT_MEGA_DECLARE(2, 'D', PD2, A),
  78                 AVR_EXTINT_MEGA_DECLARE(3, 'D', PD3, A),
  79                 AVR_EXTINT_MEGA_DECLARE(4, 'E', PE4, B),
  80                 AVR_EXTINT_MEGA_DECLARE(5, 'E', PE5, B),
  81                 AVR_EXTINT_MEGA_DECLARE(6, 'E', PE6, B),
  82                 AVR_EXTINT_MEGA_DECLARE(7, 'E', PE7, B),
  83         },
  84         .porta = {
  85                 .name = 'A', .r_port = PORTA, .r_ddr = DDRA, .r_pin = PINA,
  86         },
  87         .portb = {
  88                 .name = 'B', .r_port = PORTB, .r_ddr = DDRB, .r_pin = PINB,
  89                 .pcint = {
  90                         .enable = AVR_IO_REGBIT(PCICR, PCIE0),
  91                         .raised = AVR_IO_REGBIT(PCIFR, PCIF0),
  92                         .vector = PCINT0_vect,
  93                 },
  94                 .r_pcint = PCMSK0,
  95         },
  96         .portc = {
  97                 .name = 'C', .r_port = PORTC, .r_ddr = DDRC, .r_pin = PINC,
  98         },
  99         .portd = {
 100                 .name = 'D', .r_port = PORTD, .r_ddr = DDRD, .r_pin = PIND,
 101         },
 102         .porte = {
 103                 .name = 'E', .r_port = PORTE, .r_ddr = DDRE, .r_pin = PINE,
 104         },
 105         .portf = {
 106                 .name = 'F', .r_port = PORTF, .r_ddr = DDRF, .r_pin = PINF,
 107         },
 108         .portg = {
 109                 .name = 'G', .r_port = PORTG, .r_ddr = DDRG, .r_pin = PING,
 110         },
 111
 112         .porth = {
 113                 .name = 'H', .r_port = PORTH, .r_ddr = DDRH, .r_pin = PINH,
 114         },
 115         .portj = {
 116                 .name = 'J', .r_port = PORTJ, .r_ddr = DDRJ, .r_pin = PINJ,
 117         },
 118         .portk = {
 119                 .name = 'K', .r_port = PORTK, .r_ddr = DDRK, .r_pin = PINK,
 120         },
 121         .portl = {
 122                 .name = 'L', .r_port = PORTL, .r_ddr = DDRL, .r_pin = PINL,
 123         },
 124
 125         .uart0 = {
 126                 .disabled = AVR_IO_REGBIT(PRR0,PRUSART0),
 127                 .name = '0',
 128                 .r_udr = UDR0,
 129
 130                 .txen = AVR_IO_REGBIT(UCSR0B, TXEN0),
 131                 .rxen = AVR_IO_REGBIT(UCSR0B, RXEN0),
 132                 .ucsz = AVR_IO_REGBITS(UCSR0C, UCSZ00, 0x3), // 2 bits
 133                 .ucsz2 = AVR_IO_REGBIT(UCSR0B, UCSZ02),         // 1 bits
 134
 135                 .r_ucsra = UCSR0A,
 136                 .r_ucsrb = UCSR0B,
 137                 .r_ucsrc = UCSR0C,
 138                 .r_ubrrl = UBRR0L,
 139                 .r_ubrrh = UBRR0H,
 140                 .rxc = {
 141                         .enable = AVR_IO_REGBIT(UCSR0B, RXCIE0),
 142                         .raised = AVR_IO_REGBIT(UCSR0A, RXC0),
 143                         .vector = USART0_RX_vect,
 144                 },
 145                 .txc = {
 146                         .enable = AVR_IO_REGBIT(UCSR0B, TXCIE0),
 147                         .raised = AVR_IO_REGBIT(UCSR0A, TXC0),
 148                         .vector = USART0_TX_vect,
 149                 },
 150                 .udrc = {
 151                         .enable = AVR_IO_REGBIT(UCSR0B, UDRIE0),
 152                         .raised = AVR_IO_REGBIT(UCSR0A, UDRE0),
 153                         .vector = USART0_UDRE_vect,
 154                 },
 155         },
 156         .uart1 = {
 157                 .disabled = AVR_IO_REGBIT(PRR1,PRUSART1),
 158                 .name = '1',
 159                 .r_udr = UDR1,
 160
 161                 .txen = AVR_IO_REGBIT(UCSR1B, TXEN1),
 162                 .rxen = AVR_IO_REGBIT(UCSR1B, RXEN1),
 163                 .ucsz = AVR_IO_REGBITS(UCSR1C, UCSZ10, 0x3), // 2 bits
 164                 .ucsz2 = AVR_IO_REGBIT(UCSR1B, UCSZ12),         // 1 bits
 165
 166                 .r_ucsra = UCSR1A,
 167                 .r_ucsrb = UCSR1B,
 168                 .r_ucsrc = UCSR1C,
 169                 .r_ubrrl = UBRR1L,
 170                 .r_ubrrh = UBRR1H,
 171                 .rxc = {
 172                         .enable = AVR_IO_REGBIT(UCSR1B, RXCIE1),
 173                         .raised = AVR_IO_REGBIT(UCSR1A, RXC1),
 174                         .vector = USART1_RX_vect,
 175                 },
 176                 .txc = {
 177                         .enable = AVR_IO_REGBIT(UCSR1B, TXCIE1),
 178                         .raised = AVR_IO_REGBIT(UCSR1A, TXC1),
 179                         .vector = USART1_TX_vect,
 180                 },
 181                 .udrc = {
 182                         .enable = AVR_IO_REGBIT(UCSR1B, UDRIE1),
 183                         .raised = AVR_IO_REGBIT(UCSR1A, UDRE1),
 184                         .vector = USART1_UDRE_vect,
 185                 },
 186         },
 187
 188         .uart2 = {
 189                 .disabled = AVR_IO_REGBIT(PRR1,PRUSART2),
 190                 .name = '2',
 191                 .r_udr = UDR2,
 192
 193                 .txen = AVR_IO_REGBIT(UCSR2B, TXEN2),
 194                 .rxen = AVR_IO_REGBIT(UCSR2B, RXEN2),
 195                 .ucsz = AVR_IO_REGBITS(UCSR2C, UCSZ20, 0x3), // 2 bits
 196                 .ucsz2 = AVR_IO_REGBIT(UCSR2B, UCSZ22),         // 1 bits
 197
 198                 .r_ucsra = UCSR2A,
 199                 .r_ucsrb = UCSR2B,
 200                 .r_ucsrc = UCSR2C,
 201                 .r_ubrrl = UBRR2L,
 202                 .r_ubrrh = UBRR2H,
 203                 .rxc = {
 204                         .enable = AVR_IO_REGBIT(UCSR2B, RXCIE2),
 205                         .raised = AVR_IO_REGBIT(UCSR2A, RXC2),
 206                         .vector = USART2_RX_vect,
 207                 },
 208                 .txc = {
 209                         .enable = AVR_IO_REGBIT(UCSR2B, TXCIE2),
 210                         .raised = AVR_IO_REGBIT(UCSR2A, TXC2),
 211                         .vector = USART2_TX_vect,
 212                 },
 213                 .udrc = {
 214                         .enable = AVR_IO_REGBIT(UCSR2B, UDRIE2),
 215                         .raised = AVR_IO_REGBIT(UCSR2A, UDRE2),
 216                         .vector = USART2_UDRE_vect,
 217                 },
 218         },
 219
 220         .uart3 = {
 221                 .disabled = AVR_IO_REGBIT(PRR1,PRUSART3),
 222                 .name = '3',
 223                 .r_udr = UDR3,
 224
 225                 .txen = AVR_IO_REGBIT(UCSR3B, TXEN3),
 226                 .rxen = AVR_IO_REGBIT(UCSR3B, RXEN3),
 227                 .ucsz = AVR_IO_REGBITS(UCSR3C, UCSZ30, 0x3), // 2 bits
 228                 .ucsz2 = AVR_IO_REGBIT(UCSR3B, UCSZ32),         // 1 bits
 229
 230                 .r_ucsra = UCSR3A,
 231                 .r_ucsrb = UCSR3B,
 232                 .r_ucsrc = UCSR3C,
 233                 .r_ubrrl = UBRR3L,
 234                 .r_ubrrh = UBRR3H,
 235                 .rxc = {
 236                         .enable = AVR_IO_REGBIT(UCSR3B, RXCIE3),
 237                         .raised = AVR_IO_REGBIT(UCSR3A, RXC3),
 238                         .vector = USART3_RX_vect,
 239                 },
 240                 .txc = {
 241                         .enable = AVR_IO_REGBIT(UCSR3B, TXCIE3),
 242                         .raised = AVR_IO_REGBIT(UCSR3A, TXC3),
 243                         .vector = USART3_TX_vect,
 244                 },
 245                 .udrc = {
 246                         .enable = AVR_IO_REGBIT(UCSR3B, UDRIE3),
 247                         .raised = AVR_IO_REGBIT(UCSR3A, UDRE3),
 248                         .vector = USART3_UDRE_vect,
 249                 },
 250         },
 251         .adc = {
 252                 .r_admux = ADMUX,
 253                 .mux = { AVR_IO_REGBIT(ADMUX, MUX0), AVR_IO_REGBIT(ADMUX, MUX1),
 254                                         AVR_IO_REGBIT(ADMUX, MUX2), AVR_IO_REGBIT(ADMUX, MUX3),
 255                                         AVR_IO_REGBIT(ADMUX, MUX4),AVR_IO_REGBIT(ADCSRB, MUX5),},
 256                 .ref = { AVR_IO_REGBIT(ADMUX, REFS0), AVR_IO_REGBIT(ADMUX, REFS1)},
 257                 .ref_values = { [1] = ADC_VREF_AVCC, [2] = ADC_VREF_V110, [3] = ADC_VREF_V256 },
 258
 259                 .adlar = AVR_IO_REGBIT(ADMUX, ADLAR),
 260                 .r_adcsra = ADCSRA,
 261                 .aden = AVR_IO_REGBIT(ADCSRA, ADEN),
 262                 .adsc = AVR_IO_REGBIT(ADCSRA, ADSC),
 263                 .adate = AVR_IO_REGBIT(ADCSRA, ADATE),
 264                 .adps = { AVR_IO_REGBIT(ADCSRA, ADPS0), AVR_IO_REGBIT(ADCSRA, ADPS1), AVR_IO_REGBIT(ADCSRA, ADPS2),},
 265
 266                 .r_adch = ADCH,
 267                 .r_adcl = ADCL,
 268
 269                 .r_adcsrb = ADCSRB,
 270                 .adts = { AVR_IO_REGBIT(ADCSRB, ADTS0), AVR_IO_REGBIT(ADCSRB, ADTS1), AVR_IO_REGBIT(ADCSRB, ADTS2),},
 271
 272                 .muxmode = {
 273                         [0] = AVR_ADC_SINGLE(0), [1] = AVR_ADC_SINGLE(1),
 274                         [2] = AVR_ADC_SINGLE(2), [3] = AVR_ADC_SINGLE(3),
 275                         [4] = AVR_ADC_SINGLE(4), [5] = AVR_ADC_SINGLE(5),
 276                         [6] = AVR_ADC_SINGLE(6), [7] = AVR_ADC_SINGLE(7),
 277
 278                         [ 8] = AVR_ADC_DIFF(0, 0,  10), [ 9] = AVR_ADC_DIFF(1, 0,  10),
 279                         [10] = AVR_ADC_DIFF(0, 0, 200), [11] = AVR_ADC_DIFF(1, 0, 200),
 280                         [12] = AVR_ADC_DIFF(2, 2,  10), [13] = AVR_ADC_DIFF(3, 2,  10),
 281                         [14] = AVR_ADC_DIFF(2, 2, 200), [15] = AVR_ADC_DIFF(3, 2, 200),
 282
 283                         [16] = AVR_ADC_DIFF(0, 1,   1), [17] = AVR_ADC_DIFF(1, 1,   1),
 284                         [18] = AVR_ADC_DIFF(2, 1,   1), [19] = AVR_ADC_DIFF(3, 1,   1),
 285                         [20] = AVR_ADC_DIFF(4, 1,   1), [21] = AVR_ADC_DIFF(5, 1,   1),
 286                         [22] = AVR_ADC_DIFF(6, 1,   1), [23] = AVR_ADC_DIFF(7, 1,   1),
 287
 288                         [24] = AVR_ADC_DIFF(0, 2,   1), [25] = AVR_ADC_DIFF(1, 2,   1),
 289                         [26] = AVR_ADC_DIFF(2, 2,   1), [27] = AVR_ADC_DIFF(3, 2,   1),
 290                         [28] = AVR_ADC_DIFF(4, 2,   1), [29] = AVR_ADC_DIFF(5, 2,   1),
 291
 292                         [30] = AVR_ADC_REF(1100),       // 1.1V
 293                         [31] = AVR_ADC_REF(0),          // GND
 294
 295                         [32] = AVR_ADC_SINGLE( 8), [33] = AVR_ADC_SINGLE( 9),
 296                         [34] = AVR_ADC_SINGLE(10), [35] = AVR_ADC_SINGLE(11),
 297                         [36] = AVR_ADC_SINGLE(12), [37] = AVR_ADC_SINGLE(13),
 298                         [38] = AVR_ADC_SINGLE(14), [39] = AVR_ADC_SINGLE(15),
 299
 300                         [40] = AVR_ADC_DIFF( 8,  8,  10), [41] = AVR_ADC_DIFF( 9,  8,  10),
 301                         [42] = AVR_ADC_DIFF( 8,  8, 200), [43] = AVR_ADC_DIFF( 9,  8, 200),
 302
 303                         [44] = AVR_ADC_DIFF(10, 10,  10), [45] = AVR_ADC_DIFF(11, 10,  10),
 304                         [46] = AVR_ADC_DIFF(10, 10, 200), [47] = AVR_ADC_DIFF(11, 10, 200),
 305
 306                         [48] = AVR_ADC_DIFF( 8,  9,   1), [49] = AVR_ADC_DIFF( 9,  9,   1),
 307                         [50] = AVR_ADC_DIFF(10,  9,   1), [51] = AVR_ADC_DIFF(11,  9,   1),
 308                         [52] = AVR_ADC_DIFF(12,  9,   1), [53] = AVR_ADC_DIFF(13,  9,   1),
 309                         [54] = AVR_ADC_DIFF(14,  9,   1), [55] = AVR_ADC_DIFF(15,  9,   1),
 310
 311                         [56] = AVR_ADC_DIFF( 8, 10,   1), [57] = AVR_ADC_DIFF( 9, 10,   1),
 312                         [58] = AVR_ADC_DIFF(10, 10,   1), [59] = AVR_ADC_DIFF(11, 10,   1),
 313                         [60] = AVR_ADC_DIFF(12, 10,   1), [61] = AVR_ADC_DIFF(13, 10,   1),
 314                 },
 315
 316                 .adc = {
 317                         .enable = AVR_IO_REGBIT(ADCSRA, ADIE),
 318                         .raised = AVR_IO_REGBIT(ADCSRA, ADIF),
 319                         .vector = ADC_vect,
 320                 },
 321         },
 322         .timer0 = {
 323                 .name = '0',
 324                 .wgm = { AVR_IO_REGBIT(TCCR0A, WGM00), AVR_IO_REGBIT(TCCR0A, WGM01), AVR_IO_REGBIT(TCCR0B, WGM02) },
 325                 .wgm_op = {
 326                         [0] = AVR_TIMER_WGM_NORMAL8(),
 327                         [2] = AVR_TIMER_WGM_CTC(),
 328                         [3] = AVR_TIMER_WGM_FASTPWM8(),
 329                         [7] = AVR_TIMER_WGM_OCPWM(),
 330                 },
 331                 .cs = { AVR_IO_REGBIT(TCCR0B, CS00), AVR_IO_REGBIT(TCCR0B, CS01), AVR_IO_REGBIT(TCCR0B, CS02) },
 332                 .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ },
 333
 334                 .r_tcnt = TCNT0,
 335
 336                 .overflow = {
 337                         .enable = AVR_IO_REGBIT(TIMSK0, TOIE0),
 338                         .raised = AVR_IO_REGBIT(TIFR0, TOV0),
 339                         .vector = TIMER0_OVF_vect,
 340                 },
 341                 .comp = {
 342                         [AVR_TIMER_COMPA] = {
 343                                 .r_ocr = OCR0A,
 344                                 .com = AVR_IO_REGBITS(TCCR0A, COM0A0, 0x3),
 345                                 .com_pin = AVR_IO_REGBIT(PORTB, PB7), // same as timer1C
 346                                 .interrupt = {
 347                                         .enable = AVR_IO_REGBIT(TIMSK0, OCIE0A),
 348                                         .raised = AVR_IO_REGBIT(TIFR0, OCF0A),
 349                                         .vector = TIMER0_COMPA_vect,
 350                                 },
 351                         },
 352                         [AVR_TIMER_COMPB] = {
 353                                 .r_ocr = OCR0B,
 354                                 .com = AVR_IO_REGBITS(TCCR0A, COM0B0, 0x3),
 355                                 .com_pin = AVR_IO_REGBIT(PORTG, PG5),
 356                                 .interrupt = {
 357                                         .enable = AVR_IO_REGBIT(TIMSK0, OCIE0B),
 358                                         .raised = AVR_IO_REGBIT(TIFR0, OCF0B),
 359                                         .vector = TIMER0_COMPB_vect,
 360                                 },
 361                         },
 362                 },
 363         },
 364         .timer1 = {
 365                 .name = '1',
 366                 .disabled = AVR_IO_REGBIT(PRR0,PRTIM1),
 367                 .wgm = { AVR_IO_REGBIT(TCCR1A, WGM10), AVR_IO_REGBIT(TCCR1A, WGM11),
 368                                         AVR_IO_REGBIT(TCCR1B, WGM12), AVR_IO_REGBIT(TCCR1B, WGM13) },
 369                 .wgm_op = {
 370                         [0] = AVR_TIMER_WGM_NORMAL16(),
 371                         // TODO: 1 PWM phase correct 8bit
 372                         //               2 PWM phase correct 9bit
 373                         //       3 PWM phase correct 10bit
 374                         [4] = AVR_TIMER_WGM_CTC(),
 375                         [5] = AVR_TIMER_WGM_FASTPWM8(),
 376                         [6] = AVR_TIMER_WGM_FASTPWM9(),
 377                         [7] = AVR_TIMER_WGM_FASTPWM10(),
 378                         // TODO: 8, 9 PWM phase and freq correct ICR & 10, 11
 379                         [12] = AVR_TIMER_WGM_ICCTC(),
 380                         [14] = AVR_TIMER_WGM_ICPWM(),
 381                         [15] = AVR_TIMER_WGM_OCPWM(),
 382                 },
 383                 .cs = { AVR_IO_REGBIT(TCCR1B, CS10), AVR_IO_REGBIT(TCCR1B, CS11), AVR_IO_REGBIT(TCCR1B, CS12) },
 384                 .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */  /* External clock T1 is not handled */},
 385
 386                 .r_tcnt = TCNT1L,
 387                 .r_tcnth = TCNT1H,
 388                 .r_icr = ICR1L,
 389                 .r_icrh = ICR1H,
 390
 391                 .ices = AVR_IO_REGBIT(TCCR1B, ICES1),
 392                 .icp = AVR_IO_REGBIT(PORTD, PD4),
 393
 394                 .overflow = {
 395                         .enable = AVR_IO_REGBIT(TIMSK1, TOIE1),
 396                         .raised = AVR_IO_REGBIT(TIFR1, TOV1),
 397                         .vector = TIMER1_OVF_vect,
 398                 },
 399                 .icr = {
 400                         .enable = AVR_IO_REGBIT(TIMSK1, ICIE1),
 401                         .raised = AVR_IO_REGBIT(TIFR1, ICF1),
 402                         .vector = TIMER1_CAPT_vect,
 403                 },
 404                 .comp = {
 405                         [AVR_TIMER_COMPA] = {
 406                                 .r_ocr = OCR1AL,
 407                                 .r_ocrh = OCR1AH,       // 16 bits timers have two bytes of it
 408                                 .com = AVR_IO_REGBITS(TCCR1A, COM1A0, 0x3),
 409                                 .com_pin = AVR_IO_REGBIT(PORTB, PB5),
 410                                 .interrupt = {
 411                                         .enable = AVR_IO_REGBIT(TIMSK1, OCIE1A),
 412                                         .raised = AVR_IO_REGBIT(TIFR1, OCF1A),
 413                                         .vector = TIMER1_COMPA_vect,
 414                                 },
 415                         },
 416                         [AVR_TIMER_COMPB] = {
 417                                 .r_ocr = OCR1BL,
 418                                 .r_ocrh = OCR1BH,
 419                                 .com = AVR_IO_REGBITS(TCCR1A, COM1B0, 0x3),
 420                                 .com_pin = AVR_IO_REGBIT(PORTB, PB6),
 421                                 .interrupt = {
 422                                         .enable = AVR_IO_REGBIT(TIMSK1, OCIE1B),
 423                                         .raised = AVR_IO_REGBIT(TIFR1, OCF1B),
 424                                         .vector = TIMER1_COMPB_vect,
 425                                 },
 426                         },
 427                         [AVR_TIMER_COMPC] = {
 428                                 .r_ocr = OCR1CL,
 429                                 .r_ocrh = OCR1CH,
 430                                 .com = AVR_IO_REGBITS(TCCR1A, COM1C0, 0x3),
 431                                 .com_pin = AVR_IO_REGBIT(PORTB, PB7), // same as timer0A
 432                                 .interrupt = {
 433                                         .enable = AVR_IO_REGBIT(TIMSK1, OCIE1C),
 434                                         .raised = AVR_IO_REGBIT(TIFR1, OCF1C),
 435                                         .vector = TIMER1_COMPC_vect,
 436                                 },
 437                         },
 438                 },
 439
 440         },
 441         .timer2 = {
 442                 .name = '2',
 443                 .wgm = { AVR_IO_REGBIT(TCCR2A, WGM20), AVR_IO_REGBIT(TCCR2A, WGM21), AVR_IO_REGBIT(TCCR2B, WGM22) },
 444                 .wgm_op = {
 445                         [0] = AVR_TIMER_WGM_NORMAL8(),
 446                         // TODO 1 pwm phase correct
 447                         [2] = AVR_TIMER_WGM_CTC(),
 448                         [3] = AVR_TIMER_WGM_FASTPWM8(),
 449                         [7] = AVR_TIMER_WGM_OCPWM(),
 450                 },
 451                 .cs = { AVR_IO_REGBIT(TCCR2B, CS20), AVR_IO_REGBIT(TCCR2B, CS21), AVR_IO_REGBIT(TCCR2B, CS22) },
 452                 .cs_div = { 0, 0, 3 /* 8 */, 5 /* 32 */, 6 /* 64 */, 7 /* 128 */, 8 /* 256 */, 10 /* 1024 */ },
 453
 454                 .r_tcnt = TCNT2,
 455                 // asynchronous timer source bit.. if set, use 32khz frequency
 456                 .as2 = AVR_IO_REGBIT(ASSR, AS2),
 457
 458                 .overflow = {
 459                         .enable = AVR_IO_REGBIT(TIMSK2, TOIE2),
 460                         .raised = AVR_IO_REGBIT(TIFR2, TOV2),
 461                         .vector = TIMER2_OVF_vect,
 462                 },
 463                 .comp = {
 464                         [AVR_TIMER_COMPA] = {
 465                                 .r_ocr = OCR2A,
 466                                 .com = AVR_IO_REGBITS(TCCR2A, COM2A0, 0x3),
 467                                 .com_pin = AVR_IO_REGBIT(PORTB, PB4),
 468                                 .interrupt = {
 469                                         .enable = AVR_IO_REGBIT(TIMSK2, OCIE2A),
 470                                         .raised = AVR_IO_REGBIT(TIFR2, OCF2A),
 471                                         .vector = TIMER2_COMPA_vect,
 472                                 },
 473                         },
 474             // TIMER2_COMPB is only appeared in 1280
 475                         //[AVR_TIMER_COMPB] = {
 476                         //      .r_ocr = OCR2B,
 477                         //      .com = AVR_IO_REGBITS(TCCR2A, COM2B0, 0x3),
 478                         //      .com_pin = AVR_IO_REGBIT(PORTH, PH6),
 479                         //      .interrupt = {
 480                         //              .enable = AVR_IO_REGBIT(TIMSK2, OCIE2B),
 481                         //              .raised = AVR_IO_REGBIT(TIFR2, OCF2B),
 482                         //              .vector = TIMER2_COMPB_vect,
 483                         //      },
 484                         //},
 485                 },
 486         },
 487         .timer3 = {
 488                 .name = '3',
 489                 .wgm = { AVR_IO_REGBIT(TCCR3A, WGM30), AVR_IO_REGBIT(TCCR3A, WGM31),
 490                                         AVR_IO_REGBIT(TCCR3B, WGM32), AVR_IO_REGBIT(TCCR3B, WGM33) },
 491                 .wgm_op = {
 492                         [0] = AVR_TIMER_WGM_NORMAL16(),
 493                         // TODO: 1 PWM phase correct 8bit
 494                         //       2 PWM phase correct 9bit
 495                         //       3 PWM phase correct 10bit
 496                         [4] = AVR_TIMER_WGM_CTC(),
 497                         [5] = AVR_TIMER_WGM_FASTPWM8(),
 498                         [6] = AVR_TIMER_WGM_FASTPWM9(),
 499                         [7] = AVR_TIMER_WGM_FASTPWM10(),
 500                         // TODO: 8 PWM phase and freq correct ICR
 501                         //       9 PWM phase and freq correct OCR
 502                         //       10
 503                         //       11
 504                         [12] = AVR_TIMER_WGM_ICCTC(),
 505                         [14] = AVR_TIMER_WGM_ICPWM(),
 506                         [15] = AVR_TIMER_WGM_OCPWM(),
 507                 },
 508                 .cs = { AVR_IO_REGBIT(TCCR3B, CS30), AVR_IO_REGBIT(TCCR3B, CS31), AVR_IO_REGBIT(TCCR3B, CS32) },
 509                 .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */  /* TODO: 2 External clocks */},
 510
 511                 .r_tcnt = TCNT3L,
 512                 .r_icr = ICR3L,
 513                 .r_icrh = ICR3H,
 514                 .r_tcnth = TCNT3H,
 515
 516                 .ices = AVR_IO_REGBIT(TCCR3B, ICES3),
 517                 .icp = AVR_IO_REGBIT(PORTE, PE7),
 518
 519                 .overflow = {
 520                         .enable = AVR_IO_REGBIT(TIMSK3, TOIE3),
 521                         .raised = AVR_IO_REGBIT(TIFR3, TOV3),
 522                         .vector = TIMER3_OVF_vect,
 523                 },
 524                 .comp = {
 525                         [AVR_TIMER_COMPA] = {
 526                                 .r_ocr = OCR3AL,
 527                                 .r_ocrh = OCR3AH,       // 16 bits timers have two bytes of it
 528                                 .com = AVR_IO_REGBITS(TCCR3A, COM3A0, 0x3),
 529                                 .com_pin = AVR_IO_REGBIT(PORTE, PE3),
 530                                 .interrupt = {
 531                                         .enable = AVR_IO_REGBIT(TIMSK3, OCIE3A),
 532                                         .raised = AVR_IO_REGBIT(TIFR3, OCF3A),
 533                                         .vector = TIMER3_COMPA_vect,
 534                                 }
 535                         },
 536                         [AVR_TIMER_COMPB] = {
 537                                 .r_ocr = OCR3BL,
 538                                 .r_ocrh = OCR3BH,
 539                                 .com = AVR_IO_REGBITS(TCCR3A, COM3B0, 0x3),
 540                                 .com_pin = AVR_IO_REGBIT(PORTE, PE4),
 541                                 .interrupt = {
 542                                         .enable = AVR_IO_REGBIT(TIMSK3, OCIE3B),
 543                                         .raised = AVR_IO_REGBIT(TIFR3, OCF3B),
 544                                         .vector = TIMER3_COMPB_vect,
 545                                 }
 546                         },
 547                         [AVR_TIMER_COMPC] = {
 548                                 .r_ocr = OCR3CL,
 549                                 .r_ocrh = OCR3CH,
 550                                 .com = AVR_IO_REGBITS(TCCR3A, COM3C0, 0x3),
 551                                 .com_pin = AVR_IO_REGBIT(PORTE, PE5),
 552                                 .interrupt = {
 553                                         .enable = AVR_IO_REGBIT(TIMSK3, OCIE3C),
 554                                         .raised = AVR_IO_REGBIT(TIFR3, OCF3C),
 555                                         .vector = TIMER3_COMPC_vect,
 556                                 }
 557                         }
 558                 },
 559                 .icr = {
 560                         .enable = AVR_IO_REGBIT(TIMSK3, ICIE3),
 561                         .raised = AVR_IO_REGBIT(TIFR3, ICF3),
 562                         .vector = TIMER3_CAPT_vect,
 563                 },
 564         },
 565         .timer4 = {
 566                 .name = '4',
 567                 .disabled = AVR_IO_REGBIT(PRR1,PRTIM4),
 568                 .wgm = { AVR_IO_REGBIT(TCCR4A, WGM40), AVR_IO_REGBIT(TCCR4A, WGM41),
 569                                         AVR_IO_REGBIT(TCCR4B, WGM42), AVR_IO_REGBIT(TCCR4B, WGM43) },
 570                 .wgm_op = {
 571                         [0] = AVR_TIMER_WGM_NORMAL16(),
 572                         // TODO: 1 PWM phase correct 8bit
 573                         //               2 PWM phase correct 9bit
 574                         //       3 PWM phase correct 10bit
 575                         [4] = AVR_TIMER_WGM_CTC(),
 576                         [5] = AVR_TIMER_WGM_FASTPWM8(),
 577                         [6] = AVR_TIMER_WGM_FASTPWM9(),
 578                         [7] = AVR_TIMER_WGM_FASTPWM10(),
 579                         // TODO: 8, 9 PWM phase and freq correct ICR & 10, 11
 580                         [12] = AVR_TIMER_WGM_ICCTC(),
 581                         [14] = AVR_TIMER_WGM_ICPWM(),
 582                         [15] = AVR_TIMER_WGM_OCPWM(),
 583                 },
 584                 .cs = { AVR_IO_REGBIT(TCCR4B, CS40), AVR_IO_REGBIT(TCCR4B, CS41), AVR_IO_REGBIT(TCCR4B, CS42) },
 585                 .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */  /* External clock T1 is not handled */},
 586
 587                 .r_tcnt = TCNT4L,
 588                 .r_tcnth = TCNT4H,
 589                 .r_icr = ICR4L,
 590                 .r_icrh = ICR4H,
 591
 592                 .ices = AVR_IO_REGBIT(TCCR4B, ICES4),
 593                 .icp = AVR_IO_REGBIT(PORTL, PL0),
 594
 595                 .overflow = {
 596                         .enable = AVR_IO_REGBIT(TIMSK4, TOIE4),
 597                         .raised = AVR_IO_REGBIT(TIFR4, TOV4),
 598                         .vector = TIMER4_OVF_vect,
 599                 },
 600                 .icr = {
 601                         .enable = AVR_IO_REGBIT(TIMSK4, ICIE4),
 602                         .raised = AVR_IO_REGBIT(TIFR4, ICF4),
 603                         .vector = TIMER4_CAPT_vect,
 604                 },
 605                 .comp = {
 606                         [AVR_TIMER_COMPA] = {
 607                                 .r_ocr = OCR4AL,
 608                                 .r_ocrh = OCR4AH,       // 16 bits timers have two bytes of it
 609                                 .com = AVR_IO_REGBITS(TCCR4A, COM4A0, 0x3),
 610                                 .com_pin = AVR_IO_REGBIT(PORTH, PH3),
 611                                 .interrupt = {
 612                                         .enable = AVR_IO_REGBIT(TIMSK4, OCIE4A),
 613                                         .raised = AVR_IO_REGBIT(TIFR4, OCF4A),
 614                                         .vector = TIMER4_COMPA_vect,
 615                                 },
 616                         },
 617                         [AVR_TIMER_COMPB] = {
 618                                 .r_ocr = OCR4BL,
 619                                 .r_ocrh = OCR4BH,
 620                                 .com = AVR_IO_REGBITS(TCCR4A, COM4B0, 0x3),
 621                                 .com_pin = AVR_IO_REGBIT(PORTH, PH4),
 622                                 .interrupt = {
 623                                         .enable = AVR_IO_REGBIT(TIMSK4, OCIE4B),
 624                                         .raised = AVR_IO_REGBIT(TIFR4, OCF4B),
 625                                         .vector = TIMER4_COMPB_vect,
 626                                 },
 627                         },
 628                         [AVR_TIMER_COMPC] = {
 629                                 .r_ocr = OCR4CL,
 630                                 .r_ocrh = OCR4CH,
 631                                 .com = AVR_IO_REGBITS(TCCR4A, COM4C0, 0x3),
 632                                 .com_pin = AVR_IO_REGBIT(PORTH, PH5),
 633                                 .interrupt = {
 634                                         .enable = AVR_IO_REGBIT(TIMSK4, OCIE4C),
 635                                         .raised = AVR_IO_REGBIT(TIFR4, OCF4C),
 636                                         .vector = TIMER4_COMPC_vect,
 637                                 },
 638                         },
 639                 },
 640
 641         },
 642         .timer5 = {
 643                 .name = '5',
 644                 .disabled = AVR_IO_REGBIT(PRR1,PRTIM5),
 645                 .wgm = { AVR_IO_REGBIT(TCCR5A, WGM50), AVR_IO_REGBIT(TCCR5A, WGM51),
 646                                         AVR_IO_REGBIT(TCCR5B, WGM52), AVR_IO_REGBIT(TCCR5B, WGM53) },
 647                 .wgm_op = {
 648                         [0] = AVR_TIMER_WGM_NORMAL16(),
 649                         // TODO: 1 PWM phase correct 8bit
 650                         //               2 PWM phase correct 9bit
 651                         //       3 PWM phase correct 10bit
 652                         [4] = AVR_TIMER_WGM_CTC(),
 653                         [5] = AVR_TIMER_WGM_FASTPWM8(),
 654                         [6] = AVR_TIMER_WGM_FASTPWM9(),
 655                         [7] = AVR_TIMER_WGM_FASTPWM10(),
 656                         // TODO: 8, 9 PWM phase and freq correct ICR & 10, 11
 657                         [12] = AVR_TIMER_WGM_ICCTC(),
 658                         [14] = AVR_TIMER_WGM_ICPWM(),
 659                         [15] = AVR_TIMER_WGM_OCPWM(),
 660                 },
 661                 .cs = { AVR_IO_REGBIT(TCCR5B, CS50), AVR_IO_REGBIT(TCCR5B, CS51), AVR_IO_REGBIT(TCCR5B, CS52) },
 662                 .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */  /* External clock T1 is not handled */},
 663
 664                 .r_tcnt = TCNT5L,
 665                 .r_tcnth = TCNT5H,
 666                 .r_icr = ICR5L,
 667                 .r_icrh = ICR5H,
 668
 669                 .ices = AVR_IO_REGBIT(TCCR5B, ICES5),
 670                 .icp = AVR_IO_REGBIT(PORTL, PL1),
 671
 672                 .overflow = {
 673                         .enable = AVR_IO_REGBIT(TIMSK5, TOIE5),
 674                         .raised = AVR_IO_REGBIT(TIFR5, TOV5),
 675                         .vector = TIMER5_OVF_vect,
 676                 },
 677                 .icr = {
 678                         .enable = AVR_IO_REGBIT(TIMSK5, ICIE5),
 679                         .raised = AVR_IO_REGBIT(TIFR5, ICF5),
 680                         .vector = TIMER5_CAPT_vect,
 681                 },
 682                 .comp = {
 683                         [AVR_TIMER_COMPA] = {
 684                                 .r_ocr = OCR5AL,
 685                                 .r_ocrh = OCR5AH,       // 16 bits timers have two bytes of it
 686                                 .com = AVR_IO_REGBITS(TCCR5A, COM5A0, 0x3),
 687                                 .com_pin = AVR_IO_REGBIT(PORTL, PL3),
 688                                 .interrupt = {
 689                                         .enable = AVR_IO_REGBIT(TIMSK5, OCIE5A),
 690                                         .raised = AVR_IO_REGBIT(TIFR5, OCF5A),
 691                                         .vector = TIMER5_COMPA_vect,
 692                                 },
 693                         },
 694                         [AVR_TIMER_COMPB] = {
 695                                 .r_ocr = OCR5BL,
 696                                 .r_ocrh = OCR5BH,
 697                                 .com = AVR_IO_REGBITS(TCCR5A, COM5B0, 0x3),
 698                                 .com_pin = AVR_IO_REGBIT(PORTL, PL4),
 699                                 .interrupt = {
 700                                         .enable = AVR_IO_REGBIT(TIMSK5, OCIE5B),
 701                                         .raised = AVR_IO_REGBIT(TIFR5, OCF5B),
 702                                         .vector = TIMER5_COMPB_vect,
 703                                 },
 704                         },
 705                         [AVR_TIMER_COMPC] = {
 706                                 .r_ocr = OCR5CL,
 707                                 .r_ocrh = OCR5CH,
 708                                 .com = AVR_IO_REGBITS(TCCR5A, COM5C0, 0x3),
 709                                 .com_pin = AVR_IO_REGBIT(PORTL, PL5),
 710                                 .interrupt = {
 711                                         .enable = AVR_IO_REGBIT(TIMSK5, OCIE5C),
 712                                         .raised = AVR_IO_REGBIT(TIFR5, OCF5C),
 713                                         .vector = TIMER5_COMPC_vect,
 714                                 },
 715                         },
 716                 },
 717
 718         },
 719         .spi = {
 720                 .disabled = AVR_IO_REGBIT(PRR0,PRSPI),
 721
 722                 .r_spdr = SPDR,
 723                 .r_spcr = SPCR,
 724                 .r_spsr = SPSR,
 725
 726                 .spe = AVR_IO_REGBIT(SPCR, SPE),
 727                 .mstr = AVR_IO_REGBIT(SPCR, MSTR),
 728
 729                 .spr = { AVR_IO_REGBIT(SPCR, SPR0), AVR_IO_REGBIT(SPCR, SPR1), AVR_IO_REGBIT(SPSR, SPI2X) },
 730                 .spi = {
 731                         .enable = AVR_IO_REGBIT(SPCR, SPIE),
 732                         .raised = AVR_IO_REGBIT(SPSR, SPIF),
 733                         .vector = SPI_STC_vect,
 734                 },
 735         },
 736
 737         .twi = {
 738
 739                 .r_twcr = TWCR,
 740                 .r_twsr = TWSR,
 741                 .r_twbr = TWBR,
 742                 .r_twdr = TWDR,
 743                 .r_twar = TWAR,
 744                 .r_twamr = TWAMR,
 745
 746                 .twen = AVR_IO_REGBIT(TWCR, TWEN),
 747                 .twea = AVR_IO_REGBIT(TWCR, TWEA),
 748                 .twsta = AVR_IO_REGBIT(TWCR, TWSTA),
 749                 .twsto = AVR_IO_REGBIT(TWCR, TWSTO),
 750                 .twwc = AVR_IO_REGBIT(TWCR, TWWC),
 751
 752                 .twsr = AVR_IO_REGBITS(TWSR, TWS3, 0x1f),       // 5 bits
 753                 .twps = AVR_IO_REGBITS(TWSR, TWPS0, 0x3),       // 2 bits
 754
 755                 .twi = {
 756                         .enable = AVR_IO_REGBIT(TWCR, TWIE),
 757                         .raised = AVR_IO_REGBIT(TWCR, TWINT),
 758                         .raise_sticky = 1,
 759                         .vector = TWI_vect,
 760                 },
 761         },
 762
 763 };
 764
 765 static avr_t * make()
 766 {
 767         return avr_core_allocate(&mcu_mega1280.core, sizeof(struct mcu_t));
 768 }
 769
 770 avr_kind_t mega1280 = {
 771         .names = { "atmega1280" },
 772         .make = make
 773 };
 774
 775 void m1280_init(struct avr_t * avr)
 776 {
 777         struct mcu_t * mcu = (struct mcu_t*)avr;
 778
 779         avr_eeprom_init(avr, &mcu->eeprom);
 780         avr_flash_init(avr, &mcu->selfprog);
 781         avr_extint_init(avr, &mcu->extint);
 782         avr_watchdog_init(avr, &mcu->watchdog);
 783         avr_ioport_init(avr, &mcu->porta);
 784         avr_ioport_init(avr, &mcu->portb);
 785         avr_ioport_init(avr, &mcu->portc);
 786         avr_ioport_init(avr, &mcu->portd);
 787         avr_ioport_init(avr, &mcu->porte);
 788         avr_ioport_init(avr, &mcu->portf);
 789         avr_ioport_init(avr, &mcu->portg);
 790         avr_ioport_init(avr, &mcu->porth);
 791         avr_ioport_init(avr, &mcu->portj);
 792         avr_ioport_init(avr, &mcu->portk);
 793         avr_ioport_init(avr, &mcu->portl);
 794
 795         avr_uart_init(avr, &mcu->uart0);
 796         avr_uart_init(avr, &mcu->uart1);
 797         avr_uart_init(avr, &mcu->uart2);
 798         avr_uart_init(avr, &mcu->uart3);
 799         avr_adc_init(avr, &mcu->adc);
 800         avr_timer_init(avr, &mcu->timer0);
 801         avr_timer_init(avr, &mcu->timer1);
 802         avr_timer_init(avr, &mcu->timer2);
 803         avr_timer_init(avr, &mcu->timer3);
 804         avr_timer_init(avr, &mcu->timer4);
 805         avr_timer_init(avr, &mcu->timer5);
 806         avr_spi_init(avr, &mcu->spi);
 807         avr_twi_init(avr, &mcu->twi);
 808 }
 809
 810 void m1280_reset(struct avr_t * avr)
 811 {
 812 //      struct mcu_t * mcu = (struct mcu_t*)avr;
 813 }